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This application report contains implementation instructions for the DDR2 interface contained on the TCI6482 DSP device. The approach to specifying interface timing for the DDR2 interface is quite different than on previous devices.

The previous approach specified device timing in terms of data sheet specifications and simulation models. The customer was required to obtain compatible memory devices, as well as their data sheets and simulation models. The customer would then take this information and design their printed circuit board (PCB) using high speed simulation to close system timing.

For the TCI6482 DDR2 interface, the approach is to specify compatible DDR2 devices and provide the PCB routing rule solution directly to the customer. TI has performed the simulation and system design work to ensure DDR2 interface timings are met. The DDR2 system solution is referred to as the TCI6482 DDR2 collateral. This document describes the content of this collateral.

The TCI6482 DSK and EVM provide example PCB layouts following these routing rules that pass FCC EMI requirements. The DSK contains a single TCI6482 device and the EVM is a DSK with an attached daughter card containing another TCI6482 device. Both DDR2 layouts on the DSK/EVM meet the routing rules detailed in this document. The customer may copy these DDR2 layouts directly, but the intent is to allow enough flexibility in the routing rules to meet other PCB requirements and allow the customer to derive an optimized layout for their specific application.