This document contains implementation instructions for the three serializer/deserializer (SERDES) based interfaces on the TMS320C6474 DSP device. These include the Serial RapidIO® (SRIO), antenna, and serial gigabit media independent interface (SGMII) interfaces.
Serial RapidIO is an industry-standard high-speed switched-packet interconnect. The antenna interface is compatible with two industry standards targeted at cellular base station solutions; Open Base Station Architecture Initiative (OBSAI) and Common Public Radio Interface (CPRI). SGMII is a standard used for gigabit Ethernet connections from MAC to MAC or MAC to PHY.
For each of these interfaces, physical layer data transmission utilizes analog SERDES to feed low-output-swing differential current-mode logic (CML) buffers. Proper printed circuit board (PCB) design for these interfaces resembles analog or RF design, and is very different than traditional parallel digital bus design.
Due to this analog nature of SERDES based interfaces, it is not possible to specify the interface in a traditional DSP digital interface manner. Furthermore, it is undesirable to specify the interface in terms of the raw physical requirements laid out by the industry standard specifications. Understanding these specifications and producing a compliant PCB based on the explicit and implicit requirements there demands significant time, experience, and expensive tools.
For the C6474 SERDES based interfaces, the approach is to reduce the specifications to a set of easy-to-follow PCB routing rules and system configurations. TI has performed the simulation and system design work to ensure the appropriate interface requirements are met. This document describes guidelines that, when followed, result in board level implementations that meet the interface requirements.