The initialization of the DDR3 DRAM controller on KeyStone I DSPs is straightforward as long as the proper steps are followed. However, if some steps are omitted or if some sequence-sensitive steps are implemented in the wrong order, DDR3 operation will be unpredictable.
All DDR3 initialization routines must contain the basic register writes to configure the memory controller within the DSP as well as register writes that configure the mode registers within the attached DRAM devices. The data sheet for the DRAM implemented must be referenced to optimize these values.
DDR3 implementations use a fly-by routing topology, PCB track lengths for the fly-by signals (Address, Command, Control, and Clock) and data group signals (DQ, DQS, and DQM) must be available to properly initialize the leveling registers.