Search reference designs by application or product type

Find your solution now

Applications

Products

Additional resources

AND OR

Description

For modern radar system developers currently using an FPGA or ASIC to connect to high speed data converters, who need faster time to market with increased performance and significant reduction in cost, power, and size, this reference design includes the first widely available processor integrating a (...)

Key Features

  • Easy integration of signal processor to data converters over JESD204B
  • Sampling of a single 100MHz channel, when connected to ADC14X250
  • DFE processing for filtering, down-sampling or up-sampling; FFTC hardware accelerator to offload compute-intensive 2D FFT operations, achieving low latency and high (...)

Description

This reference design features the industry's first zero-crossover and zero-drift amplifier (OPA388) to buffer the analog output of a digital-to-analog converter (DAC). It demonstrates the importance of the zero-crossover and zero-drift feature and how they can minimize the integral non-linearity (...)

Key Features

  • Precision DAC (DAC8830) provides excellent linearity, low glitch, low noise and fast setting
  • Operates at 2.7-5.5 V single-supply, which is compatible with most DSP/MCU power requirements
  • Zero-crossover, zero-drift op amp (OPA388) provides true precision to minimize contributions to DAC INL (<0.5 LSB)

Description

OPC UA is an industrial machine-to-machine protocol designed to allow interoperability and communication between all machines connected under Industry 4.0. The TIDEP0078 TI Design demonstrates use of the MatrikonOPC™ OPC UA server development kit (SDK) to allow communications using an OPC UA (...)

Key Features

  • Fully embedded OPC UA server running on Sitara AM57x processor
  • Matrikon OPC UA server development kit (SDK) R100 and sample OPC UA server (demo version is time limited to two hours)
  • Linux operating environment through Processor-SDK-Linux
  • Control GPIO read/write over TCP/IP from OPC UA sample client (...)

Description

The PMP40071 is a POL module reference design suitable for DSP & FPGA applications with a DC input of 8.3V – 14V. Its ultra-high power density can help the power system to handle a high power delivery while keep a small profile. It provides a good design flexibility for different (...)

Key Features

  • Ultra-high power density up to 548W/in³
  • Tunable output voltage
  • Fully tested to comply with the industrial requirement (including high and low temperature)
  • Built-in protection and compensation
  • Small dimension:  22.6mm x 11.6mm x 8.4mm

Design Parameters

 
 
Vin (V) (Min)
Vin (V) (Min)
Vin (V) (Max)
Vin (V) (Max)
Vout (V) (Nom)
Vout (V) (Nom)
Iout (A) (Max)
Iout (A) (Max)
Output Power (W)
Output Power (W)
Isolated/Non-Isolated
Isolated/Non-Isolated
Input Type
Input Type
Topology
Topology
Designed for
Designed for
PMP40071.1
(Output Voltage 1)
8.3 14 1.2 10 12 Non-Isolated DC Buck- Synchronous
PMP40071.2
(Output Voltage 2)
8.3 14 1.2 10 12 Non-Isolated DC Buck- Synchronous

Description

For wideband receiver system developers currently using FPGA or ASIC to connect High Speed data converters to a baseband processor, who need faster time to market with increased performance and significant reduction in cost, power, and size. This reference design includes the first widely available (...)

Key Features

  • Easy integration of signal processor to data converters over JESD204B
  • Usable bandwidth of two 75MHz channels or a single 100MHz channel when connected to ADC32RF80
  • DFE processing for filtering, down-sampling or up-sampling:  FFTC hardware accelerator to offload comput-intensive 2D FFT operation (...)

Description

The TIDEP0070 reference design describes system considerations for Dual Data Rate (DDR) memory interface with Error Correcting Code (ECC) support in high-reliability applications, based on the 66AK2G02 Multicore DSP + ARM processor System-on-Chip (SoC).  It enables developers to implement a (...)

Key Features

  • Optimized high speed signal routing
  • Surface-mount PCIe x1 socket
  • Example of AC coupling capacitor placement
  • Example of recommended differential pair spacing

Description

PCI-Express provides for low pin-count, high reliability, and high-speed with data transfer at rates of up to 5.0 Gbps per lane, per direction, and an PCIe module is included on the TI 66AK2G02 DSP + ARM Processor system on chip (SoC).  This PCIe PCB design considerations reference design  (...)

Key Features

  • Optimized High Speed Signal Routing
  • Surface-Mount PCIe x1 Socket
  • Example of AC Coupling Capacitor Placement
  • Example of Recommended Differential Pair Spacing

Description

TI’s high performance ARM® Cortex®-A15 based AM57x processors also integrate C66x DSPs. These DSPs were designed to handle high signal and data processing tasks that are often required by industrial, automotive and financial applications. The AM57x OpenCL implementation makes it easy (...)

Key Features

  • The TIDEP0046 TI reference design uses OpenCL that does not require the user to be a DSP expert.
  • It provides an example of Monte-Carlo algorithm to generate Gaussian random sequences which runs faster on the C66x DSP than on the ARM Cortex-A15 core.
  • It is a complete system reference design with (...)

Description

This TI Design (TIDEP0047) is a reference platform based on the AM57x processor and companion TPS659037 power management integrated circuit (PMIC).  This TI Design specifically highlights important power and thermal design considerations and techniques for systems designed with AM57x and (...)

Key Features

  • AM57x processor with Dual ARM Cortex-A15, C66x DSP, ARM Cortex-M4, SGX544 graphics, and quad core PRU-ICSS feature set
  • TPS659037 companion PMIC
  • Design reference for PMIC, PDN, and Thermal
  • Power Estimation Tool (PET) for estimating system power and Power consumption summary
  • This reference design is (...)

Design Parameters

 
 
Vin (V) (Min)
Vin (V) (Min)
Vin (V) (Max)
Vin (V) (Max)
Vout (V) (Nom)
Vout (V) (Nom)
Iout (A) (Max)
Iout (A) (Max)
Output Power (W)
Output Power (W)
Isolated/Non-Isolated
Isolated/Non-Isolated
Input Type
Input Type
Topology
Topology
Designed for
Designed for
TIDEP0047.1
(Output
Voltage1)
Processor

Description

For developers currently using an FPGA or ASIC to connect to high speed data converters who need faster time to market with increased performance and significant reduction in cost, power, and size this reference design includes the first widely available processor integrating a JESD204B interface (...)

Key Features

  • Easy integration of signal processor to data converters over JESD204B
  • Multichannel sampling rates up to 368Msps with 150MHz of processing bandwidth
  • Also available: DFE Signal Processing Bypass mode configuration from Azcom Technology (Ecosystem partner). Please request it here.
  • DFE processing for (...)

View the Important Notice for TI Designs covering authorized use, intellectual property matters and disclaimers.