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Description

The TIDEP0084 reference design demonstrates how to connect sensors to the cloud over a long-range Sub-1 GHz wireless network, suitable for industrial settings such as building control and asset tracking. It is powered by a TI Sitara™ AM335x processor and the SimpleLink™ Sub-1 GHz (...)

Key Features

  • Large network to cloud connectivity enabling long range, up to 1 km line of sight (LOS)
  • IEEE 802.15.4e/g standards based Sub-1 GHz solution with the TI 15.4-stack SDK
  • Based on proven hardware designs enabling quick time to market with out-of-the-box ready to use demonstration software
  • TI Processor SDK (...)

Description

OPC UA is an industrial machine-to-machine protocol designed to allow interoperability and communication between all machines connected under Industry 4.0. The TIDEP0078 TI Design demonstrates use of the MatrikonOPC™ OPC UA server development kit (SDK) to allow communications using an OPC UA (...)

Key Features

  • Fully embedded OPC UA server running on Sitara AM57x processor
  • Matrikon OPC UA server development kit (SDK) R100 and sample OPC UA server (demo version is time limited to two hours)
  • Linux operating environment through Processor-SDK-Linux
  • Control GPIO read/write over TCP/IP from OPC UA sample client (...)

Description

The TIDEP-0086 reference design implements a Simple Open Real-Time Ethernet (SORTE) master with the Programmable Real-time Unit and Industrial Communication Subsystem (PRU-ICSS). SORTE enables customer applications to exchange process data between the master and devices in a 4 µs cycle time (...)

Key Features

  • SORTE device reference implementation
  • Enables 4 µs cycle time to exchange process data
  • PRU firmware provided in source code
  • Fully customizable PRU firmware

Description

Designers can save board space, cost and reduce power consumption by following DDR3 guidelines without VTT termination. This reference design shows how to do that with AM437x. This type of design is not for everyone as there are certain restrictions. Having short trace lengths, a maximum of two DDR3 (...)

Key Features

  • System optimized DDR3/DDR3L design on Sitara AM437x processor with integrated DDR controller
  • Optimized layout requires no VTT termination
  • Two 4-Gbit DDR3 / DDR3L memories
  • Up to 400 MHz clock (DDR-800 data rate)
  • Complete sub-system reference with schematics, BOM, design files and HW User's Guide (...)

Description

The TIDEP0061 reference design implements an application example of an 4-axis CNC router with 250 kHz control loop based on the Simple Open Real-Time Ethernet (SORTE) protocol with the Programmable Real-time Unit and Industrial Communication SubSystem (PRU-ICSS). SORTE enables customer applications (...)

Key Features

  • 4-axis CNC router application example driving stepper motors
  • Based on SORTE protocol
  • Enables 4 µs cycle time to exchange process data
  • PRU firmware provided in source code
  • Fully customizable PRU firmware

Description

The TIDA-00179 reference design is an EMC compliant universal digital interface to connect to absolute position encoders, like EnDat 2.2, BiSS®, SSI or HIPERFACE DSL®.  The design supports a wide input voltage range from 15-60V (24V nom). A connector with 3.3V logic I/O signals allows (...)

Key Features

  • Universal Hardware to Interface to EnDat 2.2, BiSS, SSI and 4-Wire or 2-Wire HIPERFACE DSL Encoders. Supports All Corresponding Standard Data Rates up to at least 100m Cable Length.
  • 3.3-V Supply Half-Duplex RS485 Transceiver SN65HVD78 with 12kV IEC-ESD and 4kV EFT Eliminates Cost for External ESD (...)

Description

Impelementation of BiSS C Master protocol on Industrial Communication Sub-System (PRU-ICSS). The design provides full documentation and source code for Programmable Realtime Unit (PRU).

Key Features

  • BiSS C Master protocol running on ICSS
  • Interface speed of 1, 2, 5 and 10 MHz
  • 8x oversampled input capture
  • Line delay compensation with filtered sample point
  • De-bouncing filter on oversampled input
  • Variable frame format with crc check
  • Command (CDS/CDM) interface
  • Supports up to 100 m cable
  • Runs on AM335x and (...)

Description

This TI Design implements a hardware interface solution based on the HEIDENHAIN EnDat 2.2 standard for position or rotary encoders. The building blocks include the power supply for the encoder – with innovative smart e-Fuse technology - and robust half-duplex RS485 transceivers, including line (...)

Key Features

  • Design meets EMC immunity requirements for ESD, Fast Transient Burst and Surge according to IEC61800-3
  • High-speed RS-485 transceivers robust to 15kV ESD immunity
  • Wide input (15-30VDC) high-efficiency (>85%) DCDC power supply configurable from 3.6V to 14V (defaulted to 8V) with 200mA, low-ripple (...)

Description

This reference design enables a cost-effective and low-power data acquisition system that provides an alternative to FPGA-based systems. It features a single-ended, high-impedance input that can be used in a wide number of applications, including portable instrumentation and digitizers.

The reference (...)

Key Features

  • Single-ended-to-differential data acquisition reference design using the OPA656 and THS4541 op amps
  • Low-power (330/channel) operation suitable for handheld devices
  • Option to choose between 50 ohm / 1 Mohm input impedance
  • Low system cost; replaces FPGA for data capture with Sitara™ processor (...)

Description

TI provides the system solution for Industrial Communication on Sitara™ processors with Programmable Real-Time Unit and Industrial Communication Subsystem (PRU-ICSS). This TI Design describes the integrated multi-protocol digital position encoder master interface support. The supported digital (...)

Key Features

  • Multi-protocol digital position encoder master interface
  • Supports EnDat 2.2, Hiperface DSL and BiSS C digital position encoder interfaces
  • For integrated single chip drives, servo drives and remote position encoder master devices
  • Digital position encoder master interface is supported by the PRU-ICSS (...)

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