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Tutorial G - DM6467 & OMAP3530 Architecture and Programming

Registration Cost : Rs 5000/- per person
Tutorial Duration: 2 days
Date: November 3–4, 2008 (Monday-Tuesday)
Venue Details: C 2 - 7, Texas Instruments,
Bagmane Tech Park, CV Raman Nagar,
Bangalore 560093
Total Seats Available: 25

Who is this tutorial for?

This tutorial is designed for DSP software and systems engineers with an interest in programming the DM6467 and OMAP3530 DSPs. The focus of the tutorial will be on the architecture of the device, utilization of device capabilities and programming. The tutorial will be primarily focused on implementation of video codecs and optimization tips for utilization of memories and DMA.

Prerequisites

Must have:

  • Basic knowledge of DSP concepts and C programming
  • Prior exposure to CCS and any TI DSP Family tools (compiler, assembler, linker).

Nice to have:

  • C6000 Architecture.
  • Exposure to basics of cache and DMA of any DSP

What to expect from the tutorial?

  • Understanding of the architecture of the DM6467, OMAP3530
  • Programming on DM6467, OMAP3530
  • Techniques for optimization using device capabilities primarily for video codecs

Detailed Agenda

Agenda (Day 1)

  • Welcome & TI Roadmap on accelerator based devices
  • Introduction to DM6467 architecture – Capabilities, CPU
  • Programming Guidelines – Utilization of device capabilities, DMA and Cache
  • Programming Examples – Walk through of small pieces of software

Agenda (Day 2)

  • Introduction to OMAP3530 architecture – Capabilities, CPU
  • Programming Guidelines – Utilization of device capabilities, DMA and Cache
  • Programming Examples – Walk through of small pieces of software

Trainer Profiles

Krishnakanth Rapaka is Software Systems engineer working in Multimedia Codec’s division, Texas Instruments, India. He has worked extensively on development of Video Codec’s from architecture definition, pre-silicon development to codec productization on Co-processor and 64x+ based SoC platforms like IVAHD, DM6467, DM510 and Davinci. Prior to TI, Krishna worked for Infosys Technologies on development of Video Codec’s on Intel & MAC architectures. He holds a B.E in Electronics and Communication from Visveswaraiah Tech University, India. Areas of Interest: Parallel video Architectures, Platform/System Modelling, Video Algorithms.

Kapil Ahuja received a bachelor’s degree in Electronics and Communication from Gitam College of Engineering, Visakhapatnam and a master’s degree in Electrical Engineering from Southern Methodist University, Dallas, USA. He has been working with the Multimedia Codec’s Group, Texas Instruments, Bangalore, India since 2004. Currently, he is actively involved in the development and optimization of video codec’s on the DM6467 SoC. Areas of Interest: Video Sub-system Architecture of TI SoCs, Transcoding.

Yashwant Dutt received a bachelor’s degree in Electronics and Communication from Birla Institute of Technology, Ranchi. He is working with the Multimedia Codec Group, Texas Instruments, Bangalore, India since 2006. He is actively involved in the development of optimized video codecs and algorithms on several TI platforms based on ARM and H/W accelerators. He is currently involved with development of optimized video codecs on the DM510 and DM365 based devices primarily targeting mobile, video conferencing and security market. His areas of interest includes video system architecture and codec optimization.

Pramod Kumar Swami graduated from REC Jaipur in 2001 (Electronics and Communication Engineering). Since then he has been working on design and development of video codec’s on different platforms which includes Intel P4, Apple’s G4, TI processors (6415, DM642, Davinci, OMAP2, OMAP3). He is also involved in defining architecture of TI's future video coding SoCs. His interest involves architecture definition for video SoCs and implementing optimized video algorithm on those. He joined Texas Instruments in 2004 and his earlier tenure was with Infosys Technologies Limited Bangalore.

Keshava Prasad received the B.E degree in electronics and communication engineering from Mysore University in 1997 and Masters (M.Tech) from IIT Kanpur in 2001. After graduation, he joined Agere Systems where he worked on DSP algorithms for speech compression, noise filtering and echo cancellation. In 2004 he joined Multimedia codecs group in Texas Instruments, where he works on video compression/video processing algorithms and their implementation on TI Platforms. His main areas of interest include video compression, DSP algorithms for video processing and Speech signal processing.

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