Waived DRC Error Report
C:/srf04/Agama/Agama_Lite_EM_Designs/CC1311-R3EM-5XD7793/Cadence/allegro/CC1311-R3EM-5XD7793.brd
Tue Feb 23 16:25:58 2021

DRC Error Count Summary
DRC Error Type,DRC Error Count
Package to Package,1
Etch to Pad,1
Total DRC Errors,2

Detailed DRC Errors
Constraint Name,DRC Marker Location,Required Value,Actual Value,Constraint Source,Constraint Source Type,Element 1,Element 2,Comment
Package to Package Spacing,(130.988 120.662),0 MM,0.4 MM,NONE,DESIGN,Shape "R11  Package Geometry/Place_Bound_Top",Shape "R12  Package Geometry/Place_Bound_Top",SMA/PCB selector resistor
Shape to SMD Pin Spacing,(125.430 127.195),0.15 MM,0 MM,DEFAULT,NET SPACING CONSTRAINTS,Shape "Dummy Net  Etch/Top",Pin "A1.1 (N485535)",PCB antenna

