Xilinx Design Summary

BIG3GIG Partition Summary
No partition information was found.

Device Utilization Summary
Logic Utilization	Used	Available	Utilization	Note(s)
Number of Slice Flip Flops	880	12,288	7%
Number of 4 input LUTs	340	12,288	2%
Logic Distribution
Number of occupied Slices	672	6,144	10%
Number of Slices containing only related logic	672	672	100%
Number of Slices containing unrelated logic	0	672	0%
Total Number 4 input LUTs	673	12,288	5%
Number used as logic	340
Number used as a route-thru	138
Number used as Shift registers	195
Number of bonded IOBs	116	240	48%
Number of BUFG/BUFGCTRLs	5	32	15%
Number used as BUFGs	5
Number used as BUFGCTRLs	0
Number of FIFO16/RAMB16s	21	48	43%
Number used as FIFO16s	0
Number used as RAMB16s	21
Number of DCM_ADVs	2	4	50%
Number of BSCAN_VIRTEX4s	1	4	25%
Number of RPM macros	13
Total equivalent gate count for design	1,399,779
Additional JTAG gate count for IOBs	5,568

Performance Summary
Final Timing Score:	0	Pinout Data:	Pinout Report
Routing Results:	All Signals Completely Routed	Clock Data:	Clock Report
Timing Constraints:	All Constraints Met