## AON

Instance: AON
Component: AON_WUC
Base address: 0x60000000

### TOP:AON Register Summary

Register Name | Type | Register Width (Bits) | IR
SECURITY_OBS | RO | 8 | 0
SECURITY_CTRL | WO | 8 | 1
SYSCTRL | WO | 28 | 2
SYSCTRL_OBS | RO | 28 | 3
SYSCTRL_OR | WO | 28 | 3
MISC | WO | 9 | 4
MISC_OBS | RO | 9 | 5
MISC_OR | WO | 9 | 5
MCUVD | WO | 19 | 6
MCUVD_OBS | RO | 19 | 7
MCUVD_OR | WO | 19 | 7
CLK | WO | 9 | 8
CLK_OBS | RO | 9 | 9
CLK_OR | WO | 9 | 9
AUXVD | WO | 12 | 10
AUXVD_OBS | RO | 12 | 11
AUXVD_OR | WO | 12 | 11
TMS_CTRL | WO | 7 | 12
PSCON_CTRL | WO | 5 | 13

### TOP:AON Register Descriptions

### TOP:AON_WUC:SECURITY_OBS

IR | 0
Description |
Type | RO

Bits | Field Name | Description | Type | Reset
7 | RES7 | Reserved for future use | RO | 0
6 | RES6 | Reserved for future use | RO | 0
5 | RES5 | Reserved for future use | RO | 0
4 | RES4 | Reserved for future use | RO | 0
3 | RES3 | Reserved for future use | RO | 0
2 | RES2 | Reserved for future use | RO | 0
1 | RES1 | Reserved for future use | RO | 0
0 | BDACK | Back door key acknowledge | RO | 0

### TOP:AON_WUC:SECURITY_CTRL

IR | 1
Description |
Type | WO

Bits | Field Name | Description | Type | Reset
7 | RES7 | Reserved | WO | 0
6 | RES6 | Reserved | WO | 0
5 | MCU_RESET_REQ | Mcu reset request | WO | 0
4 | AUX_RESET_REQ | Aux reset request | WO | 0
3 | BDRDY | Backdoor ready. ( bddat is read after this signal rises) | WO | 0
2 | BDDAT | Backdoor data. The device can be unlocked at TI premises if customer allows so. Secondly the backdoor has to be opened in order to perform a total erase. The protocol to open the backdoor is as follows: (described in pseudo code) For I = 0 to 127 Write instr[1] : bddat=key[I], bdrdy = 1 Read instr[0] until bdack = 1 Write instr[1] : bdrdy = 0 Read instr[0] until bdack = 0 Next The back door will then be opened if key matches the keys stored aon_wuc.unlock0-3.key | WO | 0
1 | TOTALERASE | Total erase request. To perform chip erase or total erase, assert these bits followed by a mcu_reset_req. Total erase is only possible if the security backdoor has been entered. | WO | 0
0 | CHIPERASE | Chip erase request. To perform chip erase or total erase, assert these bits followed by a mcu_reset_req. Total erase is only possible if the security backdoor has been entered. | WO | 0

### TOP:AON_WUC:SYSCTRL

IR | 2
Description | This is an override value register for SYSCTRL. It's associated override enable register is SYSCTRL_OR Each override has a value register (val) and an override enable regsister (or) The override does not take place unless *_or register is set. If the *_or is set, the *_val register will be fed to corresponding pin. The WUC tap uses the naming convention c2t_wuc* for signals coming from tap. Note that all override registers are blocked if WUC tap is not open. There is no guarantee that an override can not halt the chip, or invalidate flash. Please use with caution!
Type | WO

Bits | Field Name | Description | Type | Reset
27 | WR_EVENT_O_VAL | To be described | WO | 0
26 | DEBUG_EN_CLR_VAL | To be described | WO | 0
25 | DEBUG_EN_SET_VAL | To be described | WO | 0
24 | SCLK_HF_EN_O_VAL | To be described | WO | 0
23 | SYSCTRLPD_O_VAL | Override of syscctrlpd signal going to osctop. 1: Allow OSCTOP to gate clock off. 0: Do not allow OSCTOP to gate clock off. | WO | 0
22 | CLK_ADC_EN_O_VAL | Override of clk_adc_en, adc clock 1: Force clk_adc_en=1 0: Force clk_adc_en=0 | WO | 0
21 | CLK_CHP_EN_O_VAL | Override of clk_chp_en, charge pump clock (used by adc) 1: Force clk_chp_en=1 0: Force clk_chp_en=0 | WO | 0
20 | FORCE_RCOSC_HF_O_VAL | Override of force_rcosc_hf 1: Force force_rcosc_hf to 1, forcing rc osc to start 0: Force force_rcosc_hf to 0, don't force rc_osc to start | WO | 0
19 | CLK_DCDC_EN_O_VAL | Override of clk_dcdc_en 1: Force clk_dcdc_en to 1 0: Force clk_dcdc_en to 0 | WO | 0
18 | RESET_VDDSZ_EN_O_VAL | Override of reset_vddsz to Flash charge pump (3.3V) 1: reset_vddsz forced to 1 0: reset_vddsz forced to 0 | WO | 0
17 | PAD_RING_SLEEP_N_O_VAL | Override of sleep_n signal going to padring 1: pad ring IOs are not latched 0: Pad ring IOs are latched. All Ios are frozen ( except TMS and TCK) | WO | 0
16 | SHUTDOWN_O_VAL | Override of shutdown signal 1: Force system in to shutdown ( will reset ) 0: Prevent system from entering shutdown | WO | 0
15 | BYPASS_OSCDIG_VAL | Override to bypass oscdig 1: oscdig is bypassed 0: oscdig is not bypassed | WO | 0
14 | VDD_BOD_EN_O_VAL | Override for vdd_bod_en 1: Force vdd_bod_en to 1 0: Foce vdd_bod_en to 0 | WO | 0
13 | VREF_SH_O_VAL | Overrride for vref_sh for VDD Regulators (uldo sample hold curcuit) 1: Force vref_sh to 1 0: Force vref_sh to 0 | WO | 0
12 | VREF_TRIM_EN_O_VAL | Overrride for vref_trim_en for VDD Regulators 1: Force vref_trim_en to 1 0: Force vref_trim_en to 0 | WO | 0
11 | DIG_LDO_PRESLEEP_O_VAL | Overrride for dig_ldo_presleep for VDD Regulators 1: Force dig_ldo_presleep to 1 0: Force dig_ldo_presleep to 0 | WO | 0
10 | VDD_LDO_EN_O_VAL | Overrride for vdd_ldo_en for VDD Regulators 1: Force vdd_ldo_en to 1 0: Force vdd_ldo_en to 0 | WO | 0
9 | SLEEP_MODE_EN_O_VAL | Override of sleep_mode for VDDR Regulators 1: Force sleep_mode to 1 0: Force sleep_mode to 0 | WO | 0
8 | DCDC_EN_O_VAL | Override of dcdc_en for VDDR Regulators 1: Turn on DCDC 0: Turn off DCDC | WO | 0
7 | VDDR_REG_EN_O_VAL | Override of vddr_reg_en for VDDR Regulators 1: Turn on VDDR Regulator 0: Turn off VDDR Regulator | WO | 0
6 | GBIAS_EN_O_VAL | Override of gbias_en 1: Turn on global bias reference 0: Turn off global bias reference | WO | 0
5 | BGAP_EN_O_VAL | Override of bgap_en 1: Turn on band gap reference 0: Turn off band gap reference | WO | 0
4 | VDDS_BOD_EN_O_VAL | Override of vdds_bod_en 1: Turn on VDDS Brown out detect curcuit 0: Turn off VDDS Brown out detect circuit | WO | 0
3 | VDD_OK_OR_O_VAL | Override of VDD brown out detect override. 1: vdd_ok=0 will not cause reset 0: vdd_ok=0 will cause reset Note: There is no real brownout detect on VDD. | WO | 0
2 | VDDR_OK_OR_O_VAL | Override of VDDR brown out detect override. 1: vddr_ok=0 will not cause reset 0: vddr_ok=0 will cause reset | WO | 0
1 | VDDS_OK_OR_O_VAL | Override of VDDS brown out detect override. 1: vdds_ok=0 will not cause reset 0: vdds_ok=0 will cause reset | WO | 0
0 | CLK_LOSS_OR_N_O_VAL | Overrride for clock_loss_or_n signal between sysctrl12 and sysctrl33. Will disable clock loss detect brown out on lf_clock is forced hight | WO | 0

### TOP:AON_WUC:SYSCTRL_OBS

IR | 3
Description | Sysctrl observation registers
Type | RO

Bits | Field Name | Description | Type | Reset
27:7 | SYSCTRL_NC | Not connected | RO | 0x00 0000
6 | SYSCTRL_VDDR_OK_I | Observation of the VDDR measurement result that was seen just prior to last recharge. | RO | 0
5:2 | SYSCTRL_FSMSTATE | The state of the sysctrl12 state machine State encoding FSMSTATE[3:0]: 0000: STATE_POWERUP 0001: STATE_ACTIVE_GLDO 0010: STATE_ACTIVE_DCDC 0100: STATE_ACT_PD_SD 1100: STATE_PD_ACT 1110: STATE_POWERDOWN 1111: STATE_SHUTDOWN Note: This signal is sampled without synchronization. Intermediate values can be sampled. It is recommended to oversample to rule out intermediate states. Sysctrl12 can not change states faster than 32 Khz. Limitation: Sysctrl12 can not enter powerdown with JTAG enabled, so many of the states can not be sampled. | RO | 0x0
1 | VDDR_OK | VDDR_OK from VDDR Regulators | RO | 0
0 | VDDS_BOD_OK | Brown out detect signal from VDDS | RO | 0

### TOP:AON_WUC:SYSCTRL_OR

IR | 3
Description | This is the override enable register for SYSCTRL. It's associated override value register is SYSCTRL Each override has a value register (val) and an override enable regsister (or) The override does not take place unless *_or register is set. If the *_or is set, the *_val register will be fed to corresponding pin. The WUC tap uses the naming convention c2t_wuc* for signals coming from tap. Note that all override registers are blocked if WUC tap is not open. There is no guarantee that an override can not halt the chip, or invalidate flash. Please use with caution!
Type | WO

Bits | Field Name | Description | Type | Reset
27 | WR_EVENT_O_OR | To be documented | WO | 0
26 | DEBUG_EN_CLR_OR | To be documented | WO | 0
25 | DEBUG_EN_SET_OR | To be documented | WO | 0
24 | SCLK_HF_EN_O_OR | To be documented | WO | 0
23 | SYSCTRLPD_O_OR | Override enable of syscctrlpd signal going to osctop. 0: Override disabled 1: Override enable | WO | 0
22 | CLK_ADC_EN_O_OR | Override enable of clk_adc_en, adc clock 0: Override disabled 1: Override enabled | WO | 0
21 | CLK_CHP_EN_O_OR | Override enable of clk_chp_en, charge pump clock (used by adc) 0: Override disabled 1: Override enabled | WO | 0
20 | FORCE_RCOSC_HF_O_OR | Override enable of force_rcosc_hf 0: Override disabled 1: Override enabled | WO | 0
19 | CLK_DCDC_EN_O_OR | Override enable of clk_dcdc_en 0: Override disabled 1: Override enabled | WO | 0
18 | RESET_VDDSZ_EN_O_OR | Override enable of reset_vddsz to Flash charge pump (3.3V) 0: Override disabled 1: Override enabled | WO | 0
17 | PAD_RING_SLEEP_N_O_OR | Override enable of sleep_n signal going to padring 0: Override disabled 1: Override enabled | WO | 0
16 | SHUTDOWN_O_OR | Override enable of shutdown signal 0: Override disabled 1: Override enabled | WO | 0
15 | BYPASS_OSCDIG_OR | Override enable to bypass oscdig 0: Override disabled 1: Override enabled | WO | 0
14 | VDD_BOD_EN_O_OR | Override enable for vdd_bod_en 0: Override disabled 1: Override enabled | WO | 0
13 | VREF_SH_O_OR | Override enable for vref_sh for VDD Regulators (uldo sample hold curcuit) 0: Override disabled 1: Override enabled | WO | 0
12 | VREF_TRIM_EN_O_OR | Override enable for vref_trim_en for VDD Regulators 0: Override disabled 1: Override enabled | WO | 0
11 | DIG_LDO_PRESLEEP_O_OR | Override enable for dig_ldo_presleep for VDD Regulators 0: Override disabled 1: Override enabled | WO | 0
10 | VDD_LDO_EN_O_OR | Override enable for vdd_ldo_en for VDD Regulators 0: Override disabled 1: Override enabled | WO | 0
9 | SLEEP_MODE_EN_O_OR | Override enable of sleep_mode for VDDR Regulators 0: Override disabled 1: Override enabled | WO | 0
8 | DCDC_EN_O_OR | Override enable of dcdc_en for VDDR Regulators 0: Override disabled 1: Override enabled | WO | 0
7 | VDDR_REG_EN_O_OR | Override enable of vddr_reg_en for VDDR Regulators 0: Override disabled 1: Override enabled | WO | 0
6 | GBIAS_EN_O_OR | Override enable of gbias_en 0: Override disabled 1: Override enabled | WO | 0
5 | BGAP_EN_O_OR | Override enable of bgap_en 0: Override disabled 1: Override enabled | WO | 0
4 | VDDS_BOD_EN_O_OR | Override enable of vdds_bod_en 0: Override disabled 1: Override enabled | WO | 0
3 | VDD_OK_OR_O_OR | Override enable of VDD brown out detect override. 0: Override disabled 1: Override enabled | WO | 0
2 | VDDR_OK_OR_O_OR | Override enable of VDDR brown out detect override. 0: Override disabled 1: Override enabled | WO | 0
1 | VDDS_OK_OR_O_OR | Override enable of VDDS brown out detect override. 0: Override disabled 1: Override enabled | WO | 0
0 | CLK_LOSS_OR_N_O_OR | Override enable for clock_loss_or_n signal between sysctrl12 and sysctrl33. 0: Override disabled 1: Override enabled | WO | 0

### TOP:AON_WUC:MISC

IR | 4
Description | This is an override value register for miscallenious signals. It's associated override enable register is MISC_OR Each override has a value register (val) and an override enable regsister (or) The override does not take place unless *_or register is set. If the *_or is set, the *_val register will be fed to corresponding pin. The WUC tap uses the naming convention c2t_wuc* for signals coming from tap. Note that all override registers are blocked if WUC tap is not open. There is no guarantee that an override can not halt the chip, or invalidate flash. Please use with caution!
Type | WO

Bits | Field Name | Description | Type | Reset
8:7 | MISC_NC | Reserved for future use | WO | 0x0
6 | MCU_CLK_HF_FREQ_O_VAL | Override of mcu_clk_hf_freq signal. High frequency indication towards prcm 1: The hf clock is now a 48 MHz signal, ie prcm must divide accordingly. 0: HF clock is not a 48 MHz,- ie prcm does not need to divide before usage. | WO | 0
5 | SCLK_LF_STOP_VAL | 1: Stop the LF clock to all aon modules. The signal controls EN of a clock gater at root of AON (LF CLOCK keeps running in OSCTOP). Note: This signal does not have a corresponding *_or register. | WO | 0
4 | JTAG_DONOTRESET_WUCTAP_VAL | 1: Do not reset wuc tap when JTAG power domain is powered down. Note: This signal does not have a corresponding *_or register. | WO | 0
3 | REPAIR_DONE_VAL | Override of repair_done signal. 1: Repair is done 0: Repair is not done, this will provoke efuse to scan to SRAM repair chain | WO | 0
2 | GOTO_ACT_MODE_VAL | 0 or 1: Force goto_act signal high | WO | 0
1 | GOTO_PD_MODE_VAL | 0 or 1: Force goto_pd signal high | WO | 0
0 | JTAG_DONOTPOWERUP_VAL | 1: Prevent JTAG domain from being powered up from ICEMELTER Note: This signal does not have a corresponding *_or register. | WO | 0

### TOP:AON_WUC:MISC_OBS

IR | 5
Description | Miscellanious observation registers
Type | RO

Bits | Field Name | Description | Type | Reset
8:7 | NC7 | Not connected | RO | 0x0
6 | JTAG_PGOODIN | Feed back from PGOODIN chain in JTAG domain. | RO | 0
5 | JTAG_PONIN | Feed back from PONIN chain in JTAG domain. | RO | 0
4:3 | JTAG_STATE | Observation of JTAG state State encoding JTAG_STATE[1:0]: 01: JTAG_STATE_POWERON: 11: JTAG_STATE_POWERON_1 00: JTAG_STATE_OFF Limitation: We can only read from WUC when JTAG is on, i.e. this can only return 01 | RO | 0x0
2:0 | PM_STATE | The state of the WUC PM state machine. State encoding PM_STATE[2:0]: 000: PM_STATE_ACTIVE 001: PM_STATE_GOING_PD 010: PM_STATE_GOING_ACT 011: PM_STATE_POWERDOWN 100: PM_STATE_SHUTDOWN 111: PM_STATE_RECHARGE Limitation: WUC can not leave ACTIVE state with JTAG domain on, hence this will always return as 0 | RO | 0x0

### TOP:AON_WUC:MISC_OR

IR | 5
Description | This is the override enable register for miscellaneous signals It's associated override value register is MISC Each override has a value register (val) and an override enable regsister (or) The override does not take place unless *_or register is set. If the *_or is set, the *_val register will be fed to corresponding pin. The WUC tap uses the naming convention c2t_wuc* for signals coming from tap. Note that all override registers are blocked if WUC tap is not open. There is no guarantee that an override can not halt the chip, or invalidate flash. Please use with caution!
Type | WO

Bits | Field Name | Description | Type | Reset
8:7 | MISC_NC7 | Reserved for future use | WO | 0x0
6 | MCU_CLK_HF_FREQ_O_OR | Override of mcu_clk_hf_freq signal. High frequency indication towards prcm 1: The hf clock is now a 48 MHz signal, ie prcm must divide accordingly. 0: HF clock is not a 48 MHz,- ie prcm does not need to divide before usage. | WO | 0
5 | MISC_NC5 | 1: Stop the LF clock to all aon modules. The signal controls EN of a clock gater at root of AON (LF CLOCK keeps running in OSCTOP). Note: This signal does not have a corresponding *_or register. | WO | 0
4 | MISC_NC4 | 1: Do not reset wuc tap when JTAG power domain is powered down. Note: This signal does not have a corresponding *_or register. | WO | 0
3 | REPAIR_DONE_OR | Override of repair_done signal. 1: Repair is done 0: Repair is not done, this will provoke efuse to scan to SRAM repair chain | WO | 0
2 | GOTO_ACT_MODE_OR | 0 or 1: Force goto_act signal high | WO | 0
1 | GOTO_PD_MODE_OR | 0 or 1: Force goto_pd signal high | WO | 0
0 | MISC_NC0 | 1: Prevent JTAG domain from being powered up from ICEMELTER Note: This signal does not have a corresponding *_or register. | WO | 0

### TOP:AON_WUC:MCUVD

IR | 6
Description | This is an override value register for MCU VD signals It's associated override enable register is MCUVD_OR Each override has a value register (val) and an override enable regsister (or) The override does not take place unless *_or register is set. If the *_or is set, the *_val register will be fed to corresponding pin. The WUC tap uses the naming convention c2t_wuc* for signals coming from tap. Note that all override registers are blocked if WUC tap is not open. There is no guarantee that an override can not halt the chip, or invalidate flash. Please use with caution!
Type | WO

Bits | Field Name | Description | Type | Reset
18 | MCU_LATCH_EN_VAL | Override mcu_latch_en signal 1: Close register latches in AON domain for 0: Open register latches in AON domain | WO | 0
17 | MCU_RESET_N_O_VAL | Override of mcu_reset_n signal 1: Foce mcu_reset_n to 1 ( preventing reset ) 0: Force mcu_reset_n to 0 ( forcing reset of all in mcu domain, including registers for aon) | WO | 0
16 | MCU_ISO_EN_VAL | Override of isolation signal for muc power domain 0: Force mcu_iso_en=0 1: Force mcu_iso_en=1 | WO | 0
15 | MCU_VDD_PON_VAL | Override of weak switches for mcu power domain 0: Foce mcu_vdd_pon=0 1: Force mcu_vdd_pon=1 | WO | 0
14 | MCU_VDD_PGOOD_VAL | Override of strong switches for mcu power domain 0: Foce mcu_vdd_pgood=0 1: Force mcu_vdd_pgood=1 | WO | 0
13 | MCU_SRAM_PGOOD_VAL | Override of mcu_sram_pgood signal 0: Force mcu_sram_pgood signal to 0 1: Force mcu_sram_pgood signal to 1 | WO | 0
12 | MCU_SRAM_PON_VAL | Override of mcu_sram_pon signal 0: Force mcu_sram_pon signal to 0 1: Foce mcu_sram_pon signal to 1 | WO | 0
11 | MCU_SRAM_ERASE_VAL | Override of mcu_sram_erase signal 1: Clear content of mcu sram 0: Do not clear content of mcu sram | WO | 0
10:7 | MCU_SRAM_AGOOD_VAL | Override of mcu_sram_good[3:0] bus. (Strong switches for sram array) | WO | 0x0
6:3 | MCU_SRAM_AON_VAL | Override of mcu_sram_aon[3:0] bus. (Weak switches for sram array) | WO | 0x0
2 | MCU_SRAM_ISO_VAL | Override of mcu_sram_iso 1: force mcu_sram_iso=1 0: force mcu_sram_iso=0 | WO | 0
1 | MCU_SRAM_RETGOOD_VAL | Override of MCU SRAM RETGOOD signal. (strong switches controlling retention power in MCU SRAM) 1: mcu_sram_retgood forced to 1 0: mcu_sram_retgood forced to 0 | WO | 0
0 | MCU_SRAM_RETON_VAL | Override of MCU SRAM RETON signal. (weak switches controlling retention power in MCU SRAM) 1: mcu_sram_reton forced to 1 0: mcu_sram_reton forced to 0 | WO | 0

### TOP:AON_WUC:MCUVD_OBS

IR | 7
Description | MCUVD observation registers
Type | RO

Bits | Field Name | Description | Type | Reset
18:4 | NC | Not connected | RO | 0x0000
3:0 | MCU_VDDCTRL_STATE | State of MCU Voltage domain controller 0000: STATE_RESET 0001: STATE_RESET_1 0100: STATE_POWEROFF 0110: STATE_POWEROFF_2 0111: STATE_POWEROFF_3 0011: STATE_POWEROFF_4 1000: STATE_POWERON 1001: STATE_POWERON_1 1011: STATE_POWERON_3 1100: STATE_POWERON_4 1101: STATE_RESETREQ0 1110: STATE_RESETREQ1 1111: STATE_RESETREQ2 Note: There is no synchronization of the STATE variable that can only change @32Khz rate. It is recommended to oversample this observation to rule sampling of out false intermediate values. Note2: The state encoding is generic for aux and mcu. Not all states can be reached from MCU nor AUX | RO | 0x0

### TOP:AON_WUC:MCUVD_OR

IR | 7
Description | This is the override enable register for MCU VD It's associated override value register is MCUVD Each override has a value register (val) and an override enable regsister (or) The override does not take place unless *_or register is set. If the *_or is set, the *_val register will be fed to corresponding pin. The WUC tap uses the naming convention c2t_wuc* for signals coming from tap. Note that all override registers are blocked if WUC tap is not open. There is no guarantee that an override can not halt the chip, or invalidate flash. Please use with caution!
Type | WO

Bits | Field Name | Description | Type | Reset
18 | MCU_LATCH_EN_OR | Override enable for mcu_latch_en | WO | 0
17 | MCU_RESET_N_O_OR | Override enable for mcu_reset_n_o | WO | 0
16 | MCU_ISO_EN_OR | Override enable for mcu_iso_en | WO | 0
15 | MCU_VDD_PON_OR | Override enable for mcu_vdd_pon | WO | 0
14 | MCU_VDD_PGOOD_OR | Override enable for mcu_vdd_pgood | WO | 0
13 | MCU_SRAM_PGOOD_OR | Override enable for mcu_sram_pgood | WO | 0
12 | MCU_SRAM_PON_OR | Override enable for mcu_sram_pon | WO | 0
11 | MCU_SRAM_ERASE_OR | Override enable for mcu_sram_erase | WO | 0
10:7 | MCU_SRAM_AGOOD_OR | Override enable for mcu_sram_agood[3:0] | WO | 0x0
6:3 | MCU_SRAM_AON_OR | Override enable for mcu_sram_aon[3:0] | WO | 0x0
2 | MCU_SRAM_ISO_OR | Override enable for mcu_sram_iso | WO | 0
1 | MCU_SRAM_RETGOOD_OR | Override enable for mcu_sram_retgood | WO | 0
0 | MCU_SRAM_RETON_OR | Override enable for mcu_sram_reton | WO | 0

### TOP:AON_WUC:CLK

IR | 8
Description | This is an override value register for CLK signals It's associated override enable register is CLK_OR Each override has a value register (val) and an override enable regsister (or) The override does not take place unless *_or register is set. If the *_or is set, the *_val register will be fed to corresponding pin. The WUC tap uses the naming convention c2t_wuc* for signals coming from tap. Note that all override registers are blocked if WUC tap is not open. There is no guarantee that an override can not halt the chip, or invalidate flash. Please use with caution!
Type | WO

Bits | Field Name | Description | Type | Reset
8:6 | AUX_CLK_SRC_VAL | Clock source for AUX domain 000: No clock 001: LF Clock 010: MF Clock 100: HF Clock It is recommended not to use other combinations than the above The clock change is not immediate as the signal is synchronized to LF clock. The current active clock can be observed by reading from same positions in clk_or register | WO | 0x0
5:3 | MCU_CLK_SRC_VAL | Clock source for mcu domain 000: No clock 001: LF Clock 010: MF Clock 100: HF Clock It is recommended not to use other combinations than the above. The clock change is not immediate as the signal is synchronized to LF clock. The current active clock can be observed by reading from same positions in clk_or register | WO | 0x0
2 | HF_CLK_O_VAL | Override for single step of hf clock. 1: HF_CLK forced to 1 0: HF_CLK forced to 0 Note: A clock glitch can occur when turning on override. It is recommended that the hf clock is not used as source during this handover | WO | 0
1 | MF_CLK_O_VAL | Override for single step of mf clock. 1: MF_CLK forced to 1 0: MF_CLK forced to 0 Note: A clock glitch can occur when turning on override. It is recommended that the mf clock is not used as source during this handover | WO | 0
0 | LF_CLK_O_VAL | Override for single step of lf clock. 1: LF_CLK forced to 1 0: LF_CLK forced to 0 Note: As LF clock is used as clock source for AON, it is recommended to use sclk_lf clock stop register first to avoid a possible clock glitch when enabling the override. | WO | 0

### TOP:AON_WUC:CLK_OBS

IR | 9
Description | CLK observation registers
Type | RO

Bits | Field Name | Description | Type | Reset
8:6 | AUX_CLK_STATUS | Output of the state of the clock mux for AUX clock. 000: No clock is active 001: LF Clock is active 010: MF Clock is active 100: HF Clock is active | RO | 0x0
5:3 | MCU_CLK_STATUS | Output of the state of the clock mux for MCU clock. 000: No clock is active 001: LF Clock is active 010: MF Clock is active 100: HF Clock is active | RO | 0x0
2:0 | CLK_NC | Not connected | RO | 0x0

### TOP:AON_WUC:CLK_OR

IR | 9
Description | This is the override enable register for CLK It's associated override value register is CLK+I124 Each override has a value register (val) and an override enable regsister (or) The override does not take place unless *_or register is set. If the *_or is set, the *_val register will be fed to corresponding pin. The WUC tap uses the naming convention c2t_wuc* for signals coming from tap. Note that all override registers are blocked if WUC tap is not open. There is no guarantee that an override can not halt the chip, or invalidate flash. Please use with caution!
Type | WO

Bits | Field Name | Description | Type | Reset
8:6 | AUX_CLK_SRC_OR | Override enable for aux_clk_src | WO | 0x0
5:3 | MCU_CLK_SRC_OR | Override enable for mcu_clk_src | WO | 0x0
2 | HF_CLK_O_OR | Override enable for hf_clk_o | WO | 0
1 | MF_CLK_O_OR | Override enable for mf_clk_o | WO | 0
0 | LF_CLK_O_OR | Override enable for lf_clk_o | WO | 0

### TOP:AON_WUC:AUXVD

IR | 10
Description | This is an override value register for AUX VD signals It's associated override enable register is AUXVD_OR Each override has a value register (val) and an override enable regsister (or) The override does not take place unless *_or register is set. If the *_or is set, the *_val register will be fed to corresponding pin. The WUC tap uses the naming convention c2t_wuc* for signals coming from tap. Note that all override registers are blocked if WUC tap is not open. There is no guarantee that an override can not halt the chip, or invalidate flash. Please use with caution!
Type | WO

Bits | Field Name | Description | Type | Reset
11 | AUX_RESET_N_O_VAL | Override of aux_reset_n signal 1: Foce aux_reset_n to 1 ( preventing reset ) 0: Force aux_reset_n to 0 ( forcing reset of all in aux domain) |  | 0
10 | MCU_ISO_EN_VAL | Override of isolation signal for muc power domain 1: Force mcu_iso_en=1 0: Force mcu_iso_en=0 |  | 0
9 | MCU_VDD_PON_VAL | Override of weak switches for mcu power domain 1: Force mcu_vdd_pon=1 0: Foce mcu_vdd_pon=0 |  | 0
8 | MCU_VDD_PGOOD_VAL | Override of strong switches for mcu power domain 1: Force mcu_vdd_pgood=1 0: Foce mcu_vdd_pgood=0 |  | 0
7 | AUX_SRAM_PGOOD_VAL | Override of aux_sram_pgood signal 0: Force mcu_sram_pgood signal to 0 1: Force mcu_sram_pgood signal to 1 |  | 0
6 | AUX_SRAM_PON_VAL | Override of aux_sram_pon signal 0: Force aux_sram_pon signal to 0 1: Foce aux_sram_pon signal to 1 |  | 0
5 | AUX_SRAM_ERASE_VAL | Override of aux_sram_erase signal 1: Clear content of aux sram 0: Do not clear content of aux sram |  | 0
4 | AUX_SRAM_AGOOD_VAL | Override of aux_sram_good. (Strong switch for sram array) |  | 0
3 | AUX_SRAM_AON_VAL | Override of aux_sram_aon (Weak switch for sram array) |  | 0
2 | AUX_SRAM_ISO_VAL | Override of aux_sram_iso 1: force aux_sram_iso=1 0: force aux_sram_iso=0 |  | 0
1 | AUX_SRAM_RETGOOD_VAL | Override of AUX SRAM RETGOOD signal. (strong switches controlling retention power in AUX SRAM) 1: aux_sram_retgood forced to 1 0: aux_sram_retgood forced to 0 |  | 0
0 | AUX_SRAM_RETON_VAL | Override of AUX SRAM RETON signal. (weak switches controlling retention power in AUX SRAM) 1: aux_sram_reton forced to 1 0: aux_sram_reton forced to 0 |  | 0

### TOP:AON_WUC:AUXVD_OBS

IR | 11
Description | AUX VD observation signals
Type | RO

Bits | Field Name | Description | Type | Reset
11:10 | AUX_VDCTRL10 | Not connected |  | 0x0
9 | AUX_VDD_PGOODOUT | Observation of aux vdd pgoodout |  | 0
8 | AUX_VDD_PONOUT | Observation of aux_vdd_ponout |  | 0
7:4 | AUX_VDCTRL4 | Not connected |  | 0x0
3:0 | AUX_VDDCTRL_STATE | State of AUX Voltage domain controller 0000: STATE_RESET 0001: STATE_RESET_1 0100: STATE_POWEROFF 0110: STATE_POWEROFF_2 0111: STATE_POWEROFF_3 0011: STATE_POWEROFF_4 1000: STATE_POWERON 1001: STATE_POWERON_1 1011: STATE_POWERON_3 1100: STATE_POWERON_4 1101: STATE_RESETREQ0 1110: STATE_RESETREQ1 1111: STATE_RESETREQ2 Note: There is no synchronization of the STATE variable that can only change @32Khz rate. It is recommended to oversample this observation to rule sampling of out false intermediate values. Note2: The state encoding is generic for aux and mcu. Not all states can be reached from MCU nor AUX |  | 0x0

### TOP:AON_WUC:AUXVD_OR

IR | 11
Description | This is the override enable register for AUX VD It's associated override value register is AUXVD Each override has a value register (val) and an override enable regsister (or) The override does not take place unless *_or register is set. If the *_or is set, the *_val register will be fed to corresponding pin. The WUC tap uses the naming convention c2t_wuc* for signals coming from tap. Note that all override registers are blocked if WUC tap is not open. There is no guarantee that an override can not halt the chip, or invalidate flash. Please use with caution!
Type | WO

Bits | Field Name | Description | Type | Reset
11 | AUX_RESET_N_O_OR | Override enable for aux_reset_n_o |  | 0
10 | MCU_ISO_EN_OR | Override enable for mcu_iso_en |  | 0
9 | MCU_VDD_PON_OR | Override enable for mcu_vdd_pon |  | 0
8 | MCU_VDD_PGOOD_OR | Override enable for mcu_vdd_pgood |  | 0
7 | AUX_SRAM_PGOOD_OR | Override enable for aux_sram_pgood |  | 0
6 | AUX_SRAM_PON_OR | Override enable for aux_sram_pon |  | 0
5 | AUX_SRAM_ERASE_OR | Override enable for aux_sram_erase |  | 0
4 | AUX_SRAM_AGOOD_OR | Override enable for aux_sram_agood |  | 0
3 | AUX_SRAM_AON_OR | Override enable for aux_sram_aon |  | 0
2 | AUX_SRAM_ISO_OR | Override enable for aux_sram_iso |  | 0
1 | AUX_SRAM_RETGOOD_OR | Override enable for aux_sram_retgood |  | 0
0 | AUX_SRAM_RETON_OR | Override enable for aux_sram_reton |  | 0

### TOP:AON_WUC:TMS_CTRL

IR | 12
Description |
Type | WO

Bits | Field Name | Description | Type | Reset
6 | MCU_FORCEACTIVE_O | 1: MCU Domain is forced on. | WO | 0
5 | TMS_EC | Set EC value for TMS pad (Default 0) | WO | 0
4 | TMS_SC | Set SC value for TMS pad (Default 0) | WO | 0
3 | TMS_HC | Set HC value for TMS pad (Default 1) | WO | 0
2:0 | TMS_STRIN | Set STRIN value for the TMS pad (Default 0 which is adaptive drivestrength) Comment: What is the strength selected by other values. Are all other combinations legal? | WO | 0x0

### TOP:AON_WUC:PSCON_CTRL

IR | 13
Description |
Type | WO

Bits | Field Name | Description | Type | Reset
4 | WUC_PSCON_SPARE | Reserved for DFT purposes. Needs more documentation.... | WO | 0
3 | WUC_PSCON_AONONLY_SEL | Reserved for DFT purposes. Needs more documentation.... | WO | 0
2 | WUC_PSCON_TSTCLK_BYPASS | Reserved for DFT purposes. Needs more documentation.... | WO | 0
1 | WUC_PSCON_BLOCKOUT | Reserved for DFT purposes. Needs more documentation.... | WO | 0
0 | WUC_PSCON_MODE | Reserved for DFT purposes. Needs more documentation.... | WO | 0