## I2S0

Instance: I2S0
Component: I2S
Base address: 0x40021000

I2S Audio DMA module supporting formats I2S, LJF, RJF and DSP

### TOP:I2S0 Register Summary

Register Name | Type | Register Width (Bits) | Register Reset | Address Offset | Physical Address
AIFWCLKSRC | RW | 32 | 0x0000 0000 | 0x0000 0000 | 0x4002 1000
AIFDMACFG | RW | 32 | 0x0000 0000 | 0x0000 0004 | 0x4002 1004
AIFDIRCFG | RW | 32 | 0x0000 0000 | 0x0000 0008 | 0x4002 1008
AIFFMTCFG | RW | 32 | 0x0000 0170 | 0x0000 000C | 0x4002 100C
AIFWMASK0 | RW | 32 | 0x0000 0003 | 0x0000 0010 | 0x4002 1010
AIFWMASK1 | RW | 32 | 0x0000 0003 | 0x0000 0014 | 0x4002 1014
AIFWMASK2 | RW | 32 | 0x0000 0003 | 0x0000 0018 | 0x4002 1018
AIFPWMVALUE | RW | 32 | 0x0000 0000 | 0x0000 001C | 0x4002 101C
AIFINPTRNEXT | RW | 32 | 0x0000 0000 | 0x0000 0020 | 0x4002 1020
AIFINPTR | RW | 32 | 0x0000 0000 | 0x0000 0024 | 0x4002 1024
AIFOUTPTRNEXT | RW | 32 | 0x0000 0000 | 0x0000 0028 | 0x4002 1028
AIFOUTPTR | RW | 32 | 0x0000 0000 | 0x0000 002C | 0x4002 102C
STMPCTL | RW | 32 | 0x0000 0000 | 0x0000 0034 | 0x4002 1034
STMPXCNTCAPT0 | RO | 32 | 0x0000 0000 | 0x0000 0038 | 0x4002 1038
STMPXPER | RO | 32 | 0x0000 0000 | 0x0000 003C | 0x4002 103C
STMPWCNTCAPT0 | RO | 32 | 0x0000 0000 | 0x0000 0040 | 0x4002 1040
STMPWPER | RW | 32 | 0x0000 0000 | 0x0000 0044 | 0x4002 1044
STMPINTRIG | RW | 32 | 0x0000 0000 | 0x0000 0048 | 0x4002 1048
STMPOUTTRIG | RW | 32 | 0x0000 0000 | 0x0000 004C | 0x4002 104C
STMPWSET | RW | 32 | 0x0000 0000 | 0x0000 0050 | 0x4002 1050
STMPWADD | RW | 32 | 0x0000 0000 | 0x0000 0054 | 0x4002 1054
STMPXPERMIN | RW | 32 | 0x0000 FFFF | 0x0000 0058 | 0x4002 1058
STMPWCNT | RO | 32 | 0x0000 0000 | 0x0000 005C | 0x4002 105C
STMPXCNT | RO | 32 | 0x0000 0000 | 0x0000 0060 | 0x4002 1060
STMPXCNTCAPT1 | RO | 32 | 0x0000 0000 | 0x0000 0064 | 0x4002 1064
STMPWCNTCAPT1 | RO | 32 | 0x0000 0000 | 0x0000 0068 | 0x4002 1068
IRQMASK | RW | 32 | 0x0000 0000 | 0x0000 0070 | 0x4002 1070
IRQFLAGS | RO | 32 | 0x0000 0000 | 0x0000 0074 | 0x4002 1074
IRQSET | WO | 32 | 0x0000 0000 | 0x0000 0078 | 0x4002 1078
IRQCLR | WO | 32 | 0x0000 0000 | 0x0000 007C | 0x4002 107C

### TOP:I2S0 Register Descriptions

### TOP:I2S:AIFWCLKSRC

Address offset | 0x0000 0000
Physical address | 0x4002 1000 | Instance | I2S0
Description | WCLK Source Selection
Type | RW

Bits | Field Name | Description | Type | Reset
31:3 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0000 0000
2 | WCLK_INV | Inverts WCLK source (pad or internal) when set. 0: Not inverted 1: Inverted | RW | 0
1:0 | WCLK_SRC | Selects WCLK source for AIF (should be the same as the BCLK source). The BCLK source is defined in the PRCM:I2SBCLKSEL.SRC
Value | ENUM name | Description
0x0 | NONE | None ('0')
0x1 | EXT | External WCLK generator, from pad
0x2 | INT | Internal WCLK generator, from module PRCM/ClkCtrl
0x3 | RESERVED | Not supported. Will give same WCLK as 'NONE' ('00')
| RW | 0x0

### TOP:I2S:AIFDMACFG

Address offset | 0x0000 0004
Physical address | 0x4002 1004 | Instance | I2S0
Description | DMA Buffer Size Configuration
Type | RW

Bits | Field Name | Description | Type | Reset
31:8 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x00 0000
7:0 | END_FRAME_IDX | Defines the length of the Writing a non-zero value to this registerfield enables and initializes AIF. Note that before doing so, all other configuration must have been done, and AIFINPTR/AIFOUTPTR must have been loaded. | RW | 0x00

### TOP:I2S:AIFDIRCFG

Address offset | 0x0000 0008
Physical address | 0x4002 1008 | Instance | I2S0
Description | Pin Direction
Type | RW

Bits | Field Name | Description | Type | Reset
31:10 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x00 0000
9:8 | AD2 | Configures the AD2 audio data pin usage 0x3: Reserved
Value | ENUM name | Description
0x0 | DIS | Not in use (disabled)
0x1 | IN | Input mode
0x2 | OUT | Output mode
| RW | 0x0
7:6 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0
5:4 | AD1 | Configures the AD1 audio data pin usage: 0x3: Reserved
Value | ENUM name | Description
0x0 | DIS | Not in use (disabled)
0x1 | IN | Input mode
0x2 | OUT | Output mode
| RW | 0x0
3:2 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0
1:0 | AD0 | Configures the AD0 audio data pin usage: 0x3: Reserved
Value | ENUM name | Description
0x0 | DIS | Not in use (disabled)
0x1 | IN | Input mode
0x2 | OUT | Output mode
| RW | 0x0

### TOP:I2S:AIFFMTCFG

Address offset | 0x0000 000C
Physical address | 0x4002 100C | Instance | I2S0
Description | Serial Interface Format Configuration
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0000
15:8 | DATA_DELAY | The number of BCLK periods between a WCLK edge and MSB of the first word in a phase: 0x00: LJF format 0x01: I2S and DSP format 0x02: RJF format ... 0xFF: RJF format Note: When 0, MSB of the next word will be output in the idle period between LSB of the previous word and the start of the next word. Otherwise logical 0 will be output until the data delay has expired. | RW | 0x01
7 | MEM_LEN_24 | The size of each word stored to or loaded from memory:
Value | ENUM name | Description
0 | 16BIT | 16-bit (one 16 bit access per sample)
1 | 24BIT | 24-bit (one 8 bit and one 16 bit locked access per sample)
| RW | 0
6 | SMPL_EDGE | On the serial audio interface, data (and wclk) is sampled and clocked out on opposite edges of BCLK.
Value | ENUM name | Description
0 | NEG | Data is sampled on the negative edge and clocked out on the positive edge.
1 | POS | Data is sampled on the positive edge and clocked out on the negative edge.
| RW | 1
5 | DUAL_PHASE | Selects dual- or single-phase format. 0: Single-phase 1: Dual-phase | RW | 1
4:0 | WORD_LEN | Number of bits per word (8-24): In single-phase format, this is the exact number of bits per word. In dual-phase format, this is the maximum number of bits per word. Values below 8 and above 24 give undefined behavior. Data written to memory is always aligned to 16 or 24 bits as defined by MEM_LEN_24. Bit widths that differ from this alignment will either be truncated or zero padded. | RW | 0x10

### TOP:I2S:AIFWMASK0

Address offset | 0x0000 0010
Physical address | 0x4002 1010 | Instance | I2S0
Description | Word Selection Bit Mask for Pin 0
Type | RW

Bits | Field Name | Description | Type | Reset
31:8 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text) | RW | 0x00 0000
7:0 | MASK | Bit-mask indicating valid channels in a frame on AD0. In single-phase mode, each bit represents one channel, starting with LSB for the first word in the frame. A frame can contain up to 8 channels. Channels that are not included in the mask will not be sampled and stored in memory, and clocked out as '0'. In dual-phase mode, only the two LSBs are considered. For a stereo configuration, set both bits. For a mono configuration, set bit 0 only. In mono mode, only channel 0 will be sampled and stored to memory, and channel 0 will be repeated when clocked out. In mono mode, only channel 0 will be sampled and stored to memory, and channel 0 will be repeated in the second phase when clocked out. If all bits are zero, no input words will be stored to memory, and the output data lines will be constant '0'. This can be utilized when PWM debug output is desired without any actively used output pins. | RW | 0x03

### TOP:I2S:AIFWMASK1

Address offset | 0x0000 0014
Physical address | 0x4002 1014 | Instance | I2S0
Description | Word Selection Bit Mask for Pin 1
Type | RW

Bits | Field Name | Description | Type | Reset
31:8 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x00 0000
7:0 | MASK | Bit-mask indicating valid channels in a frame on AD1. In single-phase mode, each bit represents one channel, starting with LSB for the first word in the frame. A frame can contain up to 8 channels. Channels that are not included in the mask will not be sampled and stored in memory, and clocked out as '0'. In dual-phase mode, only the two LSBs are considered. For a stereo configuration, set both bits. For a mono configuration, set bit 0 only. In mono mode, only channel 0 will be sampled and stored to memory, and channel 0 will be repeated when clocked out. In mono mode, only channel 0 will be sampled and stored to memory, and channel 0 will be repeated in the second phase when clocked out. If all bits are zero, no input words will be stored to memory, and the output data lines will be constant '0'. This can be utilized when PWM debug output is desired without any actively used output pins. | RW | 0x03

### TOP:I2S:AIFWMASK2

Address offset | 0x0000 0018
Physical address | 0x4002 1018 | Instance | I2S0
Description | Word Selection Bit Mask for Pin 2
Type | RW

Bits | Field Name | Description | Type | Reset
31:8 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x00 0000
7:0 | MASK | Bit-mask indicating valid channels in a frame on AD2 In single-phase mode, each bit represents one channel, starting with LSB for the first word in the frame. A frame can contain up to 8 channels. Channels that are not included in the mask will not be sampled and stored in memory, and clocked out as '0'. In dual-phase mode, only the two LSBs are considered. For a stereo configuration, set both bits. For a mono configuration, set bit 0 only. In mono mode, only channel 0 will be sampled and stored to memory, and channel 0 will be repeated when clocked out. In mono mode, only channel 0 will be sampled and stored to memory, and channel 0 will be repeated in the second phase when clocked out. If all bits are zero, no input words will be stored to memory, and the output data lines will be constant '0'. This can be utilized when PWM debug output is desired without any actively used output pins. | RW | 0x03

### TOP:I2S:AIFPWMVALUE

Address offset | 0x0000 001C
Physical address | 0x4002 101C | Instance | I2S0
Description | Audio Interface PWM Debug Value
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0000
15:0 | PULSE_WIDTH | The value written to this register determines the width of the active high PWM pulse (pwm_debug), which starts together with MSB of the first output word in a DMA buffer: 0x0000: Constant low 0x0001: Width of the pulse (number of BCLK cycles, here 1). ... 0xFFFE: Width of the pulse (number of BCLK cycles, here 65534). 0xFFFF: Constant high | RW | 0x0000

### TOP:I2S:AIFINPTRNEXT

Address offset | 0x0000 0020
Physical address | 0x4002 1020 | Instance | I2S0
Description | DMA Input Buffer Next Pointer
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | PTR | Pointer to the first byte in the next DMA input buffer. The read value equals the last written value until the currently used DMA input buffer is completed, and then becomes null when the last written value is transferred to the DMA controller to start on the next buffer. This event is signalized by aif_dma_in_irq. At startup, the value should be written once before and once after configuring the DMA buffer size in AIFDMACFG. The next pointer must be written to this register while the DMA function uses the previously written pointer. If not written in time, IRQFLAGS.PTR_ERR will be raised and all input pins will be disabled. Note the following limitations: - Address space wrapping is not supported (i.e. address(last sample) must be higher than address(first sample). - A DMA block cannot be aligned with the end of the address space (i.e. a block cannot contain the address 0xFFFF) | RW | 0x0000 0000

### TOP:I2S:AIFINPTR

Address offset | 0x0000 0024
Physical address | 0x4002 1024 | Instance | I2S0
Description | DMA Input Buffer Current Pointer
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | PTR | Value of the DMA input buffer pointer currently used by the DMA controller. Incremented by 1 (byte) or 2 (word) for each AHB access. | RW | 0x0000 0000

### TOP:I2S:AIFOUTPTRNEXT

Address offset | 0x0000 0028
Physical address | 0x4002 1028 | Instance | I2S0
Description | DMA Output Buffer Next Pointer
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | PTR | Pointer to the first byte in the next DMA output buffer. The read value equals the last written value until the currently used DMA output buffer is completed, and then becomes null when the last written value is transferred to the DMA controller to start on the next buffer. This event is signalized by aif_dma_out_irq. At startup, the value should be written once before and once after configuring the DMA buffer size in AIFDMACFG. At this time, the first two samples will be fetched from memory. The next pointer must be written to this register while the DMA function uses the previously written pointer. If not written in time, IRQFLAGS.PTR_ERR will be raised and all output pins will be disabled. Note the following limitations: - Address space wrapping is not supported (i.e. address(last sample) must be higher than address(first sample). - A DMA block cannot be aligned with the end of the address space (i.e. a block cannot contain the address 0xFFFF) | RW | 0x0000 0000

### TOP:I2S:AIFOUTPTR

Address offset | 0x0000 002C
Physical address | 0x4002 102C | Instance | I2S0
Description | DMA Output Buffer Current Pointer
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | PTR | Value of the DMA output buffer pointer currently used by the DMA controller Incremented by 1 (byte) or 2 (word) for each AHB access. | RW | 0x0000 0000

### TOP:I2S:STMPCTL

Address offset | 0x0000 0034
Physical address | 0x4002 1034 | Instance | I2S0
Description | SampleStaMP Generator Control Register
Type | RW

Bits | Field Name | Description | Type | Reset
31:3 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0000 0000
2 | OUT_RDY | Low until the output pins are ready to be started by the samplestamp generator. When started (i.e. STMPOUTTRIG equals the WCLK counter) the bit goes back low. | RO | 0
1 | IN_RDY | Low until the input pins are ready to be started by the samplestamp generator. When started (i.e. STMPINTRIG equals the WCLK counter) the bit goes back low. | RO | 0
0 | STMP_EN | Enables the samplestamp generator. The samplestamp generator should only be enabled after it has been properly configured. When cleared, all samplestamp generator counters and capture values are cleared. | RW | 0

### TOP:I2S:STMPXCNTCAPT0

Address offset | 0x0000 0038
Physical address | 0x4002 1038 | Instance | I2S0
Description | Captured XOSC Counter Value, Capture Channel 0
Type | RO

Bits | Field Name | Description | Type | Reset
31:16 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0000
15:0 | CAPT_VALUE | The value of the samplestamp XOSC counter (STMPXCNT.CURR_VALUE) last time an event was pulsed (event source selected in [EVENT.I2SSTMPSEL0.EV] for channel 0). This number corresponds to the number of 24 MHz clock cycles since the last positive edge of the selected WCLK. The value is cleared when STMPCTL.STMP_EN = 0. Note: Due to buffering and synchronization, WCLK is delayed by a small number of BCLK periods and clk periods. Note: When calculating the fractional part of the sample stamp, STMPXPER may be less than this bit field. | RO | 0x0000

### TOP:I2S:STMPXPER

Address offset | 0x0000 003C
Physical address | 0x4002 103C | Instance | I2S0
Description | XOSC Period Value
Type | RO

Bits | Field Name | Description | Type | Reset
31:16 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0000
15:0 | VALUE | The number of 24 MHz clock cycles in the previous WCLK period (i.e. the next value of the XOSC counter at the positive WCLK edge, had it not been reset to 0). The value is cleared when STMPCTL.STMP_EN = 0. | RO | 0x0000

### TOP:I2S:STMPWCNTCAPT0

Address offset | 0x0000 0040
Physical address | 0x4002 1040 | Instance | I2S0
Description | Captured WCLK Counter Value, Capture Channel 0
Type | RO

Bits | Field Name | Description | Type | Reset
31:16 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0000
15:0 | CAPT_VALUE | The value of the samplestamp WCLK counter (STMPWCNT.CURR_VALUE) last time an event was pulsed (event source selected in [EVENT.I2SSTMPSEL0.EV] for channel 0). This number corresponds to the number of positive WCLK edges since the samplestamp generator was enabled (not taking modification through STMPWADD/STMPWSET into account). The value is cleared when STMPCTL.STMP_EN = 0. | RO | 0x0000

### TOP:I2S:STMPWPER

Address offset | 0x0000 0044
Physical address | 0x4002 1044 | Instance | I2S0
Description | WCLK Counter Period Value
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0000
15:0 | VALUE | Used to define when STMPWCNT is to be reset so number of WCLK edges are found for the size of the sample buffer. This is thus a modulo value for the WCLK counter. This number should correspond to the size of the sample buffer used by the system (i.e. the index of the last sample plus 1). | RW | 0x0000

### TOP:I2S:STMPINTRIG

Address offset | 0x0000 0048
Physical address | 0x4002 1048 | Instance | I2S0
Description | WCLK Counter Trigger Value for Input Pins
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0000
15:0 | IN_START_WCNT | Compare value used to start the incoming audio streams. This bit field shall equal the WCLK counter value during the WCLK period in which the first input word(s) are sampled and stored to memory (i.e. the sample at the start of the very first DMA input buffer). The value of this register takes effect when the following conditions are met: - One or more pins are configured as inputs in AIFDIRCFG. - AIFDMACFG has been configured for the correct buffer size, and at least 32 BCLK cycle ticks have happened. Note: To avoid false triggers, this bit field should be set higher than STMPWPER.VALUE. | RW | 0x0000

### TOP:I2S:STMPOUTTRIG

Address offset | 0x0000 004C
Physical address | 0x4002 104C | Instance | I2S0
Description | WCLK Counter Trigger Value for Output Pins
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0000
15:0 | OUT_START_WCNT | Compare value used to start the outgoing audio streams. This bit field shall equal the WCLK counter value during the WCLK period in which the first output word(s) read from memory are clocked out (i.e. the sample at the start of the very first DMA output buffer). The value of this register takes effect when the following conditions are met: - One or more pins are configured as outputs in AIFDIRCFG. - AIFDMACFG has been configured for the correct buffer size, and 32 BCLK cycle ticks have happened. - 2 samples have been preloaded from memory (examine the AIFOUTPTR register if necessary). Note: The memory read access is only performed when required, i.e. channels 0/1 must be selected in AIFWMASK0/AIFWMASK1. Note: To avoid false triggers, this bit field should be set higher than STMPWPER.VALUE. | RW | 0x0000

### TOP:I2S:STMPWSET

Address offset | 0x0000 0050
Physical address | 0x4002 1050 | Instance | I2S0
Description | WCLK Counter Set Operation
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0000
15:0 | VALUE | WCLK counter modification: Sets the running WCLK counter equal to the written value. | RW | 0x0000

### TOP:I2S:STMPWADD

Address offset | 0x0000 0054
Physical address | 0x4002 1054 | Instance | I2S0
Description | WCLK Counter Add Operation
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0000
15:0 | VALUE_INC | WCLK counter modification: Adds the written value to the running WCLK counter. If a positive edge of WCLK occurs at the same time as the operation, this will be taken into account. This operation is typically used to adjust the WCLK counter after receiving the first WASP beacon. To add a negative value, write "STMPWPER.VALUE - value". | RW | 0x0000

### TOP:I2S:STMPXPERMIN

Address offset | 0x0000 0058
Physical address | 0x4002 1058 | Instance | I2S0
Description | XOSC Minimum Period Value Minimum Value of STMPXPER
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0000
15:0 | VALUE | Each time STMPXPER is updated, the value is also loaded into this register, provided that the value is smaller than the current value in this register. When written, the register is reset to 0xFFFF (65535), regardless of the value written. The minimum value can be used to detect extra WCLK pulses (this registers value will be significantly smaller than STMPXPER.VALUE). | RW | 0xFFFF

### TOP:I2S:STMPWCNT

Address offset | 0x0000 005C
Physical address | 0x4002 105C | Instance | I2S0
Description | Current Value of WCNT
Type | RO

Bits | Field Name | Description | Type | Reset
31:16 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0000
15:0 | CURR_VALUE | Current value of the WCLK counter | RO | 0x0000

### TOP:I2S:STMPXCNT

Address offset | 0x0000 0060
Physical address | 0x4002 1060 | Instance | I2S0
Description | Current Value of XCNT
Type | RO

Bits | Field Name | Description | Type | Reset
31:16 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0000
15:0 | CURR_VALUE | Current value of the XOSC counter, latched when reading STMPWCNT. | RO | 0x0000

### TOP:I2S:STMPXCNTCAPT1

Address offset | 0x0000 0064
Physical address | 0x4002 1064 | Instance | I2S0
Description | Captured XOSC Counter Value, Capture Channel 1
Type | RO

Bits | Field Name | Description | Type | Reset
31:16 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0000
15:0 | CAPT_VALUE | Channel 1 is idle and can not be sampled from an external pulse as with Channel 0 STMPXCNTCAPT0 | RO | 0x0000

### TOP:I2S:STMPWCNTCAPT1

Address offset | 0x0000 0068
Physical address | 0x4002 1068 | Instance | I2S0
Description | Captured WCLK Counter Value, Capture Channel 1
Type | RO

Bits | Field Name | Description | Type | Reset
31:16 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0000
15:0 | CAPT_VALUE | Channel 1 is idle and can not be sampled from an external event as with Channel 0 STMPWCNTCAPT0 | RO | 0x0000

### TOP:I2S:IRQMASK

Address offset | 0x0000 0070
Physical address | 0x4002 1070 | Instance | I2S0
Description | I2S Masked Interrupt Status Register
Type | RW

Bits | Field Name | Description | Type | Reset
31:6 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text) | RW | 0x000 0000
5 | AIF_DMA_IN | Defines the masks state for the interrupt of IRQFLAGS.AIF_DMA_IN 0: Disable 1: Enable | RW | 0
4 | AIF_DMA_OUT | Defines the masks state for the interrupt of IRQFLAGS.AIF_DMA_OUT 0: Disable 1: Enable | RW | 0
3 | WCLK_TIMEOUT | Defines the masks state for the interrupt of IRQFLAGS.WCLK_TIMEOUT 0: Disable 1: Enable | RW | 0
2 | BUS_ERR | Defines the masks state for the interrupt of IRQFLAGS.BUS_ERR 0: Disable 1: Enable | RW | 0
1 | WCLK_ERR | Defines the masks state for the interrupt of IRQFLAGS.WCLK_ERR 0: Disable 1: Enable | RW | 0
0 | PTR_ERR | Defines the masks state for the interrupt of IRQFLAGS.PTR_ERR 0: Disable 1: Enable | RW | 0

### TOP:I2S:IRQFLAGS

Address offset | 0x0000 0074
Physical address | 0x4002 1074 | Instance | I2S0
Description | I2S Raw Interrupt Status Register
Type | RO

Bits | Field Name | Description | Type | Reset
31:6 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x000 0000
5 | AIF_DMA_IN | Set when condition for this bit field event occurs (auto cleared when input pointer is updated - AIFINPTR), see description of AIFINPTR register | RO | 0
4 | AIF_DMA_OUT | Set when condition for this bit field event occurs (auto cleared when output pointer is updated - AIFOUTPTR), see description of AIFOUTPTR register for details | RO | 0
3 | WCLK_TIMEOUT | Set when the sample stamp generator does not detect a positive WCLK edge for 65535 clk periods. This signalizes that the internal or external BCLK and WCLK generator source has been disabled. The bit is sticky and may only be cleared by software (by writing '1' to IRQCLR.WCLK_TIMEOUT). | RO | 0
2 | BUS_ERR | Set when a DMA operation is not completed in time (i.e. audio output buffer underflow, or audio input buffer overflow). This error requires a complete restart since word synchronization has been lost. The bit is sticky and may only be cleared by software (by writing '1' to IRQCLR.BUS_ERR). | RO | 0
1 | WCLK_ERR | Set when: - An unexpected WCLK edge occurs during the data delay period of a phase. Note unexpected WCLK edges during the word and idle periods of the phase are not detected. - In dual-phase mode, when two WCLK edges are less than 4 BCLK cycles apart. - In single-phase mode, when a WCLK pulse occurs before the last channel. This error requires a complete restart since word synchronization has been lost. The bit is sticky and may only be cleared by software (by writing '1' to IRQCLR.WCLK_ERR). | RO | 0
0 | PTR_ERR | Set when AIFINPTRNEXT or AIFOUTPTRNEXT has not been loaded with the next block address in time. This error requires a complete restart since word synchronization has been lost. The bit is sticky and may only be cleared by software (by writing '1' to IRQCLR.PTR_ERR). | RO | 0

### TOP:I2S:IRQSET

Address offset | 0x0000 0078
Physical address | 0x4002 1078 | Instance | I2S0
Description | I2S Interrupt Set Register
Type | WO

Bits | Field Name | Description | Type | Reset
31:6 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(WO std text) | WO | 0x000 0000
5 | AIF_DMA_IN | 1: Sets the interrupt of IRQFLAGS.AIF_DMA_IN (unless a auto clear criteria was given at the same time, in which the set will be ignored) | WO | 0
4 | AIF_DMA_OUT | 1: Sets the interrupt of IRQFLAGS.AIF_DMA_OUT (unless a auto clear criteria was given at the same time, in which the set will be ignored) | WO | 0
3 | WCLK_TIMEOUT | 1: Sets the interrupt of IRQFLAGS.WCLK_TIMEOUT | WO | 0
2 | BUS_ERR | 1: Sets the interrupt of IRQFLAGS.BUS_ERR | WO | 0
1 | WCLK_ERR | 1: Sets the interrupt of IRQFLAGS.WCLK_ERR | WO | 0
0 | PTR_ERR | 1: Sets the interrupt of IRQFLAGS.PTR_ERR | WO | 0

### TOP:I2S:IRQCLR

Address offset | 0x0000 007C
Physical address | 0x4002 107C | Instance | I2S0
Description | I2S Interrupt Clear Register
Type | WO

Bits | Field Name | Description | Type | Reset
31:6 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(WO std text) | WO | 0x000 0000
5 | AIF_DMA_IN | 1: Clears the interrupt of IRQFLAGS.AIF_DMA_IN (unless a set criteria was given at the same time in which the clear will be ignored) | WO | 0
4 | AIF_DMA_OUT | 1: Clears the interrupt of IRQFLAGS.AIF_DMA_OUT (unless a set criteria was given at the same time in which the clear will be ignored) | WO | 0
3 | WCLK_TIMEOUT | 1: Clears the interrupt of IRQFLAGS.WCLK_TIMEOUT (unless a set criteria was given at the same time in which the clear will be ignored) | WO | 0
2 | BUS_ERR | 1: Clears the interrupt of IRQFLAGS.BUS_ERR (unless a set criteria was given at the same time in which the clear will be ignored) | WO | 0
1 | WCLK_ERR | 1: Clears the interrupt of IRQFLAGS.WCLK_ERR (unless a set criteria was given at the same time in which the clear will be ignored) | WO | 0
0 | PTR_ERR | 1: Clears the interrupt of IRQFLAGS.PTR_ERR (unless a set criteria was given at the same time in which the clear will be ignored) | WO | 0