## EVENT

Instance: EVENT
Component: EVENT
Base address: 0x40083000

Event Fabric Component Definition

### TOP:EVENT Register Summary

Register Name | Type | Register Width (Bits) | Register Reset | Address Offset | Physical Address
CPUIRQSEL0 | RO | 32 | 0x0000 0004 | 0x0000 0000 | 0x4008 3000
CPUIRQSEL1 | RO | 32 | 0x0000 0009 | 0x0000 0004 | 0x4008 3004
CPUIRQSEL2 | RO | 32 | 0x0000 001E | 0x0000 0008 | 0x4008 3008
CPUIRQSEL3 | RO | 32 | 0x0000 0038 | 0x0000 000C | 0x4008 300C
CPUIRQSEL4 | RO | 32 | 0x0000 0007 | 0x0000 0010 | 0x4008 3010
CPUIRQSEL5 | RO | 32 | 0x0000 0024 | 0x0000 0014 | 0x4008 3014
CPUIRQSEL6 | RO | 32 | 0x0000 001C | 0x0000 0018 | 0x4008 3018
CPUIRQSEL7 | RO | 32 | 0x0000 0022 | 0x0000 001C | 0x4008 301C
CPUIRQSEL8 | RO | 32 | 0x0000 0023 | 0x0000 0020 | 0x4008 3020
CPUIRQSEL9 | RO | 32 | 0x0000 001B | 0x0000 0024 | 0x4008 3024
CPUIRQSEL10 | RO | 32 | 0x0000 001A | 0x0000 0028 | 0x4008 3028
CPUIRQSEL11 | RO | 32 | 0x0000 0019 | 0x0000 002C | 0x4008 302C
CPUIRQSEL12 | RO | 32 | 0x0000 0008 | 0x0000 0030 | 0x4008 3030
CPUIRQSEL13 | RO | 32 | 0x0000 001D | 0x0000 0034 | 0x4008 3034
CPUIRQSEL14 | RO | 32 | 0x0000 0018 | 0x0000 0038 | 0x4008 3038
CPUIRQSEL15 | RO | 32 | 0x0000 0010 | 0x0000 003C | 0x4008 303C
CPUIRQSEL16 | RO | 32 | 0x0000 0011 | 0x0000 0040 | 0x4008 3040
CPUIRQSEL17 | RO | 32 | 0x0000 0012 | 0x0000 0044 | 0x4008 3044
CPUIRQSEL18 | RO | 32 | 0x0000 0013 | 0x0000 0048 | 0x4008 3048
CPUIRQSEL19 | RO | 32 | 0x0000 000C | 0x0000 004C | 0x4008 304C
CPUIRQSEL20 | RO | 32 | 0x0000 000D | 0x0000 0050 | 0x4008 3050
CPUIRQSEL21 | RO | 32 | 0x0000 000E | 0x0000 0054 | 0x4008 3054
CPUIRQSEL22 | RO | 32 | 0x0000 000F | 0x0000 0058 | 0x4008 3058
CPUIRQSEL23 | RO | 32 | 0x0000 005D | 0x0000 005C | 0x4008 305C
CPUIRQSEL24 | RO | 32 | 0x0000 0027 | 0x0000 0060 | 0x4008 3060
CPUIRQSEL25 | RO | 32 | 0x0000 0026 | 0x0000 0064 | 0x4008 3064
CPUIRQSEL26 | RO | 32 | 0x0000 0015 | 0x0000 0068 | 0x4008 3068
CPUIRQSEL27 | RO | 32 | 0x0000 0064 | 0x0000 006C | 0x4008 306C
CPUIRQSEL28 | RO | 32 | 0x0000 000B | 0x0000 0070 | 0x4008 3070
CPUIRQSEL29 | RO | 32 | 0x0000 0001 | 0x0000 0074 | 0x4008 3074
CPUIRQSEL30 | RW | 32 | 0x0000 0000 | 0x0000 0078 | 0x4008 3078
CPUIRQSEL31 | RO | 32 | 0x0000 006A | 0x0000 007C | 0x4008 307C
CPUIRQSEL32 | RO | 32 | 0x0000 0073 | 0x0000 0080 | 0x4008 3080
CPUIRQSEL33 | RO | 32 | 0x0000 0068 | 0x0000 0084 | 0x4008 3084
RFCSEL0 | RO | 32 | 0x0000 003D | 0x0000 0100 | 0x4008 3100
RFCSEL1 | RO | 32 | 0x0000 003E | 0x0000 0104 | 0x4008 3104
RFCSEL2 | RO | 32 | 0x0000 003F | 0x0000 0108 | 0x4008 3108
RFCSEL3 | RO | 32 | 0x0000 0040 | 0x0000 010C | 0x4008 310C
RFCSEL4 | RO | 32 | 0x0000 0041 | 0x0000 0110 | 0x4008 3110
RFCSEL5 | RO | 32 | 0x0000 0042 | 0x0000 0114 | 0x4008 3114
RFCSEL6 | RO | 32 | 0x0000 0043 | 0x0000 0118 | 0x4008 3118
RFCSEL7 | RO | 32 | 0x0000 0044 | 0x0000 011C | 0x4008 311C
RFCSEL8 | RO | 32 | 0x0000 0077 | 0x0000 0120 | 0x4008 3120
RFCSEL9 | RW | 32 | 0x0000 0002 | 0x0000 0124 | 0x4008 3124
GPT0ACAPTSEL | RW | 32 | 0x0000 0055 | 0x0000 0200 | 0x4008 3200
GPT0BCAPTSEL | RW | 32 | 0x0000 0056 | 0x0000 0204 | 0x4008 3204
GPT1ACAPTSEL | RW | 32 | 0x0000 0057 | 0x0000 0300 | 0x4008 3300
GPT1BCAPTSEL | RW | 32 | 0x0000 0058 | 0x0000 0304 | 0x4008 3304
GPT2ACAPTSEL | RW | 32 | 0x0000 0059 | 0x0000 0400 | 0x4008 3400
GPT2BCAPTSEL | RW | 32 | 0x0000 005A | 0x0000 0404 | 0x4008 3404
UDMACH1SSEL | RO | 32 | 0x0000 0031 | 0x0000 0508 | 0x4008 3508
UDMACH1BSEL | RO | 32 | 0x0000 0030 | 0x0000 050C | 0x4008 350C
UDMACH2SSEL | RO | 32 | 0x0000 0033 | 0x0000 0510 | 0x4008 3510
UDMACH2BSEL | RO | 32 | 0x0000 0032 | 0x0000 0514 | 0x4008 3514
UDMACH3SSEL | RO | 32 | 0x0000 0029 | 0x0000 0518 | 0x4008 3518
UDMACH3BSEL | RO | 32 | 0x0000 0028 | 0x0000 051C | 0x4008 351C
UDMACH4SSEL | RO | 32 | 0x0000 002B | 0x0000 0520 | 0x4008 3520
UDMACH4BSEL | RO | 32 | 0x0000 002A | 0x0000 0524 | 0x4008 3524
UDMACH5SSEL | RO | 32 | 0x0000 003A | 0x0000 0528 | 0x4008 3528
UDMACH5BSEL | RO | 32 | 0x0000 0039 | 0x0000 052C | 0x4008 352C
UDMACH6SSEL | RO | 32 | 0x0000 003C | 0x0000 0530 | 0x4008 3530
UDMACH6BSEL | RO | 32 | 0x0000 003B | 0x0000 0534 | 0x4008 3534
UDMACH7SSEL | RO | 32 | 0x0000 0075 | 0x0000 0538 | 0x4008 3538
UDMACH7BSEL | RO | 32 | 0x0000 0076 | 0x0000 053C | 0x4008 353C
UDMACH8SSEL | RO | 32 | 0x0000 0074 | 0x0000 0540 | 0x4008 3540
UDMACH8BSEL | RO | 32 | 0x0000 0074 | 0x0000 0544 | 0x4008 3544
UDMACH9SSEL | RW | 32 | 0x0000 0045 | 0x0000 0548 | 0x4008 3548
UDMACH9BSEL | RW | 32 | 0x0000 004D | 0x0000 054C | 0x4008 354C
UDMACH10SSEL | RW | 32 | 0x0000 0046 | 0x0000 0550 | 0x4008 3550
UDMACH10BSEL | RW | 32 | 0x0000 004E | 0x0000 0554 | 0x4008 3554
UDMACH11SSEL | RW | 32 | 0x0000 0047 | 0x0000 0558 | 0x4008 3558
UDMACH11BSEL | RW | 32 | 0x0000 004F | 0x0000 055C | 0x4008 355C
UDMACH12SSEL | RW | 32 | 0x0000 0048 | 0x0000 0560 | 0x4008 3560
UDMACH12BSEL | RW | 32 | 0x0000 0050 | 0x0000 0564 | 0x4008 3564
UDMACH13BSEL | RO | 32 | 0x0000 0003 | 0x0000 056C | 0x4008 356C
UDMACH14BSEL | RW | 32 | 0x0000 0001 | 0x0000 0574 | 0x4008 3574
UDMACH15BSEL | RO | 32 | 0x0000 0007 | 0x0000 057C | 0x4008 357C
UDMACH16SSEL | RO | 32 | 0x0000 002D | 0x0000 0580 | 0x4008 3580
UDMACH16BSEL | RO | 32 | 0x0000 002C | 0x0000 0584 | 0x4008 3584
UDMACH17SSEL | RO | 32 | 0x0000 002F | 0x0000 0588 | 0x4008 3588
UDMACH17BSEL | RO | 32 | 0x0000 002E | 0x0000 058C | 0x4008 358C
UDMACH21SSEL | RO | 32 | 0x0000 0064 | 0x0000 05A8 | 0x4008 35A8
UDMACH21BSEL | RO | 32 | 0x0000 0064 | 0x0000 05AC | 0x4008 35AC
UDMACH22SSEL | RO | 32 | 0x0000 0065 | 0x0000 05B0 | 0x4008 35B0
UDMACH22BSEL | RO | 32 | 0x0000 0065 | 0x0000 05B4 | 0x4008 35B4
UDMACH23SSEL | RO | 32 | 0x0000 0066 | 0x0000 05B8 | 0x4008 35B8
UDMACH23BSEL | RO | 32 | 0x0000 0066 | 0x0000 05BC | 0x4008 35BC
UDMACH24SSEL | RO | 32 | 0x0000 0067 | 0x0000 05C0 | 0x4008 35C0
UDMACH24BSEL | RO | 32 | 0x0000 0067 | 0x0000 05C4 | 0x4008 35C4
GPT3ACAPTSEL | RW | 32 | 0x0000 005B | 0x0000 0600 | 0x4008 3600
GPT3BCAPTSEL | RW | 32 | 0x0000 005C | 0x0000 0604 | 0x4008 3604
AUXSEL0 | RW | 32 | 0x0000 0010 | 0x0000 0700 | 0x4008 3700
CM3NMISEL0 | RO | 32 | 0x0000 0063 | 0x0000 0800 | 0x4008 3800
I2SSTMPSEL0 | RW | 32 | 0x0000 005F | 0x0000 0900 | 0x4008 3900
FRZSEL0 | RW | 32 | 0x0000 0078 | 0x0000 0A00 | 0x4008 3A00
SWEV | RW | 32 | 0x0000 0000 | 0x0000 0F00 | 0x4008 3F00

### TOP:EVENT Register Descriptions

### TOP:EVENT:CPUIRQSEL0

Address offset | 0x0000 0000
Physical address | 0x4008 3000 | Instance | EVENT
Description | Output Selection for CPU Interrupt 0
Type | RO

Bits | Field Name | Description | Type | Reset
31:7 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x000 0000
6:0 | EV | Read only selection value
Value | ENUM name | Description
0x04 | AON_GPIO_EDGE | Edge detect event from IOC. Configureded by the IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET settings
| RO | 0x04

### TOP:EVENT:CPUIRQSEL1

Address offset | 0x0000 0004
Physical address | 0x4008 3004 | Instance | EVENT
Description | Output Selection for CPU Interrupt 1
Type | RO

Bits | Field Name | Description | Type | Reset
31:7 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x000 0000
6:0 | EV | Read only selection value
Value | ENUM name | Description
0x09 | I2C_IRQ | Interrupt event from I2C
| RO | 0x09

### TOP:EVENT:CPUIRQSEL2

Address offset | 0x0000 0008
Physical address | 0x4008 3008 | Instance | EVENT
Description | Output Selection for CPU Interrupt 2
Type | RO

Bits | Field Name | Description | Type | Reset
31:7 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x000 0000
6:0 | EV | Read only selection value
Value | ENUM name | Description
0x1E | RFC_CPE_1 | Combined Interrupt for CPE Generated events. Corresponding flags are here RFC_DBELL:RFCPEIFG. Only interrupts selected with CPE1 in RFC_DBELL:RFCPEIFG can trigger a RFC_CPE_1 event
| RO | 0x1E

### TOP:EVENT:CPUIRQSEL3

Address offset | 0x0000 000C
Physical address | 0x4008 300C | Instance | EVENT
Description | Output Selection for CPU Interrupt 3
Type | RO

Bits | Field Name | Description | Type | Reset
31:7 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x000 0000
6:0 | EV | Read only selection value
Value | ENUM name | Description
0x38 | SPIS_COMB | SPIS Combined event, the flags are found here SPIS:GPFLAGS
| RO | 0x38

### TOP:EVENT:CPUIRQSEL4

Address offset | 0x0000 0010
Physical address | 0x4008 3010 | Instance | EVENT
Description | Output Selection for CPU Interrupt 4
Type | RO

Bits | Field Name | Description | Type | Reset
31:7 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x000 0000
6:0 | EV | Read only selection value
Value | ENUM name | Description
0x07 | AON_RTC_COMB | Event from AON_RTC controlled by the AON_RTC:CTL.COMB_EV_MASK setting
| RO | 0x07

### TOP:EVENT:CPUIRQSEL5

Address offset | 0x0000 0014
Physical address | 0x4008 3014 | Instance | EVENT
Description | Output Selection for CPU Interrupt 5
Type | RO

Bits | Field Name | Description | Type | Reset
31:7 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x000 0000
6:0 | EV | Read only selection value
Value | ENUM name | Description
0x24 | UART0_COMB | UART0 combined interrupt, interrupt flags are found here UART0:MIS
| RO | 0x24

### TOP:EVENT:CPUIRQSEL6

Address offset | 0x0000 0018
Physical address | 0x4008 3018 | Instance | EVENT
Description | Output Selection for CPU Interrupt 6
Type | RO

Bits | Field Name | Description | Type | Reset
31:7 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x000 0000
6:0 | EV | Read only selection value
Value | ENUM name | Description
0x1C | AUX_SWEV0 | AUX software event 0, triggered by AUX_EVCTL:SWEVSET.SWEV0, also available as AUX_EVENT0 AON wake up event. MCU domain wakeup control AON_EVENT:MCUWUSEL AUX domain wakeup control AON_EVENT:AUXWUSEL
| RO | 0x1C

### TOP:EVENT:CPUIRQSEL7

Address offset | 0x0000 001C
Physical address | 0x4008 301C | Instance | EVENT
Description | Output Selection for CPU Interrupt 7
Type | RO

Bits | Field Name | Description | Type | Reset
31:7 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x000 0000
6:0 | EV | Read only selection value
Value | ENUM name | Description
0x22 | SSI0_COMB | SSI0 combined interrupt, interrupt flags are found here SSI0:MIS
| RO | 0x22

### TOP:EVENT:CPUIRQSEL8

Address offset | 0x0000 0020
Physical address | 0x4008 3020 | Instance | EVENT
Description | Output Selection for CPU Interrupt 8
Type | RO

Bits | Field Name | Description | Type | Reset
31:7 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x000 0000
6:0 | EV | Read only selection value
Value | ENUM name | Description
0x23 | SSI1_COMB | SSI0 combined interrupt, interrupt flags are found here SSI1:MIS
| RO | 0x23

### TOP:EVENT:CPUIRQSEL9

Address offset | 0x0000 0024
Physical address | 0x4008 3024 | Instance | EVENT
Description | Output Selection for CPU Interrupt 9
Type | RO

Bits | Field Name | Description | Type | Reset
31:7 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x000 0000
6:0 | EV | Read only selection value
Value | ENUM name | Description
0x1B | RFC_CPE_0 | Combined Interrupt for CPE Generated events. Corresponding flags are here RFC_DBELL:RFCPEIFG. Only interrupts selected with CPE0 in RFC_DBELL:RFCPEIFG can trigger a RFC_CPE_0 event
| RO | 0x1B

### TOP:EVENT:CPUIRQSEL10

Address offset | 0x0000 0028
Physical address | 0x4008 3028 | Instance | EVENT
Description | Output Selection for CPU Interrupt 10
Type | RO

Bits | Field Name | Description | Type | Reset
31:7 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x000 0000
6:0 | EV | Read only selection value
Value | ENUM name | Description
0x1A | RFC_HW_COMB | Combined RCF hardware interrupt, corresponding flag is here RFC_DBELL:RFHWIFG
| RO | 0x1A

### TOP:EVENT:CPUIRQSEL11

Address offset | 0x0000 002C
Physical address | 0x4008 302C | Instance | EVENT
Description | Output Selection for CPU Interrupt 11
Type | RO

Bits | Field Name | Description | Type | Reset
31:7 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x000 0000
6:0 | EV | Read only selection value
Value | ENUM name | Description
0x19 | RFC_CMD_ACK | RFC Doorbell Command Acknowledgement Interrupt, equvialent to RFC_DBELL:RFACKIFG.ACKFLAG
| RO | 0x19

### TOP:EVENT:CPUIRQSEL12

Address offset | 0x0000 0030
Physical address | 0x4008 3030 | Instance | EVENT
Description | Output Selection for CPU Interrupt 12
Type | RO

Bits | Field Name | Description | Type | Reset
31:7 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x000 0000
6:0 | EV | Read only selection value
Value | ENUM name | Description
0x08 | I2S_IRQ | Interrupt event from I2S
| RO | 0x08

### TOP:EVENT:CPUIRQSEL13

Address offset | 0x0000 0034
Physical address | 0x4008 3034 | Instance | EVENT
Description | Output Selection for CPU Interrupt 13
Type | RO

Bits | Field Name | Description | Type | Reset
31:7 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x000 0000
6:0 | EV | Read only selection value
Value | ENUM name | Description
0x1D | AUX_SWEV1 | AUX software event 1, triggered by AUX_EVCTL:SWEVSET.SWEV1, also available as AUX_EVENT2 AON wake up event. MCU domain wakeup control AON_EVENT:MCUWUSEL AUX domain wakeup control AON_EVENT:AUXWUSEL
| RO | 0x1D

### TOP:EVENT:CPUIRQSEL14

Address offset | 0x0000 0038
Physical address | 0x4008 3038 | Instance | EVENT
Description | Output Selection for CPU Interrupt 14
Type | RO

Bits | Field Name | Description | Type | Reset
31:7 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x000 0000
6:0 | EV | Read only selection value
Value | ENUM name | Description
0x18 | WDT_IRQ | Watchdog interrupt event, controlled by WDT:CTL.INTEN
| RO | 0x18

### TOP:EVENT:CPUIRQSEL15

Address offset | 0x0000 003C
Physical address | 0x4008 303C | Instance | EVENT
Description | Output Selection for CPU Interrupt 15
Type | RO

Bits | Field Name | Description | Type | Reset
31:7 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x000 0000
6:0 | EV | Read only selection value
Value | ENUM name | Description
0x10 | GPT0A | GPT0A interrupt event, controlled by GPT0:TAMR
| RO | 0x10

### TOP:EVENT:CPUIRQSEL16

Address offset | 0x0000 0040
Physical address | 0x4008 3040 | Instance | EVENT
Description | Output Selection for CPU Interrupt 16
Type | RO

Bits | Field Name | Description | Type | Reset
31:7 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x000 0000
6:0 | EV | Read only selection value
Value | ENUM name | Description
0x11 | GPT0B | GPT0B interrupt event, controlled by GPT0:TBMR
| RO | 0x11

### TOP:EVENT:CPUIRQSEL17

Address offset | 0x0000 0044
Physical address | 0x4008 3044 | Instance | EVENT
Description | Output Selection for CPU Interrupt 17
Type | RO

Bits | Field Name | Description | Type | Reset
31:7 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x000 0000
6:0 | EV | Read only selection value
Value | ENUM name | Description
0x12 | GPT1A | GPT1A interrupt event, controlled by GPT1:TAMR
| RO | 0x12

### TOP:EVENT:CPUIRQSEL18

Address offset | 0x0000 0048
Physical address | 0x4008 3048 | Instance | EVENT
Description | Output Selection for CPU Interrupt 18
Type | RO

Bits | Field Name | Description | Type | Reset
31:7 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x000 0000
6:0 | EV | Read only selection value
Value | ENUM name | Description
0x13 | GPT1B | GPT1B interrupt event, controlled by GPT1:TBMR
| RO | 0x13

### TOP:EVENT:CPUIRQSEL19

Address offset | 0x0000 004C
Physical address | 0x4008 304C | Instance | EVENT
Description | Output Selection for CPU Interrupt 19
Type | RO

Bits | Field Name | Description | Type | Reset
31:7 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x000 0000
6:0 | EV | Read only selection value
Value | ENUM name | Description
0x0C | GPT2A | GPT2A interrupt event, controlled by GPT2:TAMR
| RO | 0x0C

### TOP:EVENT:CPUIRQSEL20

Address offset | 0x0000 0050
Physical address | 0x4008 3050 | Instance | EVENT
Description | Output Selection for CPU Interrupt 20
Type | RO

Bits | Field Name | Description | Type | Reset
31:7 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x000 0000
6:0 | EV | Read only selection value
Value | ENUM name | Description
0x0D | GPT2B | GPT2B interrupt event, controlled by GPT2:TBMR
| RO | 0x0D

### TOP:EVENT:CPUIRQSEL21

Address offset | 0x0000 0054
Physical address | 0x4008 3054 | Instance | EVENT
Description | Output Selection for CPU Interrupt 21
Type | RO

Bits | Field Name | Description | Type | Reset
31:7 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x000 0000
6:0 | EV | Read only selection value
Value | ENUM name | Description
0x0E | GPT3A | GPT3A interrupt event, controlled by GPT3:TAMR
| RO | 0x0E

### TOP:EVENT:CPUIRQSEL22

Address offset | 0x0000 0058
Physical address | 0x4008 3058 | Instance | EVENT
Description | Output Selection for CPU Interrupt 22
Type | RO

Bits | Field Name | Description | Type | Reset
31:7 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x000 0000
6:0 | EV | Read only selection value
Value | ENUM name | Description
0x0F | GPT3B | GPT3B interrupt event, controlled by GPT3:TBMR
| RO | 0x0F

### TOP:EVENT:CPUIRQSEL23

Address offset | 0x0000 005C
Physical address | 0x4008 305C | Instance | EVENT
Description | Output Selection for CPU Interrupt 23
Type | RO

Bits | Field Name | Description | Type | Reset
31:7 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x000 0000
6:0 | EV | Read only selection value
Value | ENUM name | Description
0x5D | CRYPTO_RESULT_AVAIL_IRQ | CRYPTO result available interupt event, the corresponding flag is found here CRYPTO:IRQSTAT.RESULT_AVAIL. Controlled by CRYPTO:IRQSTAT.RESULT_AVAIL
| RO | 0x5D

### TOP:EVENT:CPUIRQSEL24

Address offset | 0x0000 0060
Physical address | 0x4008 3060 | Instance | EVENT
Description | Output Selection for CPU Interrupt 24
Type | RO

Bits | Field Name | Description | Type | Reset
31:7 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x000 0000
6:0 | EV | Read only selection value
Value | ENUM name | Description
0x27 | DMA_DONE_COMB | Combined DMA done corresponding flags are here UDMA0:REQDONE
| RO | 0x27

### TOP:EVENT:CPUIRQSEL25

Address offset | 0x0000 0064
Physical address | 0x4008 3064 | Instance | EVENT
Description | Output Selection for CPU Interrupt 25
Type | RO

Bits | Field Name | Description | Type | Reset
31:7 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x000 0000
6:0 | EV | Read only selection value
Value | ENUM name | Description
0x26 | DMA_ERR | DMA bus error, corresponds to UDMA0:ERROR.STATUS
| RO | 0x26

### TOP:EVENT:CPUIRQSEL26

Address offset | 0x0000 0068
Physical address | 0x4008 3068 | Instance | EVENT
Description | Output Selection for CPU Interrupt 26
Type | RO

Bits | Field Name | Description | Type | Reset
31:7 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x000 0000
6:0 | EV | Read only selection value
Value | ENUM name | Description
0x15 | FLASH | FLASH controller error event, the status flags are FLASH:FEDACSTAT.FSM_DONE and FLASH:FEDACSTAT.RVF_INT
| RO | 0x15

### TOP:EVENT:CPUIRQSEL27

Address offset | 0x0000 006C
Physical address | 0x4008 306C | Instance | EVENT
Description | Output Selection for CPU Interrupt 27
Type | RO

Bits | Field Name | Description | Type | Reset
31:7 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x000 0000
6:0 | EV | Read only selection value
Value | ENUM name | Description
0x64 | SWEV0 | Software event 0, triggered by SWEV.SWEV0
| RO | 0x64

### TOP:EVENT:CPUIRQSEL28

Address offset | 0x0000 0070
Physical address | 0x4008 3070 | Instance | EVENT
Description | Output Selection for CPU Interrupt 28
Type | RO

Bits | Field Name | Description | Type | Reset
31:7 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x000 0000
6:0 | EV | Read only selection value
Value | ENUM name | Description
0x0B | AUX_COMB | AUX combined event, the corresponding flag register is here AUX_EVCTL:EVTOMCUFLAGS
| RO | 0x0B

### TOP:EVENT:CPUIRQSEL29

Address offset | 0x0000 0074
Physical address | 0x4008 3074 | Instance | EVENT
Description | Output Selection for CPU Interrupt 29
Type | RO

Bits | Field Name | Description | Type | Reset
31:7 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x000 0000
6:0 | EV | Read only selection value
Value | ENUM name | Description
0x01 | AON_PROG0 | Event selected by AON_EVENT MCU event selector, AON_EVENT:EVTOMCUSEL.AON_PROG0_EV
| RO | 0x01

### TOP:EVENT:CPUIRQSEL30

Address offset | 0x0000 0078
Physical address | 0x4008 3078 | Instance | EVENT
Description | Output Selection for CPU Interrupt 30
Type | RW

Bits | Field Name | Description | Type | Reset
31:7 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x000 0000
6:0 | EV | Read/write selection value
Value | ENUM name | Description
0x00 | NONE | Always inactive
0x02 | AON_PROG1 | Event selected by AON_EVENT MCU event selector, AON_EVENT:EVTOMCUSEL.AON_PROG1_EV
0x03 | AON_PROG2 | Event selected by AON_EVENT MCU event selector, AON_EVENT:EVTOMCUSEL.AON_PROG2_EV
0x05 | AON_SPIS_BYTE_DONE | A complete byte transfer event from the SPIS. Equivalent to the SPIS:GPFLAGS.BYTE_DONE flag
0x06 | AON_SPIS_CS | SPIS chip select event. Equivalent to the SPIS:GPFLAGS.CS flag
0x08 | I2S_IRQ | Interrupt event from I2S
0x0A | AON_AUX_SWEV0 | AUX Software event 0, AUX_EVCTL:SWEVSET.SWEV0
0x14 | DMA_CH0_DONE | DMA done for software tiggered UDMA channel 0, see UDMA0:SOFTREQ
0x16 | DMA_CH18_DONE | DMA done for software tiggered UDMA channel 18, see UDMA0:SOFTREQ
0x5E | CRYPTO_DMA_DONE_IRQ | CRYPTO DMA input done event, the correspondingg flag is CRYPTO:IRQSTAT.DMA_IN_DONE. Controlled by CRYPTO:IRQEN.DMA_IN_DONE
0x5F | RFC_IN_EV4 | RFC RAT event 4, configured by RFC_RAT:RATEV.OEVT4
0x60 | RFC_IN_EV5 | RFC RAT event 5, configured by RFC_RAT:RATEV.OEVT5
0x69 | AUX_AON_WU_EV | AON wakeup event, corresponds flags are here AUX_EVCTL:EVTOMCUFLAGS.AON_WU_EV
0x6B | AUX_COMPB | AUX Compare B event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPB
0x6C | AUX_TDC_DONE | AUX TDC measurement done event, corresponds to the flag AUX_EVCTL:EVTOMCUFLAGS.TDC_DONE and the AUX_TDC status AUX_TDC:STAT.DONE
0x6D | AUX_TIMER0_EV | AUX timer 0 event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.TIMER0_EV
0x6E | AUX_TIMER1_EV | AUX timer 1 event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.TIMER1_EV
0x6F | AUX_SMPH_AUTOTAKE_DONE | Autotake event from AUX semaphore, configured by AUX_SMPH:AUTOTAKE
0x70 | AUX_ADC_DONE | AUX ADC done, corresponds to AUX_EVCTL:EVTOMCUFLAGS.ADC_DONE
0x71 | AUX_ADC_FIFO_ALMOST_FULL | AUX ADC FIFO watermark event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.ADC_FIFO_ALMOST_FULL
0x72 | AUX_OBSMUX0 | Loopback of OBSMUX0 through AUX, corresponds to AUX_EVCTL:EVTOMCUFLAGS.OBSMUX0
0x77 | AON_RTC_UPD | RTC periodic event controlled by AON_RTC:CTL.RTC_UPD_EN
0x79 | ALWAYS_ACTIVE | Always asserted
| RW | 0x00

### TOP:EVENT:CPUIRQSEL31

Address offset | 0x0000 007C
Physical address | 0x4008 307C | Instance | EVENT
Description | Output Selection for CPU Interrupt 31
Type | RO

Bits | Field Name | Description | Type | Reset
31:7 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x000 0000
6:0 | EV | Read only selection value
Value | ENUM name | Description
0x6A | AUX_COMPA | AUX Compare A event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA
| RO | 0x6A

### TOP:EVENT:CPUIRQSEL32

Address offset | 0x0000 0080
Physical address | 0x4008 3080 | Instance | EVENT
Description | Output Selection for CPU Interrupt 32
Type | RO

Bits | Field Name | Description | Type | Reset
31:7 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x000 0000
6:0 | EV | Read only selection value
Value | ENUM name | Description
0x73 | AUX_ADC_IRQ | AUX ADC interrupt event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.ADC_IRQ. Status flags are found here [AUX_EVCTL:EVTOMCUFLAGS.ADC*]
| RO | 0x73

### TOP:EVENT:CPUIRQSEL33

Address offset | 0x0000 0084
Physical address | 0x4008 3084 | Instance | EVENT
Description | Output Selection for CPU Interrupt 33
Type | RO

Bits | Field Name | Description | Type | Reset
31:7 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x000 0000
6:0 | EV | Read only selection value
Value | ENUM name | Description
0x68 | TRNG_IRQ | TRNG Interrupt event, controlled by TRNG:IRQEN.EN
| RO | 0x68

### TOP:EVENT:RFCSEL0

Address offset | 0x0000 0100
Physical address | 0x4008 3100 | Instance | EVENT
Description | Output Selection for RFC Event 0
Type | RO

Bits | Field Name | Description | Type | Reset
31:7 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x000 0000
6:0 | EV | Read only selection value
Value | ENUM name | Description
0x3D | GPT0A_CMP | GPT0A compare event. Configured by GPT0:TAMR.TCACT
| RO | 0x3D

### TOP:EVENT:RFCSEL1

Address offset | 0x0000 0104
Physical address | 0x4008 3104 | Instance | EVENT
Description | Output Selection for RFC Event 1
Type | RO

Bits | Field Name | Description | Type | Reset
31:7 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x000 0000
6:0 | EV | Read only selection value
Value | ENUM name | Description
0x3E | GPT0B_CMP | GPT0B compare event. Configured by GPT0:TBMR.TCACT
| RO | 0x3E

### TOP:EVENT:RFCSEL2

Address offset | 0x0000 0108
Physical address | 0x4008 3108 | Instance | EVENT
Description | Output Selection for RFC Event 2
Type | RO

Bits | Field Name | Description | Type | Reset
31:7 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x000 0000
6:0 | EV | Read only selection value
Value | ENUM name | Description
0x3F | GPT1A_CMP | GPT1A compare event. Configured by GPT1:TAMR.TCACT
| RO | 0x3F

### TOP:EVENT:RFCSEL3

Address offset | 0x0000 010C
Physical address | 0x4008 310C | Instance | EVENT
Description | Output Selection for RFC Event 3
Type | RO

Bits | Field Name | Description | Type | Reset
31:7 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x000 0000
6:0 | EV | Read only selection value
Value | ENUM name | Description
0x40 | GPT1B_CMP | GPT1B compare event. Configured by GPT1:TBMR.TCACT
| RO | 0x40

### TOP:EVENT:RFCSEL4

Address offset | 0x0000 0110
Physical address | 0x4008 3110 | Instance | EVENT
Description | Output Selection for RFC Event 4
Type | RO

Bits | Field Name | Description | Type | Reset
31:7 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x000 0000
6:0 | EV | Read only selection value
Value | ENUM name | Description
0x41 | GPT2A_CMP | GPT2A compare event. Configured by GPT2:TAMR.TCACT
| RO | 0x41

### TOP:EVENT:RFCSEL5

Address offset | 0x0000 0114
Physical address | 0x4008 3114 | Instance | EVENT
Description | Output Selection for RFC Event 5
Type | RO

Bits | Field Name | Description | Type | Reset
31:7 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x000 0000
6:0 | EV | Read only selection value
Value | ENUM name | Description
0x42 | GPT2B_CMP | GPT2B compare event. Configured by GPT2:TBMR.TCACT
| RO | 0x42

### TOP:EVENT:RFCSEL6

Address offset | 0x0000 0118
Physical address | 0x4008 3118 | Instance | EVENT
Description | Output Selection for RFC Event 6
Type | RO

Bits | Field Name | Description | Type | Reset
31:7 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x000 0000
6:0 | EV | Read only selection value
Value | ENUM name | Description
0x43 | GPT3A_CMP | GPT3A compare event. Configured by GPT3:TAMR.TCACT
| RO | 0x43

### TOP:EVENT:RFCSEL7

Address offset | 0x0000 011C
Physical address | 0x4008 311C | Instance | EVENT
Description | Output Selection for RFC Event 7
Type | RO

Bits | Field Name | Description | Type | Reset
31:7 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x000 0000
6:0 | EV | Read only selection value
Value | ENUM name | Description
0x44 | GPT3B_CMP | GPT3B compare event. Configured by GPT3:TBMR.TCACT
| RO | 0x44

### TOP:EVENT:RFCSEL8

Address offset | 0x0000 0120
Physical address | 0x4008 3120 | Instance | EVENT
Description | Output Selection for RFC Event 8
Type | RO

Bits | Field Name | Description | Type | Reset
31:7 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x000 0000
6:0 | EV | Read only selection value
Value | ENUM name | Description
0x77 | AON_RTC_UPD | RTC periodic event controlled by AON_RTC:CTL.RTC_UPD_EN
| RO | 0x77

### TOP:EVENT:RFCSEL9

Address offset | 0x0000 0124
Physical address | 0x4008 3124 | Instance | EVENT
Description | Output Selection for RFC Event 9
Type | RW

Bits | Field Name | Description | Type | Reset
31:7 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x000 0000
6:0 | EV | Read/write selection value
Value | ENUM name | Description
0x00 | NONE | Always inactive
0x01 | AON_PROG0 | Event selected by AON_EVENT MCU event selector, AON_EVENT:EVTOMCUSEL.AON_PROG0_EV
0x02 | AON_PROG1 | Event selected by AON_EVENT MCU event selector, AON_EVENT:EVTOMCUSEL.AON_PROG1_EV
0x08 | I2S_IRQ | Interrupt event from I2S
0x0A | AON_AUX_SWEV0 | AUX Software event 0, AUX_EVCTL:SWEVSET.SWEV0
0x18 | WDT_IRQ | Watchdog interrupt event, controlled by WDT:CTL.INTEN
0x22 | SSI0_COMB | SSI0 combined interrupt, interrupt flags are found here SSI0:MIS
0x23 | SSI1_COMB | SSI0 combined interrupt, interrupt flags are found here SSI1:MIS
0x24 | UART0_COMB | UART0 combined interrupt, interrupt flags are found here UART0:MIS
0x27 | DMA_DONE_COMB | Combined DMA done corresponding flags are here UDMA0:REQDONE
0x5D | CRYPTO_RESULT_AVAIL_IRQ | CRYPTO result available interupt event, the corresponding flag is found here CRYPTO:IRQSTAT.RESULT_AVAIL. Controlled by CRYPTO:IRQSTAT.RESULT_AVAIL
0x64 | SWEV0 | Software event 0, triggered by SWEV.SWEV0
0x65 | SWEV1 | Software event 1, triggered by SWEV.SWEV1
0x69 | AUX_AON_WU_EV | AON wakeup event, corresponds flags are here AUX_EVCTL:EVTOMCUFLAGS.AON_WU_EV
0x6A | AUX_COMPA | AUX Compare A event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA
0x6B | AUX_COMPB | AUX Compare B event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPB
0x6C | AUX_TDC_DONE | AUX TDC measurement done event, corresponds to the flag AUX_EVCTL:EVTOMCUFLAGS.TDC_DONE and the AUX_TDC status AUX_TDC:STAT.DONE
0x6D | AUX_TIMER0_EV | AUX timer 0 event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.TIMER0_EV
0x6E | AUX_TIMER1_EV | AUX timer 1 event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.TIMER1_EV
0x6F | AUX_SMPH_AUTOTAKE_DONE | Autotake event from AUX semaphore, configured by AUX_SMPH:AUTOTAKE
0x70 | AUX_ADC_DONE | AUX ADC done, corresponds to AUX_EVCTL:EVTOMCUFLAGS.ADC_DONE
0x71 | AUX_ADC_FIFO_ALMOST_FULL | AUX ADC FIFO watermark event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.ADC_FIFO_ALMOST_FULL
0x72 | AUX_OBSMUX0 | Loopback of OBSMUX0 through AUX, corresponds to AUX_EVCTL:EVTOMCUFLAGS.OBSMUX0
0x73 | AUX_ADC_IRQ | AUX ADC interrupt event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.ADC_IRQ. Status flags are found here [AUX_EVCTL:EVTOMCUFLAGS.ADC*]
0x79 | ALWAYS_ACTIVE | Always asserted
| RW | 0x02

### TOP:EVENT:GPT0ACAPTSEL

Address offset | 0x0000 0200
Physical address | 0x4008 3200 | Instance | EVENT
Description | Output Selection for GPT0 0
Type | RW

Bits | Field Name | Description | Type | Reset
31:7 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x000 0000
6:0 | EV | Read/write selection value
Value | ENUM name | Description
0x00 | NONE | Always inactive
0x04 | AON_GPIO_EDGE | Edge detect event from IOC. Configureded by the IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET settings
0x05 | AON_SPIS_BYTE_DONE | A complete byte transfer event from the SPIS. Equivalent to the SPIS:GPFLAGS.BYTE_DONE flag
0x06 | AON_SPIS_CS | SPIS chip select event. Equivalent to the SPIS:GPFLAGS.CS flag
0x07 | AON_RTC_COMB | Event from AON_RTC controlled by the AON_RTC:CTL.COMB_EV_MASK setting
0x09 | I2C_IRQ | Interrupt event from I2C
0x0B | AUX_COMB | AUX combined event, the corresponding flag register is here AUX_EVCTL:EVTOMCUFLAGS
0x15 | FLASH | FLASH controller error event, the status flags are FLASH:FEDACSTAT.FSM_DONE and FLASH:FEDACSTAT.RVF_INT
0x19 | RFC_CMD_ACK | RFC Doorbell Command Acknowledgement Interrupt, equvialent to RFC_DBELL:RFACKIFG.ACKFLAG
0x1A | RFC_HW_COMB | Combined RCF hardware interrupt, corresponding flag is here RFC_DBELL:RFHWIFG
0x1B | RFC_CPE_0 | Combined Interrupt for CPE Generated events. Corresponding flags are here RFC_DBELL:RFCPEIFG. Only interrupts selected with CPE0 in RFC_DBELL:RFCPEIFG can trigger a RFC_CPE_0 event
0x1E | RFC_CPE_1 | Combined Interrupt for CPE Generated events. Corresponding flags are here RFC_DBELL:RFCPEIFG. Only interrupts selected with CPE1 in RFC_DBELL:RFCPEIFG can trigger a RFC_CPE_1 event
0x22 | SSI0_COMB | SSI0 combined interrupt, interrupt flags are found here SSI0:MIS
0x23 | SSI1_COMB | SSI0 combined interrupt, interrupt flags are found here SSI1:MIS
0x24 | UART0_COMB | UART0 combined interrupt, interrupt flags are found here UART0:MIS
0x3D | GPT0A_CMP | GPT0A compare event. Configured by GPT0:TAMR.TCACT
0x3E | GPT0B_CMP | GPT0B compare event. Configured by GPT0:TBMR.TCACT
0x3F | GPT1A_CMP | GPT1A compare event. Configured by GPT1:TAMR.TCACT
0x40 | GPT1B_CMP | GPT1B compare event. Configured by GPT1:TBMR.TCACT
0x41 | GPT2A_CMP | GPT2A compare event. Configured by GPT2:TAMR.TCACT
0x42 | GPT2B_CMP | GPT2B compare event. Configured by GPT2:TBMR.TCACT
0x43 | GPT3A_CMP | GPT3A compare event. Configured by GPT3:TAMR.TCACT
0x44 | GPT3B_CMP | GPT3B compare event. Configured by GPT3:TBMR.TCACT
0x55 | PORT_EVENT0 | Port capture event from IOC, configured by IOC:IOCFGn.PORT_ID. Events on ports configured with ENUM PORT_EVENT0 wil be routed here.
0x56 | PORT_EVENT1 | Port capture event from IOC, configured by IOC:IOCFGn.PORT_ID. Events on ports configured with ENUM PORT_EVENT1 wil be routed here.
0x5F | RFC_IN_EV4 | RFC RAT event 4, configured by RFC_RAT:RATEV.OEVT4
0x60 | RFC_IN_EV5 | RFC RAT event 5, configured by RFC_RAT:RATEV.OEVT5
0x69 | AUX_AON_WU_EV | AON wakeup event, corresponds flags are here AUX_EVCTL:EVTOMCUFLAGS.AON_WU_EV
0x6A | AUX_COMPA | AUX Compare A event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA
0x6B | AUX_COMPB | AUX Compare B event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPB
0x6C | AUX_TDC_DONE | AUX TDC measurement done event, corresponds to the flag AUX_EVCTL:EVTOMCUFLAGS.TDC_DONE and the AUX_TDC status AUX_TDC:STAT.DONE
0x6D | AUX_TIMER0_EV | AUX timer 0 event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.TIMER0_EV
0x6E | AUX_TIMER1_EV | AUX timer 1 event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.TIMER1_EV
0x6F | AUX_SMPH_AUTOTAKE_DONE | Autotake event from AUX semaphore, configured by AUX_SMPH:AUTOTAKE
0x70 | AUX_ADC_DONE | AUX ADC done, corresponds to AUX_EVCTL:EVTOMCUFLAGS.ADC_DONE
0x71 | AUX_ADC_FIFO_ALMOST_FULL | AUX ADC FIFO watermark event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.ADC_FIFO_ALMOST_FULL
0x72 | AUX_OBSMUX0 | Loopback of OBSMUX0 through AUX, corresponds to AUX_EVCTL:EVTOMCUFLAGS.OBSMUX0
0x73 | AUX_ADC_IRQ | AUX ADC interrupt event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.ADC_IRQ. Status flags are found here [AUX_EVCTL:EVTOMCUFLAGS.ADC*]
0x77 | AON_RTC_UPD | RTC periodic event controlled by AON_RTC:CTL.RTC_UPD_EN
0x79 | ALWAYS_ACTIVE | Always asserted
| RW | 0x55

### TOP:EVENT:GPT0BCAPTSEL

Address offset | 0x0000 0204
Physical address | 0x4008 3204 | Instance | EVENT
Description | Output Selection for GPT0 1
Type | RW

Bits | Field Name | Description | Type | Reset
31:7 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x000 0000
6:0 | EV | Read/write selection value
Value | ENUM name | Description
0x00 | NONE | Always inactive
0x04 | AON_GPIO_EDGE | Edge detect event from IOC. Configureded by the IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET settings
0x05 | AON_SPIS_BYTE_DONE | A complete byte transfer event from the SPIS. Equivalent to the SPIS:GPFLAGS.BYTE_DONE flag
0x06 | AON_SPIS_CS | SPIS chip select event. Equivalent to the SPIS:GPFLAGS.CS flag
0x07 | AON_RTC_COMB | Event from AON_RTC controlled by the AON_RTC:CTL.COMB_EV_MASK setting
0x09 | I2C_IRQ | Interrupt event from I2C
0x0B | AUX_COMB | AUX combined event, the corresponding flag register is here AUX_EVCTL:EVTOMCUFLAGS
0x15 | FLASH | FLASH controller error event, the status flags are FLASH:FEDACSTAT.FSM_DONE and FLASH:FEDACSTAT.RVF_INT
0x19 | RFC_CMD_ACK | RFC Doorbell Command Acknowledgement Interrupt, equvialent to RFC_DBELL:RFACKIFG.ACKFLAG
0x1A | RFC_HW_COMB | Combined RCF hardware interrupt, corresponding flag is here RFC_DBELL:RFHWIFG
0x1B | RFC_CPE_0 | Combined Interrupt for CPE Generated events. Corresponding flags are here RFC_DBELL:RFCPEIFG. Only interrupts selected with CPE0 in RFC_DBELL:RFCPEIFG can trigger a RFC_CPE_0 event
0x1E | RFC_CPE_1 | Combined Interrupt for CPE Generated events. Corresponding flags are here RFC_DBELL:RFCPEIFG. Only interrupts selected with CPE1 in RFC_DBELL:RFCPEIFG can trigger a RFC_CPE_1 event
0x22 | SSI0_COMB | SSI0 combined interrupt, interrupt flags are found here SSI0:MIS
0x23 | SSI1_COMB | SSI0 combined interrupt, interrupt flags are found here SSI1:MIS
0x24 | UART0_COMB | UART0 combined interrupt, interrupt flags are found here UART0:MIS
0x3D | GPT0A_CMP | GPT0A compare event. Configured by GPT0:TAMR.TCACT
0x3E | GPT0B_CMP | GPT0B compare event. Configured by GPT0:TBMR.TCACT
0x3F | GPT1A_CMP | GPT1A compare event. Configured by GPT1:TAMR.TCACT
0x40 | GPT1B_CMP | GPT1B compare event. Configured by GPT1:TBMR.TCACT
0x41 | GPT2A_CMP | GPT2A compare event. Configured by GPT2:TAMR.TCACT
0x42 | GPT2B_CMP | GPT2B compare event. Configured by GPT2:TBMR.TCACT
0x43 | GPT3A_CMP | GPT3A compare event. Configured by GPT3:TAMR.TCACT
0x44 | GPT3B_CMP | GPT3B compare event. Configured by GPT3:TBMR.TCACT
0x55 | PORT_EVENT0 | Port capture event from IOC, configured by IOC:IOCFGn.PORT_ID. Events on ports configured with ENUM PORT_EVENT0 wil be routed here.
0x56 | PORT_EVENT1 | Port capture event from IOC, configured by IOC:IOCFGn.PORT_ID. Events on ports configured with ENUM PORT_EVENT1 wil be routed here.
0x5F | RFC_IN_EV4 | RFC RAT event 4, configured by RFC_RAT:RATEV.OEVT4
0x60 | RFC_IN_EV5 | RFC RAT event 5, configured by RFC_RAT:RATEV.OEVT5
0x69 | AUX_AON_WU_EV | AON wakeup event, corresponds flags are here AUX_EVCTL:EVTOMCUFLAGS.AON_WU_EV
0x6A | AUX_COMPA | AUX Compare A event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA
0x6B | AUX_COMPB | AUX Compare B event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPB
0x6C | AUX_TDC_DONE | AUX TDC measurement done event, corresponds to the flag AUX_EVCTL:EVTOMCUFLAGS.TDC_DONE and the AUX_TDC status AUX_TDC:STAT.DONE
0x6D | AUX_TIMER0_EV | AUX timer 0 event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.TIMER0_EV
0x6E | AUX_TIMER1_EV | AUX timer 1 event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.TIMER1_EV
0x6F | AUX_SMPH_AUTOTAKE_DONE | Autotake event from AUX semaphore, configured by AUX_SMPH:AUTOTAKE
0x70 | AUX_ADC_DONE | AUX ADC done, corresponds to AUX_EVCTL:EVTOMCUFLAGS.ADC_DONE
0x71 | AUX_ADC_FIFO_ALMOST_FULL | AUX ADC FIFO watermark event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.ADC_FIFO_ALMOST_FULL
0x72 | AUX_OBSMUX0 | Loopback of OBSMUX0 through AUX, corresponds to AUX_EVCTL:EVTOMCUFLAGS.OBSMUX0
0x73 | AUX_ADC_IRQ | AUX ADC interrupt event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.ADC_IRQ. Status flags are found here [AUX_EVCTL:EVTOMCUFLAGS.ADC*]
0x77 | AON_RTC_UPD | RTC periodic event controlled by AON_RTC:CTL.RTC_UPD_EN
0x79 | ALWAYS_ACTIVE | Always asserted
| RW | 0x56

### TOP:EVENT:GPT1ACAPTSEL

Address offset | 0x0000 0300
Physical address | 0x4008 3300 | Instance | EVENT
Description | Output Selection for GPT1 0
Type | RW

Bits | Field Name | Description | Type | Reset
31:7 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x000 0000
6:0 | EV | Read/write selection value
Value | ENUM name | Description
0x00 | NONE | Always inactive
0x04 | AON_GPIO_EDGE | Edge detect event from IOC. Configureded by the IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET settings
0x05 | AON_SPIS_BYTE_DONE | A complete byte transfer event from the SPIS. Equivalent to the SPIS:GPFLAGS.BYTE_DONE flag
0x06 | AON_SPIS_CS | SPIS chip select event. Equivalent to the SPIS:GPFLAGS.CS flag
0x07 | AON_RTC_COMB | Event from AON_RTC controlled by the AON_RTC:CTL.COMB_EV_MASK setting
0x09 | I2C_IRQ | Interrupt event from I2C
0x0B | AUX_COMB | AUX combined event, the corresponding flag register is here AUX_EVCTL:EVTOMCUFLAGS
0x15 | FLASH | FLASH controller error event, the status flags are FLASH:FEDACSTAT.FSM_DONE and FLASH:FEDACSTAT.RVF_INT
0x19 | RFC_CMD_ACK | RFC Doorbell Command Acknowledgement Interrupt, equvialent to RFC_DBELL:RFACKIFG.ACKFLAG
0x1A | RFC_HW_COMB | Combined RCF hardware interrupt, corresponding flag is here RFC_DBELL:RFHWIFG
0x1B | RFC_CPE_0 | Combined Interrupt for CPE Generated events. Corresponding flags are here RFC_DBELL:RFCPEIFG. Only interrupts selected with CPE0 in RFC_DBELL:RFCPEIFG can trigger a RFC_CPE_0 event
0x1E | RFC_CPE_1 | Combined Interrupt for CPE Generated events. Corresponding flags are here RFC_DBELL:RFCPEIFG. Only interrupts selected with CPE1 in RFC_DBELL:RFCPEIFG can trigger a RFC_CPE_1 event
0x22 | SSI0_COMB | SSI0 combined interrupt, interrupt flags are found here SSI0:MIS
0x23 | SSI1_COMB | SSI0 combined interrupt, interrupt flags are found here SSI1:MIS
0x24 | UART0_COMB | UART0 combined interrupt, interrupt flags are found here UART0:MIS
0x3D | GPT0A_CMP | GPT0A compare event. Configured by GPT0:TAMR.TCACT
0x3E | GPT0B_CMP | GPT0B compare event. Configured by GPT0:TBMR.TCACT
0x3F | GPT1A_CMP | GPT1A compare event. Configured by GPT1:TAMR.TCACT
0x40 | GPT1B_CMP | GPT1B compare event. Configured by GPT1:TBMR.TCACT
0x41 | GPT2A_CMP | GPT2A compare event. Configured by GPT2:TAMR.TCACT
0x42 | GPT2B_CMP | GPT2B compare event. Configured by GPT2:TBMR.TCACT
0x43 | GPT3A_CMP | GPT3A compare event. Configured by GPT3:TAMR.TCACT
0x44 | GPT3B_CMP | GPT3B compare event. Configured by GPT3:TBMR.TCACT
0x57 | PORT_EVENT2 | Port capture event from IOC, configured by IOC:IOCFGn.PORT_ID. Events on ports configured with ENUM PORT_EVENT2 wil be routed here.
0x58 | PORT_EVENT3 | Port capture event from IOC, configured by IOC:IOCFGn.PORT_ID. Events on ports configured with ENUM PORT_EVENT3 wil be routed here.
0x5F | RFC_IN_EV4 | RFC RAT event 4, configured by RFC_RAT:RATEV.OEVT4
0x60 | RFC_IN_EV5 | RFC RAT event 5, configured by RFC_RAT:RATEV.OEVT5
0x69 | AUX_AON_WU_EV | AON wakeup event, corresponds flags are here AUX_EVCTL:EVTOMCUFLAGS.AON_WU_EV
0x6A | AUX_COMPA | AUX Compare A event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA
0x6B | AUX_COMPB | AUX Compare B event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPB
0x6C | AUX_TDC_DONE | AUX TDC measurement done event, corresponds to the flag AUX_EVCTL:EVTOMCUFLAGS.TDC_DONE and the AUX_TDC status AUX_TDC:STAT.DONE
0x6D | AUX_TIMER0_EV | AUX timer 0 event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.TIMER0_EV
0x6E | AUX_TIMER1_EV | AUX timer 1 event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.TIMER1_EV
0x6F | AUX_SMPH_AUTOTAKE_DONE | Autotake event from AUX semaphore, configured by AUX_SMPH:AUTOTAKE
0x70 | AUX_ADC_DONE | AUX ADC done, corresponds to AUX_EVCTL:EVTOMCUFLAGS.ADC_DONE
0x71 | AUX_ADC_FIFO_ALMOST_FULL | AUX ADC FIFO watermark event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.ADC_FIFO_ALMOST_FULL
0x72 | AUX_OBSMUX0 | Loopback of OBSMUX0 through AUX, corresponds to AUX_EVCTL:EVTOMCUFLAGS.OBSMUX0
0x73 | AUX_ADC_IRQ | AUX ADC interrupt event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.ADC_IRQ. Status flags are found here [AUX_EVCTL:EVTOMCUFLAGS.ADC*]
0x77 | AON_RTC_UPD | RTC periodic event controlled by AON_RTC:CTL.RTC_UPD_EN
0x79 | ALWAYS_ACTIVE | Always asserted
| RW | 0x57

### TOP:EVENT:GPT1BCAPTSEL

Address offset | 0x0000 0304
Physical address | 0x4008 3304 | Instance | EVENT
Description | Output Selection for GPT1 1
Type | RW

Bits | Field Name | Description | Type | Reset
31:7 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x000 0000
6:0 | EV | Read/write selection value
Value | ENUM name | Description
0x00 | NONE | Always inactive
0x04 | AON_GPIO_EDGE | Edge detect event from IOC. Configureded by the IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET settings
0x05 | AON_SPIS_BYTE_DONE | A complete byte transfer event from the SPIS. Equivalent to the SPIS:GPFLAGS.BYTE_DONE flag
0x06 | AON_SPIS_CS | SPIS chip select event. Equivalent to the SPIS:GPFLAGS.CS flag
0x07 | AON_RTC_COMB | Event from AON_RTC controlled by the AON_RTC:CTL.COMB_EV_MASK setting
0x09 | I2C_IRQ | Interrupt event from I2C
0x0B | AUX_COMB | AUX combined event, the corresponding flag register is here AUX_EVCTL:EVTOMCUFLAGS
0x15 | FLASH | FLASH controller error event, the status flags are FLASH:FEDACSTAT.FSM_DONE and FLASH:FEDACSTAT.RVF_INT
0x19 | RFC_CMD_ACK | RFC Doorbell Command Acknowledgement Interrupt, equvialent to RFC_DBELL:RFACKIFG.ACKFLAG
0x1A | RFC_HW_COMB | Combined RCF hardware interrupt, corresponding flag is here RFC_DBELL:RFHWIFG
0x1B | RFC_CPE_0 | Combined Interrupt for CPE Generated events. Corresponding flags are here RFC_DBELL:RFCPEIFG. Only interrupts selected with CPE0 in RFC_DBELL:RFCPEIFG can trigger a RFC_CPE_0 event
0x1E | RFC_CPE_1 | Combined Interrupt for CPE Generated events. Corresponding flags are here RFC_DBELL:RFCPEIFG. Only interrupts selected with CPE1 in RFC_DBELL:RFCPEIFG can trigger a RFC_CPE_1 event
0x22 | SSI0_COMB | SSI0 combined interrupt, interrupt flags are found here SSI0:MIS
0x23 | SSI1_COMB | SSI0 combined interrupt, interrupt flags are found here SSI1:MIS
0x24 | UART0_COMB | UART0 combined interrupt, interrupt flags are found here UART0:MIS
0x3D | GPT0A_CMP | GPT0A compare event. Configured by GPT0:TAMR.TCACT
0x3E | GPT0B_CMP | GPT0B compare event. Configured by GPT0:TBMR.TCACT
0x3F | GPT1A_CMP | GPT1A compare event. Configured by GPT1:TAMR.TCACT
0x40 | GPT1B_CMP | GPT1B compare event. Configured by GPT1:TBMR.TCACT
0x41 | GPT2A_CMP | GPT2A compare event. Configured by GPT2:TAMR.TCACT
0x42 | GPT2B_CMP | GPT2B compare event. Configured by GPT2:TBMR.TCACT
0x43 | GPT3A_CMP | GPT3A compare event. Configured by GPT3:TAMR.TCACT
0x44 | GPT3B_CMP | GPT3B compare event. Configured by GPT3:TBMR.TCACT
0x57 | PORT_EVENT2 | Port capture event from IOC, configured by IOC:IOCFGn.PORT_ID. Events on ports configured with ENUM PORT_EVENT2 wil be routed here.
0x58 | PORT_EVENT3 | Port capture event from IOC, configured by IOC:IOCFGn.PORT_ID. Events on ports configured with ENUM PORT_EVENT3 wil be routed here.
0x5F | RFC_IN_EV4 | RFC RAT event 4, configured by RFC_RAT:RATEV.OEVT4
0x60 | RFC_IN_EV5 | RFC RAT event 5, configured by RFC_RAT:RATEV.OEVT5
0x69 | AUX_AON_WU_EV | AON wakeup event, corresponds flags are here AUX_EVCTL:EVTOMCUFLAGS.AON_WU_EV
0x6A | AUX_COMPA | AUX Compare A event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA
0x6B | AUX_COMPB | AUX Compare B event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPB
0x6C | AUX_TDC_DONE | AUX TDC measurement done event, corresponds to the flag AUX_EVCTL:EVTOMCUFLAGS.TDC_DONE and the AUX_TDC status AUX_TDC:STAT.DONE
0x6D | AUX_TIMER0_EV | AUX timer 0 event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.TIMER0_EV
0x6E | AUX_TIMER1_EV | AUX timer 1 event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.TIMER1_EV
0x6F | AUX_SMPH_AUTOTAKE_DONE | Autotake event from AUX semaphore, configured by AUX_SMPH:AUTOTAKE
0x70 | AUX_ADC_DONE | AUX ADC done, corresponds to AUX_EVCTL:EVTOMCUFLAGS.ADC_DONE
0x71 | AUX_ADC_FIFO_ALMOST_FULL | AUX ADC FIFO watermark event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.ADC_FIFO_ALMOST_FULL
0x72 | AUX_OBSMUX0 | Loopback of OBSMUX0 through AUX, corresponds to AUX_EVCTL:EVTOMCUFLAGS.OBSMUX0
0x73 | AUX_ADC_IRQ | AUX ADC interrupt event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.ADC_IRQ. Status flags are found here [AUX_EVCTL:EVTOMCUFLAGS.ADC*]
0x77 | AON_RTC_UPD | RTC periodic event controlled by AON_RTC:CTL.RTC_UPD_EN
0x79 | ALWAYS_ACTIVE | Always asserted
| RW | 0x58

### TOP:EVENT:GPT2ACAPTSEL

Address offset | 0x0000 0400
Physical address | 0x4008 3400 | Instance | EVENT
Description | Output Selection for GPT2 0
Type | RW

Bits | Field Name | Description | Type | Reset
31:7 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x000 0000
6:0 | EV | Read/write selection value
Value | ENUM name | Description
0x00 | NONE | Always inactive
0x04 | AON_GPIO_EDGE | Edge detect event from IOC. Configureded by the IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET settings
0x05 | AON_SPIS_BYTE_DONE | A complete byte transfer event from the SPIS. Equivalent to the SPIS:GPFLAGS.BYTE_DONE flag
0x06 | AON_SPIS_CS | SPIS chip select event. Equivalent to the SPIS:GPFLAGS.CS flag
0x07 | AON_RTC_COMB | Event from AON_RTC controlled by the AON_RTC:CTL.COMB_EV_MASK setting
0x09 | I2C_IRQ | Interrupt event from I2C
0x0B | AUX_COMB | AUX combined event, the corresponding flag register is here AUX_EVCTL:EVTOMCUFLAGS
0x15 | FLASH | FLASH controller error event, the status flags are FLASH:FEDACSTAT.FSM_DONE and FLASH:FEDACSTAT.RVF_INT
0x19 | RFC_CMD_ACK | RFC Doorbell Command Acknowledgement Interrupt, equvialent to RFC_DBELL:RFACKIFG.ACKFLAG
0x1A | RFC_HW_COMB | Combined RCF hardware interrupt, corresponding flag is here RFC_DBELL:RFHWIFG
0x1B | RFC_CPE_0 | Combined Interrupt for CPE Generated events. Corresponding flags are here RFC_DBELL:RFCPEIFG. Only interrupts selected with CPE0 in RFC_DBELL:RFCPEIFG can trigger a RFC_CPE_0 event
0x1E | RFC_CPE_1 | Combined Interrupt for CPE Generated events. Corresponding flags are here RFC_DBELL:RFCPEIFG. Only interrupts selected with CPE1 in RFC_DBELL:RFCPEIFG can trigger a RFC_CPE_1 event
0x22 | SSI0_COMB | SSI0 combined interrupt, interrupt flags are found here SSI0:MIS
0x23 | SSI1_COMB | SSI0 combined interrupt, interrupt flags are found here SSI1:MIS
0x24 | UART0_COMB | UART0 combined interrupt, interrupt flags are found here UART0:MIS
0x3D | GPT0A_CMP | GPT0A compare event. Configured by GPT0:TAMR.TCACT
0x3E | GPT0B_CMP | GPT0B compare event. Configured by GPT0:TBMR.TCACT
0x3F | GPT1A_CMP | GPT1A compare event. Configured by GPT1:TAMR.TCACT
0x40 | GPT1B_CMP | GPT1B compare event. Configured by GPT1:TBMR.TCACT
0x41 | GPT2A_CMP | GPT2A compare event. Configured by GPT2:TAMR.TCACT
0x42 | GPT2B_CMP | GPT2B compare event. Configured by GPT2:TBMR.TCACT
0x43 | GPT3A_CMP | GPT3A compare event. Configured by GPT3:TAMR.TCACT
0x44 | GPT3B_CMP | GPT3B compare event. Configured by GPT3:TBMR.TCACT
0x59 | PORT_EVENT4 | Port capture event from IOC, configured by IOC:IOCFGn.PORT_ID. Events on ports configured with ENUM PORT_EVENT4 wil be routed here.
0x5A | PORT_EVENT5 | Port capture event from IOC, configured by IOC:IOCFGn.PORT_ID. Events on ports configured with ENUM PORT_EVENT4 wil be routed here.
0x61 | RFC_IN_EV6 | RFC RAT event 6, configured by RFC_RAT:RATEV.OEVT6
0x62 | RFC_IN_EV7 | RFC RAT event 7, configured by RFC_RAT:RATEV.OEVT7
0x69 | AUX_AON_WU_EV | AON wakeup event, corresponds flags are here AUX_EVCTL:EVTOMCUFLAGS.AON_WU_EV
0x6A | AUX_COMPA | AUX Compare A event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA
0x6B | AUX_COMPB | AUX Compare B event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPB
0x6C | AUX_TDC_DONE | AUX TDC measurement done event, corresponds to the flag AUX_EVCTL:EVTOMCUFLAGS.TDC_DONE and the AUX_TDC status AUX_TDC:STAT.DONE
0x6D | AUX_TIMER0_EV | AUX timer 0 event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.TIMER0_EV
0x6E | AUX_TIMER1_EV | AUX timer 1 event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.TIMER1_EV
0x6F | AUX_SMPH_AUTOTAKE_DONE | Autotake event from AUX semaphore, configured by AUX_SMPH:AUTOTAKE
0x70 | AUX_ADC_DONE | AUX ADC done, corresponds to AUX_EVCTL:EVTOMCUFLAGS.ADC_DONE
0x71 | AUX_ADC_FIFO_ALMOST_FULL | AUX ADC FIFO watermark event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.ADC_FIFO_ALMOST_FULL
0x72 | AUX_OBSMUX0 | Loopback of OBSMUX0 through AUX, corresponds to AUX_EVCTL:EVTOMCUFLAGS.OBSMUX0
0x73 | AUX_ADC_IRQ | AUX ADC interrupt event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.ADC_IRQ. Status flags are found here [AUX_EVCTL:EVTOMCUFLAGS.ADC*]
0x77 | AON_RTC_UPD | RTC periodic event controlled by AON_RTC:CTL.RTC_UPD_EN
0x79 | ALWAYS_ACTIVE | Always asserted
| RW | 0x59

### TOP:EVENT:GPT2BCAPTSEL

Address offset | 0x0000 0404
Physical address | 0x4008 3404 | Instance | EVENT
Description | Output Selection for GPT2 1
Type | RW

Bits | Field Name | Description | Type | Reset
31:7 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x000 0000
6:0 | EV | Read/write selection value
Value | ENUM name | Description
0x00 | NONE | Always inactive
0x04 | AON_GPIO_EDGE | Edge detect event from IOC. Configureded by the IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET settings
0x05 | AON_SPIS_BYTE_DONE | A complete byte transfer event from the SPIS. Equivalent to the SPIS:GPFLAGS.BYTE_DONE flag
0x06 | AON_SPIS_CS | SPIS chip select event. Equivalent to the SPIS:GPFLAGS.CS flag
0x07 | AON_RTC_COMB | Event from AON_RTC controlled by the AON_RTC:CTL.COMB_EV_MASK setting
0x09 | I2C_IRQ | Interrupt event from I2C
0x0B | AUX_COMB | AUX combined event, the corresponding flag register is here AUX_EVCTL:EVTOMCUFLAGS
0x15 | FLASH | FLASH controller error event, the status flags are FLASH:FEDACSTAT.FSM_DONE and FLASH:FEDACSTAT.RVF_INT
0x19 | RFC_CMD_ACK | RFC Doorbell Command Acknowledgement Interrupt, equvialent to RFC_DBELL:RFACKIFG.ACKFLAG
0x1A | RFC_HW_COMB | Combined RCF hardware interrupt, corresponding flag is here RFC_DBELL:RFHWIFG
0x1B | RFC_CPE_0 | Combined Interrupt for CPE Generated events. Corresponding flags are here RFC_DBELL:RFCPEIFG. Only interrupts selected with CPE0 in RFC_DBELL:RFCPEIFG can trigger a RFC_CPE_0 event
0x1E | RFC_CPE_1 | Combined Interrupt for CPE Generated events. Corresponding flags are here RFC_DBELL:RFCPEIFG. Only interrupts selected with CPE1 in RFC_DBELL:RFCPEIFG can trigger a RFC_CPE_1 event
0x22 | SSI0_COMB | SSI0 combined interrupt, interrupt flags are found here SSI0:MIS
0x23 | SSI1_COMB | SSI0 combined interrupt, interrupt flags are found here SSI1:MIS
0x24 | UART0_COMB | UART0 combined interrupt, interrupt flags are found here UART0:MIS
0x3D | GPT0A_CMP | GPT0A compare event. Configured by GPT0:TAMR.TCACT
0x3E | GPT0B_CMP | GPT0B compare event. Configured by GPT0:TBMR.TCACT
0x3F | GPT1A_CMP | GPT1A compare event. Configured by GPT1:TAMR.TCACT
0x40 | GPT1B_CMP | GPT1B compare event. Configured by GPT1:TBMR.TCACT
0x41 | GPT2A_CMP | GPT2A compare event. Configured by GPT2:TAMR.TCACT
0x42 | GPT2B_CMP | GPT2B compare event. Configured by GPT2:TBMR.TCACT
0x43 | GPT3A_CMP | GPT3A compare event. Configured by GPT3:TAMR.TCACT
0x44 | GPT3B_CMP | GPT3B compare event. Configured by GPT3:TBMR.TCACT
0x59 | PORT_EVENT4 | Port capture event from IOC, configured by IOC:IOCFGn.PORT_ID. Events on ports configured with ENUM PORT_EVENT4 wil be routed here.
0x5A | PORT_EVENT5 | Port capture event from IOC, configured by IOC:IOCFGn.PORT_ID. Events on ports configured with ENUM PORT_EVENT4 wil be routed here.
0x61 | RFC_IN_EV6 | RFC RAT event 6, configured by RFC_RAT:RATEV.OEVT6
0x62 | RFC_IN_EV7 | RFC RAT event 7, configured by RFC_RAT:RATEV.OEVT7
0x69 | AUX_AON_WU_EV | AON wakeup event, corresponds flags are here AUX_EVCTL:EVTOMCUFLAGS.AON_WU_EV
0x6A | AUX_COMPA | AUX Compare A event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA
0x6B | AUX_COMPB | AUX Compare B event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPB
0x6C | AUX_TDC_DONE | AUX TDC measurement done event, corresponds to the flag AUX_EVCTL:EVTOMCUFLAGS.TDC_DONE and the AUX_TDC status AUX_TDC:STAT.DONE
0x6D | AUX_TIMER0_EV | AUX timer 0 event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.TIMER0_EV
0x6E | AUX_TIMER1_EV | AUX timer 1 event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.TIMER1_EV
0x6F | AUX_SMPH_AUTOTAKE_DONE | Autotake event from AUX semaphore, configured by AUX_SMPH:AUTOTAKE
0x70 | AUX_ADC_DONE | AUX ADC done, corresponds to AUX_EVCTL:EVTOMCUFLAGS.ADC_DONE
0x71 | AUX_ADC_FIFO_ALMOST_FULL | AUX ADC FIFO watermark event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.ADC_FIFO_ALMOST_FULL
0x72 | AUX_OBSMUX0 | Loopback of OBSMUX0 through AUX, corresponds to AUX_EVCTL:EVTOMCUFLAGS.OBSMUX0
0x73 | AUX_ADC_IRQ | AUX ADC interrupt event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.ADC_IRQ. Status flags are found here [AUX_EVCTL:EVTOMCUFLAGS.ADC*]
0x77 | AON_RTC_UPD | RTC periodic event controlled by AON_RTC:CTL.RTC_UPD_EN
0x79 | ALWAYS_ACTIVE | Always asserted
| RW | 0x5A

### TOP:EVENT:UDMACH1SSEL

Address offset | 0x0000 0508
Physical address | 0x4008 3508 | Instance | EVENT
Description | Output Selection for DMA Channel 1 SREQ
Type | RO

Bits | Field Name | Description | Type | Reset
31:7 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x000 0000
6:0 | EV | Read only selection value
Value | ENUM name | Description
0x31 | UART0_RX_DMASREQ | UART0 RX DMA single request, controlled by UART0:DMACTL.RXDMAE
| RO | 0x31

### TOP:EVENT:UDMACH1BSEL

Address offset | 0x0000 050C
Physical address | 0x4008 350C | Instance | EVENT
Description | Output Selection for DMA Channel 1 REQ
Type | RO

Bits | Field Name | Description | Type | Reset
31:7 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x000 0000
6:0 | EV | Read only selection value
Value | ENUM name | Description
0x30 | UART0_RX_DMABREQ | UART0 RX DMA burst request, controlled by UART0:DMACTL.RXDMAE
| RO | 0x30

### TOP:EVENT:UDMACH2SSEL

Address offset | 0x0000 0510
Physical address | 0x4008 3510 | Instance | EVENT
Description | Output Selection for DMA Channel 2 SREQ
Type | RO

Bits | Field Name | Description | Type | Reset
31:7 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x000 0000
6:0 | EV | Read only selection value
Value | ENUM name | Description
0x33 | UART0_TX_DMASREQ | UART0 TX DMA single request, controlled by UART0:DMACTL.TXDMAE
| RO | 0x33

### TOP:EVENT:UDMACH2BSEL

Address offset | 0x0000 0514
Physical address | 0x4008 3514 | Instance | EVENT
Description | Output Selection for DMA Channel 2 REQ
Type | RO

Bits | Field Name | Description | Type | Reset
31:7 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x000 0000
6:0 | EV | Read only selection value
Value | ENUM name | Description
0x32 | UART0_TX_DMABREQ | UART0 TX DMA burst request, controlled by UART0:DMACTL.TXDMAE
| RO | 0x32

### TOP:EVENT:UDMACH3SSEL

Address offset | 0x0000 0518
Physical address | 0x4008 3518 | Instance | EVENT
Description | Output Selection for DMA Channel 3 SREQ
Type | RO

Bits | Field Name | Description | Type | Reset
31:7 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x000 0000
6:0 | EV | Read only selection value
Value | ENUM name | Description
0x29 | SSI0_RX_DMASREQ | SSI0 RX DMA single request, controlled by SSI0:DMACR.RXDMAE
| RO | 0x29

### TOP:EVENT:UDMACH3BSEL

Address offset | 0x0000 051C
Physical address | 0x4008 351C | Instance | EVENT
Description | Output Selection for DMA Channel 3 REQ
Type | RO

Bits | Field Name | Description | Type | Reset
31:7 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x000 0000
6:0 | EV | Read only selection value
Value | ENUM name | Description
0x28 | SSI0_RX_DMABREQ | SSI0 RX DMA burst request , controlled by SSI0:DMACR.RXDMAE
| RO | 0x28

### TOP:EVENT:UDMACH4SSEL

Address offset | 0x0000 0520
Physical address | 0x4008 3520 | Instance | EVENT
Description | Output Selection for DMA Channel 4 SREQ
Type | RO

Bits | Field Name | Description | Type | Reset
31:7 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x000 0000
6:0 | EV | Read only selection value
Value | ENUM name | Description
0x2B | SSI0_TX_DMASREQ | SSI0 TX DMA single request, controlled by SSI0:DMACR.TXDMAE
| RO | 0x2B

### TOP:EVENT:UDMACH4BSEL

Address offset | 0x0000 0524
Physical address | 0x4008 3524 | Instance | EVENT
Description | Output Selection for DMA Channel 4 REQ
Type | RO

Bits | Field Name | Description | Type | Reset
31:7 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x000 0000
6:0 | EV | Read only selection value
Value | ENUM name | Description
0x2A | SSI0_TX_DMABREQ | SSI0 TX DMA burst request , controlled by SSI0:DMACR.TXDMAE
| RO | 0x2A

### TOP:EVENT:UDMACH5SSEL

Address offset | 0x0000 0528
Physical address | 0x4008 3528 | Instance | EVENT
Description | Output Selection for DMA Channel 5 SREQ
Type | RO

Bits | Field Name | Description | Type | Reset
31:7 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x000 0000
6:0 | EV | Read only selection value
Value | ENUM name | Description
0x3A | SPIS_RXF_DMASREQ | SPIS RX FIFO DMA single request, controlled by SPIS:CFG.TR_DMA_REQ_TYPE
| RO | 0x3A

### TOP:EVENT:UDMACH5BSEL

Address offset | 0x0000 052C
Physical address | 0x4008 352C | Instance | EVENT
Description | Output Selection for DMA Channel 5 REQ
Type | RO

Bits | Field Name | Description | Type | Reset
31:7 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x000 0000
6:0 | EV | Read only selection value
Value | ENUM name | Description
0x39 | SPIS_RXF_DMABREQ | SPIS RX FIFO DMA burst request, controlled by SPIS:CFG.TR_DMA_REQ_TYPE
| RO | 0x39

### TOP:EVENT:UDMACH6SSEL

Address offset | 0x0000 0530
Physical address | 0x4008 3530 | Instance | EVENT
Description | Output Selection for DMA Channel 6 SREQ
Type | RO

Bits | Field Name | Description | Type | Reset
31:7 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x000 0000
6:0 | EV | Read only selection value
Value | ENUM name | Description
0x3C | SPIS_TXF_DMASREQ | SPIS TX FIFO DMA single request, controlled by SPIS:CFG.TX_DMA_REQ_TYPE
| RO | 0x3C

### TOP:EVENT:UDMACH6BSEL

Address offset | 0x0000 0534
Physical address | 0x4008 3534 | Instance | EVENT
Description | Output Selection for DMA Channel 6 REQ
Type | RO

Bits | Field Name | Description | Type | Reset
31:7 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x000 0000
6:0 | EV | Read only selection value
Value | ENUM name | Description
0x3B | SPIS_TXF_DMABREQ | SPIS TX FIFO DMA burst request, controlled by SPIS:CFG.TX_DMA_REQ_TYPE
| RO | 0x3B

### TOP:EVENT:UDMACH7SSEL

Address offset | 0x0000 0538
Physical address | 0x4008 3538 | Instance | EVENT
Description | Output Selection for DMA Channel 7 SREQ
Type | RO

Bits | Field Name | Description | Type | Reset
31:7 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x000 0000
6:0 | EV | Read only selection value
Value | ENUM name | Description
0x75 | AUX_DMASREQ | DMA single request event from AUX, configured by AUX_EVCTL:DMACTL
| RO | 0x75

### TOP:EVENT:UDMACH7BSEL

Address offset | 0x0000 053C
Physical address | 0x4008 353C | Instance | EVENT
Description | Output Selection for DMA Channel 7 REQ
Type | RO

Bits | Field Name | Description | Type | Reset
31:7 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x000 0000
6:0 | EV | Read only selection value
Value | ENUM name | Description
0x76 | AUX_DMABREQ | DMA burst request event from AUX, configured by AUX_EVCTL:DMACTL
| RO | 0x76

### TOP:EVENT:UDMACH8SSEL

Address offset | 0x0000 0540
Physical address | 0x4008 3540 | Instance | EVENT
Description | Output Selection for DMA Channel 8 SREQ Single request is ignored for this channel
Type | RO

Bits | Field Name | Description | Type | Reset
31:7 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x000 0000
6:0 | EV | Read only selection value
Value | ENUM name | Description
0x74 | AUX_SW_DMABREQ | AUX observation loopback
| RO | 0x74

### TOP:EVENT:UDMACH8BSEL

Address offset | 0x0000 0544
Physical address | 0x4008 3544 | Instance | EVENT
Description | Output Selection for DMA Channel 8 REQ
Type | RO

Bits | Field Name | Description | Type | Reset
31:7 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x000 0000
6:0 | EV | Read only selection value
Value | ENUM name | Description
0x74 | AUX_SW_DMABREQ | AUX observation loopback
| RO | 0x74

### TOP:EVENT:UDMACH9SSEL

Address offset | 0x0000 0548
Physical address | 0x4008 3548 | Instance | EVENT
Description | Output Selection for DMA Channel 9 SREQ DMA_DONE for the corresponding DMA channel is available as interrupt on GPT0 as GPT0:RIS.DMAARIS
Type | RW

Bits | Field Name | Description | Type | Reset
31:7 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x000 0000
6:0 | EV | Read/write selection value
Value | ENUM name | Description
0x45 | NONE | Always inactive
0x4D | GPT0A_DMABREQ | GPT0A DMA trigger event. Configured by GPT0:DMAEV
0x4E | GPT0B_DMABREQ | GPT0B DMA trigger event. Configured by GPT0:DMAEV
0x4F | GPT1A_DMABREQ | GPT1A DMA trigger event. Configured by GPT1:DMAEV
0x50 | GPT1B_DMABREQ | GPT1B DMA trigger event. Configured by GPT1:DMAEV
0x51 | GPT2A_DMABREQ | GPT2A DMA trigger event. Configured by GPT2:DMAEV
0x52 | GPT2B_DMABREQ | GPT2B DMA trigger event. Configured by GPT2:DMAEV
0x53 | GPT3A_DMABREQ | GPT3A DMA trigger event. Configured by GPT3:DMAEV
0x54 | GPT3B_DMABREQ | GPT3B DMA trigger event. Configured by GPT3:DMAEV
| RW | 0x45

### TOP:EVENT:UDMACH9BSEL

Address offset | 0x0000 054C
Physical address | 0x4008 354C | Instance | EVENT
Description | Output Selection for DMA Channel 9 REQ DMA_DONE for the corresponding DMA channel is available as interrupt on GPT0 as GPT0:RIS.DMAARIS
Type | RW

Bits | Field Name | Description | Type | Reset
31:7 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x000 0000
6:0 | EV | Read/write selection value
Value | ENUM name | Description
0x45 | NONE | Always inactive
0x4D | GPT0A_DMABREQ | GPT0A DMA trigger event. Configured by GPT0:DMAEV
0x4E | GPT0B_DMABREQ | GPT0B DMA trigger event. Configured by GPT0:DMAEV
0x4F | GPT1A_DMABREQ | GPT1A DMA trigger event. Configured by GPT1:DMAEV
0x50 | GPT1B_DMABREQ | GPT1B DMA trigger event. Configured by GPT1:DMAEV
0x51 | GPT2A_DMABREQ | GPT2A DMA trigger event. Configured by GPT2:DMAEV
0x52 | GPT2B_DMABREQ | GPT2B DMA trigger event. Configured by GPT2:DMAEV
0x53 | GPT3A_DMABREQ | GPT3A DMA trigger event. Configured by GPT3:DMAEV
0x54 | GPT3B_DMABREQ | GPT3B DMA trigger event. Configured by GPT3:DMAEV
| RW | 0x4D

### TOP:EVENT:UDMACH10SSEL

Address offset | 0x0000 0550
Physical address | 0x4008 3550 | Instance | EVENT
Description | Output Selection for DMA Channel 10 SREQ DMA_DONE for the corresponding DMA channel is available as interrupt on GPT0 as GPT0:RIS.DMABRIS
Type | RW

Bits | Field Name | Description | Type | Reset
31:7 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x000 0000
6:0 | EV | Read/write selection value
Value | ENUM name | Description
0x45 | NONE | Always inactive
0x4D | GPT0A_DMABREQ | GPT0A DMA trigger event. Configured by GPT0:DMAEV
0x4E | GPT0B_DMABREQ | GPT0B DMA trigger event. Configured by GPT0:DMAEV
0x4F | GPT1A_DMABREQ | GPT1A DMA trigger event. Configured by GPT1:DMAEV
0x50 | GPT1B_DMABREQ | GPT1B DMA trigger event. Configured by GPT1:DMAEV
0x51 | GPT2A_DMABREQ | GPT2A DMA trigger event. Configured by GPT2:DMAEV
0x52 | GPT2B_DMABREQ | GPT2B DMA trigger event. Configured by GPT2:DMAEV
0x53 | GPT3A_DMABREQ | GPT3A DMA trigger event. Configured by GPT3:DMAEV
0x54 | GPT3B_DMABREQ | GPT3B DMA trigger event. Configured by GPT3:DMAEV
| RW | 0x46

### TOP:EVENT:UDMACH10BSEL

Address offset | 0x0000 0554
Physical address | 0x4008 3554 | Instance | EVENT
Description | Output Selection for DMA Channel 10 REQ DMA_DONE for the corresponding DMA channel is available as interrupt on GPT0 as GPT0:RIS.DMABRIS
Type | RW

Bits | Field Name | Description | Type | Reset
31:7 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x000 0000
6:0 | EV | Read/write selection value
Value | ENUM name | Description
0x45 | NONE | Always inactive
0x4D | GPT0A_DMABREQ | GPT0A DMA trigger event. Configured by GPT0:DMAEV
0x4E | GPT0B_DMABREQ | GPT0B DMA trigger event. Configured by GPT0:DMAEV
0x4F | GPT1A_DMABREQ | GPT1A DMA trigger event. Configured by GPT1:DMAEV
0x50 | GPT1B_DMABREQ | GPT1B DMA trigger event. Configured by GPT1:DMAEV
0x51 | GPT2A_DMABREQ | GPT2A DMA trigger event. Configured by GPT2:DMAEV
0x52 | GPT2B_DMABREQ | GPT2B DMA trigger event. Configured by GPT2:DMAEV
0x53 | GPT3A_DMABREQ | GPT3A DMA trigger event. Configured by GPT3:DMAEV
0x54 | GPT3B_DMABREQ | GPT3B DMA trigger event. Configured by GPT3:DMAEV
| RW | 0x4E

### TOP:EVENT:UDMACH11SSEL

Address offset | 0x0000 0558
Physical address | 0x4008 3558 | Instance | EVENT
Description | Output Selection for DMA Channel 11 SREQ DMA_DONE for the corresponding DMA channel is available as interrupt on GPT1 as GPT1:RIS.DMAARIS
Type | RW

Bits | Field Name | Description | Type | Reset
31:7 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x000 0000
6:0 | EV | Read/write selection value
Value | ENUM name | Description
0x45 | NONE | Always inactive
0x4D | GPT0A_DMABREQ | GPT0A DMA trigger event. Configured by GPT0:DMAEV
0x4E | GPT0B_DMABREQ | GPT0B DMA trigger event. Configured by GPT0:DMAEV
0x4F | GPT1A_DMABREQ | GPT1A DMA trigger event. Configured by GPT1:DMAEV
0x50 | GPT1B_DMABREQ | GPT1B DMA trigger event. Configured by GPT1:DMAEV
0x51 | GPT2A_DMABREQ | GPT2A DMA trigger event. Configured by GPT2:DMAEV
0x52 | GPT2B_DMABREQ | GPT2B DMA trigger event. Configured by GPT2:DMAEV
0x53 | GPT3A_DMABREQ | GPT3A DMA trigger event. Configured by GPT3:DMAEV
0x54 | GPT3B_DMABREQ | GPT3B DMA trigger event. Configured by GPT3:DMAEV
| RW | 0x47

### TOP:EVENT:UDMACH11BSEL

Address offset | 0x0000 055C
Physical address | 0x4008 355C | Instance | EVENT
Description | Output Selection for DMA Channel 11 REQ DMA_DONE for the corresponding DMA channel is available as interrupt on GPT1 as GPT1:RIS.DMAARIS
Type | RW

Bits | Field Name | Description | Type | Reset
31:7 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x000 0000
6:0 | EV | Read/write selection value
Value | ENUM name | Description
0x45 | NONE | Always inactive
0x4D | GPT0A_DMABREQ | GPT0A DMA trigger event. Configured by GPT0:DMAEV
0x4E | GPT0B_DMABREQ | GPT0B DMA trigger event. Configured by GPT0:DMAEV
0x4F | GPT1A_DMABREQ | GPT1A DMA trigger event. Configured by GPT1:DMAEV
0x50 | GPT1B_DMABREQ | GPT1B DMA trigger event. Configured by GPT1:DMAEV
0x51 | GPT2A_DMABREQ | GPT2A DMA trigger event. Configured by GPT2:DMAEV
0x52 | GPT2B_DMABREQ | GPT2B DMA trigger event. Configured by GPT2:DMAEV
0x53 | GPT3A_DMABREQ | GPT3A DMA trigger event. Configured by GPT3:DMAEV
0x54 | GPT3B_DMABREQ | GPT3B DMA trigger event. Configured by GPT3:DMAEV
| RW | 0x4F

### TOP:EVENT:UDMACH12SSEL

Address offset | 0x0000 0560
Physical address | 0x4008 3560 | Instance | EVENT
Description | Output Selection for DMA Channel 12 SREQ DMA_DONE for the corresponding DMA channel is available as interrupt on GPT1 as GPT1:RIS.DMABRIS
Type | RW

Bits | Field Name | Description | Type | Reset
31:7 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x000 0000
6:0 | EV | Read/write selection value
Value | ENUM name | Description
0x45 | NONE | Always inactive
0x4D | GPT0A_DMABREQ | GPT0A DMA trigger event. Configured by GPT0:DMAEV
0x4E | GPT0B_DMABREQ | GPT0B DMA trigger event. Configured by GPT0:DMAEV
0x4F | GPT1A_DMABREQ | GPT1A DMA trigger event. Configured by GPT1:DMAEV
0x50 | GPT1B_DMABREQ | GPT1B DMA trigger event. Configured by GPT1:DMAEV
0x51 | GPT2A_DMABREQ | GPT2A DMA trigger event. Configured by GPT2:DMAEV
0x52 | GPT2B_DMABREQ | GPT2B DMA trigger event. Configured by GPT2:DMAEV
0x53 | GPT3A_DMABREQ | GPT3A DMA trigger event. Configured by GPT3:DMAEV
0x54 | GPT3B_DMABREQ | GPT3B DMA trigger event. Configured by GPT3:DMAEV
| RW | 0x48

### TOP:EVENT:UDMACH12BSEL

Address offset | 0x0000 0564
Physical address | 0x4008 3564 | Instance | EVENT
Description | Output Selection for DMA Channel 12 REQ DMA_DONE for the corresponding DMA channel is available as interrupt on GPT1 as GPT1:RIS.DMABRIS
Type | RW

Bits | Field Name | Description | Type | Reset
31:7 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x000 0000
6:0 | EV | Read/write selection value
Value | ENUM name | Description
0x45 | NONE | Always inactive
0x4D | GPT0A_DMABREQ | GPT0A DMA trigger event. Configured by GPT0:DMAEV
0x4E | GPT0B_DMABREQ | GPT0B DMA trigger event. Configured by GPT0:DMAEV
0x4F | GPT1A_DMABREQ | GPT1A DMA trigger event. Configured by GPT1:DMAEV
0x50 | GPT1B_DMABREQ | GPT1B DMA trigger event. Configured by GPT1:DMAEV
0x51 | GPT2A_DMABREQ | GPT2A DMA trigger event. Configured by GPT2:DMAEV
0x52 | GPT2B_DMABREQ | GPT2B DMA trigger event. Configured by GPT2:DMAEV
0x53 | GPT3A_DMABREQ | GPT3A DMA trigger event. Configured by GPT3:DMAEV
0x54 | GPT3B_DMABREQ | GPT3B DMA trigger event. Configured by GPT3:DMAEV
| RW | 0x50

### TOP:EVENT:UDMACH13BSEL

Address offset | 0x0000 056C
Physical address | 0x4008 356C | Instance | EVENT
Description | Output Selection for DMA Channel 13 REQ
Type | RO

Bits | Field Name | Description | Type | Reset
31:7 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x000 0000
6:0 | EV | Read only selection value
Value | ENUM name | Description
0x03 | AON_PROG2 | Event selected by AON_EVENT MCU event selector, AON_EVENT:EVTOMCUSEL.AON_PROG2_EV
| RO | 0x03

### TOP:EVENT:UDMACH14BSEL

Address offset | 0x0000 0574
Physical address | 0x4008 3574 | Instance | EVENT
Description | Output Selection for DMA Channel 14 REQ
Type | RW

Bits | Field Name | Description | Type | Reset
31:7 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x000 0000
6:0 | EV | Read/write selection value
Value | ENUM name | Description
0x00 | NONE | Always inactive
0x01 | AON_PROG0 | Event selected by AON_EVENT MCU event selector, AON_EVENT:EVTOMCUSEL.AON_PROG0_EV
0x02 | AON_PROG1 | Event selected by AON_EVENT MCU event selector, AON_EVENT:EVTOMCUSEL.AON_PROG1_EV
0x03 | AON_PROG2 | Event selected by AON_EVENT MCU event selector, AON_EVENT:EVTOMCUSEL.AON_PROG2_EV
0x04 | AON_GPIO_EDGE | Edge detect event from IOC. Configureded by the IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET settings
0x05 | AON_SPIS_BYTE_DONE | A complete byte transfer event from the SPIS. Equivalent to the SPIS:GPFLAGS.BYTE_DONE flag
0x06 | AON_SPIS_CS | SPIS chip select event. Equivalent to the SPIS:GPFLAGS.CS flag
0x07 | AON_RTC_COMB | Event from AON_RTC controlled by the AON_RTC:CTL.COMB_EV_MASK setting
0x08 | I2S_IRQ | Interrupt event from I2S
0x09 | I2C_IRQ | Interrupt event from I2C
0x0A | AON_AUX_SWEV0 | AUX Software event 0, AUX_EVCTL:SWEVSET.SWEV0
0x0B | AUX_COMB | AUX combined event, the corresponding flag register is here AUX_EVCTL:EVTOMCUFLAGS
0x0C | GPT2A | GPT2A interrupt event, controlled by GPT2:TAMR
0x0D | GPT2B | GPT2B interrupt event, controlled by GPT2:TBMR
0x0E | GPT3A | GPT3A interrupt event, controlled by GPT3:TAMR
0x0F | GPT3B | GPT3B interrupt event, controlled by GPT3:TBMR
0x10 | GPT0A | GPT0A interrupt event, controlled by GPT0:TAMR
0x11 | GPT0B | GPT0B interrupt event, controlled by GPT0:TBMR
0x12 | GPT1A | GPT1A interrupt event, controlled by GPT1:TAMR
0x13 | GPT1B | GPT1B interrupt event, controlled by GPT1:TBMR
0x14 | DMA_CH0_DONE | DMA done for software tiggered UDMA channel 0, see UDMA0:SOFTREQ
0x15 | FLASH | FLASH controller error event, the status flags are FLASH:FEDACSTAT.FSM_DONE and FLASH:FEDACSTAT.RVF_INT
0x16 | DMA_CH18_DONE | DMA done for software tiggered UDMA channel 18, see UDMA0:SOFTREQ
0x18 | WDT_IRQ | Watchdog interrupt event, controlled by WDT:CTL.INTEN
0x19 | RFC_CMD_ACK | RFC Doorbell Command Acknowledgement Interrupt, equvialent to RFC_DBELL:RFACKIFG.ACKFLAG
0x1A | RFC_HW_COMB | Combined RCF hardware interrupt, corresponding flag is here RFC_DBELL:RFHWIFG
0x1B | RFC_CPE_0 | Combined Interrupt for CPE Generated events. Corresponding flags are here RFC_DBELL:RFCPEIFG. Only interrupts selected with CPE0 in RFC_DBELL:RFCPEIFG can trigger a RFC_CPE_0 event
0x1D | AUX_SWEV1 | AUX software event 1, triggered by AUX_EVCTL:SWEVSET.SWEV1, also available as AUX_EVENT2 AON wake up event. MCU domain wakeup control AON_EVENT:MCUWUSEL AUX domain wakeup control AON_EVENT:AUXWUSEL
0x1E | RFC_CPE_1 | Combined Interrupt for CPE Generated events. Corresponding flags are here RFC_DBELL:RFCPEIFG. Only interrupts selected with CPE1 in RFC_DBELL:RFCPEIFG can trigger a RFC_CPE_1 event
0x22 | SSI0_COMB | SSI0 combined interrupt, interrupt flags are found here SSI0:MIS
0x23 | SSI1_COMB | SSI0 combined interrupt, interrupt flags are found here SSI1:MIS
0x24 | UART0_COMB | UART0 combined interrupt, interrupt flags are found here UART0:MIS
0x26 | DMA_ERR | DMA bus error, corresponds to UDMA0:ERROR.STATUS
0x27 | DMA_DONE_COMB | Combined DMA done corresponding flags are here UDMA0:REQDONE
0x28 | SSI0_RX_DMABREQ | SSI0 RX DMA burst request , controlled by SSI0:DMACR.RXDMAE
0x29 | SSI0_RX_DMASREQ | SSI0 RX DMA single request, controlled by SSI0:DMACR.RXDMAE
0x2A | SSI0_TX_DMABREQ | SSI0 TX DMA burst request , controlled by SSI0:DMACR.TXDMAE
0x2B | SSI0_TX_DMASREQ | SSI0 TX DMA single request, controlled by SSI0:DMACR.TXDMAE
0x2C | SSI1_RX_DMABREQ | SSI1 RX DMA burst request , controlled by SSI0:DMACR.RXDMAE
0x2D | SSI1_RX_DMASREQ | SSI1 RX DMA single request, controlled by SSI0:DMACR.RXDMAE
0x2E | SSI1_TX_DMABREQ | SSI1 TX DMA burst request , controlled by SSI0:DMACR.TXDMAE
0x2F | SSI1_TX_DMASREQ | SSI1 TX DMA single request, controlled by SSI0:DMACR.TXDMAE
0x30 | UART0_RX_DMABREQ | UART0 RX DMA burst request, controlled by UART0:DMACTL.RXDMAE
0x31 | UART0_RX_DMASREQ | UART0 RX DMA single request, controlled by UART0:DMACTL.RXDMAE
0x32 | UART0_TX_DMABREQ | UART0 TX DMA burst request, controlled by UART0:DMACTL.TXDMAE
0x33 | UART0_TX_DMASREQ | UART0 TX DMA single request, controlled by UART0:DMACTL.TXDMAE
0x38 | SPIS_COMB | SPIS Combined event, the flags are found here SPIS:GPFLAGS
0x39 | SPIS_RXF_DMABREQ | SPIS RX FIFO DMA burst request, controlled by SPIS:CFG.TR_DMA_REQ_TYPE
0x3A | SPIS_RXF_DMASREQ | SPIS RX FIFO DMA single request, controlled by SPIS:CFG.TR_DMA_REQ_TYPE
0x3B | SPIS_TXF_DMABREQ | SPIS TX FIFO DMA burst request, controlled by SPIS:CFG.TX_DMA_REQ_TYPE
0x3C | SPIS_TXF_DMASREQ | SPIS TX FIFO DMA single request, controlled by SPIS:CFG.TX_DMA_REQ_TYPE
0x3D | GPT0A_CMP | GPT0A compare event. Configured by GPT0:TAMR.TCACT
0x3E | GPT0B_CMP | GPT0B compare event. Configured by GPT0:TBMR.TCACT
0x3F | GPT1A_CMP | GPT1A compare event. Configured by GPT1:TAMR.TCACT
0x40 | GPT1B_CMP | GPT1B compare event. Configured by GPT1:TBMR.TCACT
0x41 | GPT2A_CMP | GPT2A compare event. Configured by GPT2:TAMR.TCACT
0x42 | GPT2B_CMP | GPT2B compare event. Configured by GPT2:TBMR.TCACT
0x43 | GPT3A_CMP | GPT3A compare event. Configured by GPT3:TAMR.TCACT
0x44 | GPT3B_CMP | GPT3B compare event. Configured by GPT3:TBMR.TCACT
0x4D | GPT0A_DMABREQ | GPT0A DMA trigger event. Configured by GPT0:DMAEV
0x4E | GPT0B_DMABREQ | GPT0B DMA trigger event. Configured by GPT0:DMAEV
0x4F | GPT1A_DMABREQ | GPT1A DMA trigger event. Configured by GPT1:DMAEV
0x50 | GPT1B_DMABREQ | GPT1B DMA trigger event. Configured by GPT1:DMAEV
0x51 | GPT2A_DMABREQ | GPT2A DMA trigger event. Configured by GPT2:DMAEV
0x52 | GPT2B_DMABREQ | GPT2B DMA trigger event. Configured by GPT2:DMAEV
0x53 | GPT3A_DMABREQ | GPT3A DMA trigger event. Configured by GPT3:DMAEV
0x54 | GPT3B_DMABREQ | GPT3B DMA trigger event. Configured by GPT3:DMAEV
0x55 | PORT_EVENT0 | Port capture event from IOC, configured by IOC:IOCFGn.PORT_ID. Events on ports configured with ENUM PORT_EVENT0 wil be routed here.
0x56 | PORT_EVENT1 | Port capture event from IOC, configured by IOC:IOCFGn.PORT_ID. Events on ports configured with ENUM PORT_EVENT1 wil be routed here.
0x57 | PORT_EVENT2 | Port capture event from IOC, configured by IOC:IOCFGn.PORT_ID. Events on ports configured with ENUM PORT_EVENT2 wil be routed here.
0x58 | PORT_EVENT3 | Port capture event from IOC, configured by IOC:IOCFGn.PORT_ID. Events on ports configured with ENUM PORT_EVENT3 wil be routed here.
0x59 | PORT_EVENT4 | Port capture event from IOC, configured by IOC:IOCFGn.PORT_ID. Events on ports configured with ENUM PORT_EVENT4 wil be routed here.
0x5A | PORT_EVENT5 | Port capture event from IOC, configured by IOC:IOCFGn.PORT_ID. Events on ports configured with ENUM PORT_EVENT4 wil be routed here.
0x5B | PORT_EVENT6 | Port capture event from IOC, configured by IOC:IOCFGn.PORT_ID. Events on ports configured with ENUM PORT_EVENT6 wil be routed here.
0x5C | PORT_EVENT7 | Port capture event from IOC, configured by IOC:IOCFGn.PORT_ID. Events on ports configured with ENUM PORT_EVENT7 wil be routed here.
0x5D | CRYPTO_RESULT_AVAIL_IRQ | CRYPTO result available interupt event, the corresponding flag is found here CRYPTO:IRQSTAT.RESULT_AVAIL. Controlled by CRYPTO:IRQSTAT.RESULT_AVAIL
0x5E | CRYPTO_DMA_DONE_IRQ | CRYPTO DMA input done event, the correspondingg flag is CRYPTO:IRQSTAT.DMA_IN_DONE. Controlled by CRYPTO:IRQEN.DMA_IN_DONE
0x5F | RFC_IN_EV4 | RFC RAT event 4, configured by RFC_RAT:RATEV.OEVT4
0x60 | RFC_IN_EV5 | RFC RAT event 5, configured by RFC_RAT:RATEV.OEVT5
0x61 | RFC_IN_EV6 | RFC RAT event 6, configured by RFC_RAT:RATEV.OEVT6
0x62 | RFC_IN_EV7 | RFC RAT event 7, configured by RFC_RAT:RATEV.OEVT7
0x63 | WDT_NMI | Watchdog non maskable interrupt event, controlled by WDT:CTL.INTTYPE
0x64 | SWEV0 | Software event 0, triggered by SWEV.SWEV0
0x65 | SWEV1 | Software event 1, triggered by SWEV.SWEV1
0x66 | SWEV2 | Software event 2, triggered by SWEV.SWEV2
0x67 | SWEV3 | Software event 3, triggered by SWEV.SWEV3
0x68 | TRNG_IRQ | TRNG Interrupt event, controlled by TRNG:IRQEN.EN
0x69 | AUX_AON_WU_EV | AON wakeup event, corresponds flags are here AUX_EVCTL:EVTOMCUFLAGS.AON_WU_EV
0x6A | AUX_COMPA | AUX Compare A event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA
0x6B | AUX_COMPB | AUX Compare B event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPB
0x6C | AUX_TDC_DONE | AUX TDC measurement done event, corresponds to the flag AUX_EVCTL:EVTOMCUFLAGS.TDC_DONE and the AUX_TDC status AUX_TDC:STAT.DONE
0x6D | AUX_TIMER0_EV | AUX timer 0 event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.TIMER0_EV
0x6E | AUX_TIMER1_EV | AUX timer 1 event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.TIMER1_EV
0x6F | AUX_SMPH_AUTOTAKE_DONE | Autotake event from AUX semaphore, configured by AUX_SMPH:AUTOTAKE
0x70 | AUX_ADC_DONE | AUX ADC done, corresponds to AUX_EVCTL:EVTOMCUFLAGS.ADC_DONE
0x71 | AUX_ADC_FIFO_ALMOST_FULL | AUX ADC FIFO watermark event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.ADC_FIFO_ALMOST_FULL
0x72 | AUX_OBSMUX0 | Loopback of OBSMUX0 through AUX, corresponds to AUX_EVCTL:EVTOMCUFLAGS.OBSMUX0
0x73 | AUX_ADC_IRQ | AUX ADC interrupt event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.ADC_IRQ. Status flags are found here [AUX_EVCTL:EVTOMCUFLAGS.ADC*]
0x74 | AUX_SW_DMABREQ | AUX observation loopback
0x75 | AUX_DMASREQ | DMA single request event from AUX, configured by AUX_EVCTL:DMACTL
0x76 | AUX_DMABREQ | DMA burst request event from AUX, configured by AUX_EVCTL:DMACTL
0x77 | AON_RTC_UPD | RTC periodic event controlled by AON_RTC:CTL.RTC_UPD_EN
0x78 | CPU_HALTED | CPU halted
0x79 | ALWAYS_ACTIVE | Always asserted
| RW | 0x01

### TOP:EVENT:UDMACH15BSEL

Address offset | 0x0000 057C
Physical address | 0x4008 357C | Instance | EVENT
Description | Output Selection for DMA Channel 15 REQ
Type | RO

Bits | Field Name | Description | Type | Reset
31:7 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x000 0000
6:0 | EV | Read only selection value
Value | ENUM name | Description
0x07 | AON_RTC_COMB | Event from AON_RTC controlled by the AON_RTC:CTL.COMB_EV_MASK setting
| RO | 0x07

### TOP:EVENT:UDMACH16SSEL

Address offset | 0x0000 0580
Physical address | 0x4008 3580 | Instance | EVENT
Description | Output Selection for DMA Channel 16 SREQ
Type | RO

Bits | Field Name | Description | Type | Reset
31:7 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x000 0000
6:0 | EV | Read only selection value
Value | ENUM name | Description
0x2D | SSI1_RX_DMASREQ | SSI1 RX DMA single request, controlled by SSI0:DMACR.RXDMAE
| RO | 0x2D

### TOP:EVENT:UDMACH16BSEL

Address offset | 0x0000 0584
Physical address | 0x4008 3584 | Instance | EVENT
Description | Output Selection for DMA Channel 16 REQ
Type | RO

Bits | Field Name | Description | Type | Reset
31:7 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x000 0000
6:0 | EV | Read only selection value
Value | ENUM name | Description
0x2C | SSI1_RX_DMABREQ | SSI1 RX DMA burst request , controlled by SSI0:DMACR.RXDMAE
| RO | 0x2C

### TOP:EVENT:UDMACH17SSEL

Address offset | 0x0000 0588
Physical address | 0x4008 3588 | Instance | EVENT
Description | Output Selection for DMA Channel 17 SREQ
Type | RO

Bits | Field Name | Description | Type | Reset
31:7 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x000 0000
6:0 | EV | Read only selection value
Value | ENUM name | Description
0x2F | SSI1_TX_DMASREQ | SSI1 TX DMA single request, controlled by SSI0:DMACR.TXDMAE
| RO | 0x2F

### TOP:EVENT:UDMACH17BSEL

Address offset | 0x0000 058C
Physical address | 0x4008 358C | Instance | EVENT
Description | Output Selection for DMA Channel 17 REQ
Type | RO

Bits | Field Name | Description | Type | Reset
31:7 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x000 0000
6:0 | EV | Read only selection value
Value | ENUM name | Description
0x2E | SSI1_TX_DMABREQ | SSI1 TX DMA burst request , controlled by SSI0:DMACR.TXDMAE
| RO | 0x2E

### TOP:EVENT:UDMACH21SSEL

Address offset | 0x0000 05A8
Physical address | 0x4008 35A8 | Instance | EVENT
Description | Output Selection for DMA Channel 21 SREQ
Type | RO

Bits | Field Name | Description | Type | Reset
31:7 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x000 0000
6:0 | EV | Read only selection value
Value | ENUM name | Description
0x64 | SWEV0 | Software event 0, triggered by SWEV.SWEV0
| RO | 0x64

### TOP:EVENT:UDMACH21BSEL

Address offset | 0x0000 05AC
Physical address | 0x4008 35AC | Instance | EVENT
Description | Output Selection for DMA Channel 21 REQ
Type | RO

Bits | Field Name | Description | Type | Reset
31:7 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x000 0000
6:0 | EV | Read only selection value
Value | ENUM name | Description
0x64 | SWEV0 | Software event 0, triggered by SWEV.SWEV0
| RO | 0x64

### TOP:EVENT:UDMACH22SSEL

Address offset | 0x0000 05B0
Physical address | 0x4008 35B0 | Instance | EVENT
Description | Output Selection for DMA Channel 22 SREQ
Type | RO

Bits | Field Name | Description | Type | Reset
31:7 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x000 0000
6:0 | EV | Read only selection value
Value | ENUM name | Description
0x65 | SWEV1 | Software event 1, triggered by SWEV.SWEV1
| RO | 0x65

### TOP:EVENT:UDMACH22BSEL

Address offset | 0x0000 05B4
Physical address | 0x4008 35B4 | Instance | EVENT
Description | Output Selection for DMA Channel 22 REQ
Type | RO

Bits | Field Name | Description | Type | Reset
31:7 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x000 0000
6:0 | EV | Read only selection value
Value | ENUM name | Description
0x65 | SWEV1 | Software event 1, triggered by SWEV.SWEV1
| RO | 0x65

### TOP:EVENT:UDMACH23SSEL

Address offset | 0x0000 05B8
Physical address | 0x4008 35B8 | Instance | EVENT
Description | Output Selection for DMA Channel 23 SREQ
Type | RO

Bits | Field Name | Description | Type | Reset
31:7 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x000 0000
6:0 | EV | Read only selection value
Value | ENUM name | Description
0x66 | SWEV2 | Software event 2, triggered by SWEV.SWEV2
| RO | 0x66

### TOP:EVENT:UDMACH23BSEL

Address offset | 0x0000 05BC
Physical address | 0x4008 35BC | Instance | EVENT
Description | Output Selection for DMA Channel 23 REQ
Type | RO

Bits | Field Name | Description | Type | Reset
31:7 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x000 0000
6:0 | EV | Read only selection value
Value | ENUM name | Description
0x66 | SWEV2 | Software event 2, triggered by SWEV.SWEV2
| RO | 0x66

### TOP:EVENT:UDMACH24SSEL

Address offset | 0x0000 05C0
Physical address | 0x4008 35C0 | Instance | EVENT
Description | Output Selection for DMA Channel 24 SREQ
Type | RO

Bits | Field Name | Description | Type | Reset
31:7 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x000 0000
6:0 | EV | Read only selection value
Value | ENUM name | Description
0x67 | SWEV3 | Software event 3, triggered by SWEV.SWEV3
| RO | 0x67

### TOP:EVENT:UDMACH24BSEL

Address offset | 0x0000 05C4
Physical address | 0x4008 35C4 | Instance | EVENT
Description | Output Selection for DMA Channel 24 REQ
Type | RO

Bits | Field Name | Description | Type | Reset
31:7 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x000 0000
6:0 | EV | Read only selection value
Value | ENUM name | Description
0x67 | SWEV3 | Software event 3, triggered by SWEV.SWEV3
| RO | 0x67

### TOP:EVENT:GPT3ACAPTSEL

Address offset | 0x0000 0600
Physical address | 0x4008 3600 | Instance | EVENT
Description | Output Selection for GPT3 0
Type | RW

Bits | Field Name | Description | Type | Reset
31:7 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x000 0000
6:0 | EV | Read/write selection value
Value | ENUM name | Description
0x00 | NONE | Always inactive
0x04 | AON_GPIO_EDGE | Edge detect event from IOC. Configureded by the IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET settings
0x05 | AON_SPIS_BYTE_DONE | A complete byte transfer event from the SPIS. Equivalent to the SPIS:GPFLAGS.BYTE_DONE flag
0x06 | AON_SPIS_CS | SPIS chip select event. Equivalent to the SPIS:GPFLAGS.CS flag
0x07 | AON_RTC_COMB | Event from AON_RTC controlled by the AON_RTC:CTL.COMB_EV_MASK setting
0x0B | AUX_COMB | AUX combined event, the corresponding flag register is here AUX_EVCTL:EVTOMCUFLAGS
0x15 | FLASH | FLASH controller error event, the status flags are FLASH:FEDACSTAT.FSM_DONE and FLASH:FEDACSTAT.RVF_INT
0x19 | RFC_CMD_ACK | RFC Doorbell Command Acknowledgement Interrupt, equvialent to RFC_DBELL:RFACKIFG.ACKFLAG
0x1A | RFC_HW_COMB | Combined RCF hardware interrupt, corresponding flag is here RFC_DBELL:RFHWIFG
0x1B | RFC_CPE_0 | Combined Interrupt for CPE Generated events. Corresponding flags are here RFC_DBELL:RFCPEIFG. Only interrupts selected with CPE0 in RFC_DBELL:RFCPEIFG can trigger a RFC_CPE_0 event
0x1E | RFC_CPE_1 | Combined Interrupt for CPE Generated events. Corresponding flags are here RFC_DBELL:RFCPEIFG. Only interrupts selected with CPE1 in RFC_DBELL:RFCPEIFG can trigger a RFC_CPE_1 event
0x22 | SSI0_COMB | SSI0 combined interrupt, interrupt flags are found here SSI0:MIS
0x23 | SSI1_COMB | SSI0 combined interrupt, interrupt flags are found here SSI1:MIS
0x24 | UART0_COMB | UART0 combined interrupt, interrupt flags are found here UART0:MIS
0x3D | GPT0A_CMP | GPT0A compare event. Configured by GPT0:TAMR.TCACT
0x3E | GPT0B_CMP | GPT0B compare event. Configured by GPT0:TBMR.TCACT
0x3F | GPT1A_CMP | GPT1A compare event. Configured by GPT1:TAMR.TCACT
0x40 | GPT1B_CMP | GPT1B compare event. Configured by GPT1:TBMR.TCACT
0x41 | GPT2A_CMP | GPT2A compare event. Configured by GPT2:TAMR.TCACT
0x42 | GPT2B_CMP | GPT2B compare event. Configured by GPT2:TBMR.TCACT
0x43 | GPT3A_CMP | GPT3A compare event. Configured by GPT3:TAMR.TCACT
0x44 | GPT3B_CMP | GPT3B compare event. Configured by GPT3:TBMR.TCACT
0x5B | PORT_EVENT6 | Port capture event from IOC, configured by IOC:IOCFGn.PORT_ID. Events on ports configured with ENUM PORT_EVENT6 wil be routed here.
0x5C | PORT_EVENT7 | Port capture event from IOC, configured by IOC:IOCFGn.PORT_ID. Events on ports configured with ENUM PORT_EVENT7 wil be routed here.
0x61 | RFC_IN_EV6 | RFC RAT event 6, configured by RFC_RAT:RATEV.OEVT6
0x62 | RFC_IN_EV7 | RFC RAT event 7, configured by RFC_RAT:RATEV.OEVT7
0x69 | AUX_AON_WU_EV | AON wakeup event, corresponds flags are here AUX_EVCTL:EVTOMCUFLAGS.AON_WU_EV
0x6A | AUX_COMPA | AUX Compare A event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA
0x6B | AUX_COMPB | AUX Compare B event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPB
0x6C | AUX_TDC_DONE | AUX TDC measurement done event, corresponds to the flag AUX_EVCTL:EVTOMCUFLAGS.TDC_DONE and the AUX_TDC status AUX_TDC:STAT.DONE
0x6D | AUX_TIMER0_EV | AUX timer 0 event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.TIMER0_EV
0x6E | AUX_TIMER1_EV | AUX timer 1 event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.TIMER1_EV
0x6F | AUX_SMPH_AUTOTAKE_DONE | Autotake event from AUX semaphore, configured by AUX_SMPH:AUTOTAKE
0x70 | AUX_ADC_DONE | AUX ADC done, corresponds to AUX_EVCTL:EVTOMCUFLAGS.ADC_DONE
0x71 | AUX_ADC_FIFO_ALMOST_FULL | AUX ADC FIFO watermark event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.ADC_FIFO_ALMOST_FULL
0x72 | AUX_OBSMUX0 | Loopback of OBSMUX0 through AUX, corresponds to AUX_EVCTL:EVTOMCUFLAGS.OBSMUX0
0x73 | AUX_ADC_IRQ | AUX ADC interrupt event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.ADC_IRQ. Status flags are found here [AUX_EVCTL:EVTOMCUFLAGS.ADC*]
0x77 | AON_RTC_UPD | RTC periodic event controlled by AON_RTC:CTL.RTC_UPD_EN
0x79 | ALWAYS_ACTIVE | Always asserted
| RW | 0x5B

### TOP:EVENT:GPT3BCAPTSEL

Address offset | 0x0000 0604
Physical address | 0x4008 3604 | Instance | EVENT
Description | Output Selection for GPT3 1
Type | RW

Bits | Field Name | Description | Type | Reset
31:7 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x000 0000
6:0 | EV | Read/write selection value
Value | ENUM name | Description
0x00 | NONE | Always inactive
0x04 | AON_GPIO_EDGE | Edge detect event from IOC. Configureded by the IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET settings
0x05 | AON_SPIS_BYTE_DONE | A complete byte transfer event from the SPIS. Equivalent to the SPIS:GPFLAGS.BYTE_DONE flag
0x06 | AON_SPIS_CS | SPIS chip select event. Equivalent to the SPIS:GPFLAGS.CS flag
0x07 | AON_RTC_COMB | Event from AON_RTC controlled by the AON_RTC:CTL.COMB_EV_MASK setting
0x0B | AUX_COMB | AUX combined event, the corresponding flag register is here AUX_EVCTL:EVTOMCUFLAGS
0x15 | FLASH | FLASH controller error event, the status flags are FLASH:FEDACSTAT.FSM_DONE and FLASH:FEDACSTAT.RVF_INT
0x19 | RFC_CMD_ACK | RFC Doorbell Command Acknowledgement Interrupt, equvialent to RFC_DBELL:RFACKIFG.ACKFLAG
0x1A | RFC_HW_COMB | Combined RCF hardware interrupt, corresponding flag is here RFC_DBELL:RFHWIFG
0x1B | RFC_CPE_0 | Combined Interrupt for CPE Generated events. Corresponding flags are here RFC_DBELL:RFCPEIFG. Only interrupts selected with CPE0 in RFC_DBELL:RFCPEIFG can trigger a RFC_CPE_0 event
0x1E | RFC_CPE_1 | Combined Interrupt for CPE Generated events. Corresponding flags are here RFC_DBELL:RFCPEIFG. Only interrupts selected with CPE1 in RFC_DBELL:RFCPEIFG can trigger a RFC_CPE_1 event
0x22 | SSI0_COMB | SSI0 combined interrupt, interrupt flags are found here SSI0:MIS
0x23 | SSI1_COMB | SSI0 combined interrupt, interrupt flags are found here SSI1:MIS
0x24 | UART0_COMB | UART0 combined interrupt, interrupt flags are found here UART0:MIS
0x3D | GPT0A_CMP | GPT0A compare event. Configured by GPT0:TAMR.TCACT
0x3E | GPT0B_CMP | GPT0B compare event. Configured by GPT0:TBMR.TCACT
0x3F | GPT1A_CMP | GPT1A compare event. Configured by GPT1:TAMR.TCACT
0x40 | GPT1B_CMP | GPT1B compare event. Configured by GPT1:TBMR.TCACT
0x41 | GPT2A_CMP | GPT2A compare event. Configured by GPT2:TAMR.TCACT
0x42 | GPT2B_CMP | GPT2B compare event. Configured by GPT2:TBMR.TCACT
0x43 | GPT3A_CMP | GPT3A compare event. Configured by GPT3:TAMR.TCACT
0x44 | GPT3B_CMP | GPT3B compare event. Configured by GPT3:TBMR.TCACT
0x5B | PORT_EVENT6 | Port capture event from IOC, configured by IOC:IOCFGn.PORT_ID. Events on ports configured with ENUM PORT_EVENT6 wil be routed here.
0x5C | PORT_EVENT7 | Port capture event from IOC, configured by IOC:IOCFGn.PORT_ID. Events on ports configured with ENUM PORT_EVENT7 wil be routed here.
0x61 | RFC_IN_EV6 | RFC RAT event 6, configured by RFC_RAT:RATEV.OEVT6
0x62 | RFC_IN_EV7 | RFC RAT event 7, configured by RFC_RAT:RATEV.OEVT7
0x69 | AUX_AON_WU_EV | AON wakeup event, corresponds flags are here AUX_EVCTL:EVTOMCUFLAGS.AON_WU_EV
0x6A | AUX_COMPA | AUX Compare A event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA
0x6B | AUX_COMPB | AUX Compare B event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPB
0x6C | AUX_TDC_DONE | AUX TDC measurement done event, corresponds to the flag AUX_EVCTL:EVTOMCUFLAGS.TDC_DONE and the AUX_TDC status AUX_TDC:STAT.DONE
0x6D | AUX_TIMER0_EV | AUX timer 0 event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.TIMER0_EV
0x6E | AUX_TIMER1_EV | AUX timer 1 event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.TIMER1_EV
0x6F | AUX_SMPH_AUTOTAKE_DONE | Autotake event from AUX semaphore, configured by AUX_SMPH:AUTOTAKE
0x70 | AUX_ADC_DONE | AUX ADC done, corresponds to AUX_EVCTL:EVTOMCUFLAGS.ADC_DONE
0x71 | AUX_ADC_FIFO_ALMOST_FULL | AUX ADC FIFO watermark event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.ADC_FIFO_ALMOST_FULL
0x72 | AUX_OBSMUX0 | Loopback of OBSMUX0 through AUX, corresponds to AUX_EVCTL:EVTOMCUFLAGS.OBSMUX0
0x73 | AUX_ADC_IRQ | AUX ADC interrupt event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.ADC_IRQ. Status flags are found here [AUX_EVCTL:EVTOMCUFLAGS.ADC*]
0x77 | AON_RTC_UPD | RTC periodic event controlled by AON_RTC:CTL.RTC_UPD_EN
0x79 | ALWAYS_ACTIVE | Always asserted
| RW | 0x5C

### TOP:EVENT:AUXSEL0

Address offset | 0x0000 0700
Physical address | 0x4008 3700 | Instance | EVENT
Description | Output Selection for AUX Subscriber 0
Type | RW

Bits | Field Name | Description | Type | Reset
31:7 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x000 0000
6:0 | EV | Read/write selection value
Value | ENUM name | Description
0x00 | NONE | Always inactive
0x0C | GPT2A | GPT2A interrupt event, controlled by GPT2:TAMR
0x0D | GPT2B | GPT2B interrupt event, controlled by GPT2:TBMR
0x0E | GPT3A | GPT3A interrupt event, controlled by GPT3:TAMR
0x0F | GPT3B | GPT3B interrupt event, controlled by GPT3:TBMR
0x10 | GPT0A | GPT0A interrupt event, controlled by GPT0:TAMR
0x11 | GPT0B | GPT0B interrupt event, controlled by GPT0:TBMR
0x12 | GPT1A | GPT1A interrupt event, controlled by GPT1:TAMR
0x13 | GPT1B | GPT1B interrupt event, controlled by GPT1:TBMR
0x79 | ALWAYS_ACTIVE | Always asserted
| RW | 0x10

### TOP:EVENT:CM3NMISEL0

Address offset | 0x0000 0800
Physical address | 0x4008 3800 | Instance | EVENT
Description | Output Selection for NMI Subscriber 0
Type | RO

Bits | Field Name | Description | Type | Reset
31:7 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x000 0000
6:0 | EV | Read only selection value
Value | ENUM name | Description
0x63 | WDT_NMI | Watchdog non maskable interrupt event, controlled by WDT:CTL.INTTYPE
| RO | 0x63

### TOP:EVENT:I2SSTMPSEL0

Address offset | 0x0000 0900
Physical address | 0x4008 3900 | Instance | EVENT
Description | Output Selection for I2S Subscriber 0
Type | RW

Bits | Field Name | Description | Type | Reset
31:7 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x000 0000
6:0 | EV | Read/write selection value
Value | ENUM name | Description
0x00 | NONE | Always inactive
0x5F | RFC_IN_EV4 | RFC RAT event 4, configured by RFC_RAT:RATEV.OEVT4
0x60 | RFC_IN_EV5 | RFC RAT event 5, configured by RFC_RAT:RATEV.OEVT5
0x61 | RFC_IN_EV6 | RFC RAT event 6, configured by RFC_RAT:RATEV.OEVT6
0x62 | RFC_IN_EV7 | RFC RAT event 7, configured by RFC_RAT:RATEV.OEVT7
0x79 | ALWAYS_ACTIVE | Always asserted
| RW | 0x5F

### TOP:EVENT:FRZSEL0

Address offset | 0x0000 0A00
Physical address | 0x4008 3A00 | Instance | EVENT
Description | Output Selection for FRZ Subscriber 0
Type | RW

Bits | Field Name | Description | Type | Reset
31:7 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x000 0000
6:0 | EV | Read/write selection value
Value | ENUM name | Description
0x00 | NONE | Always inactive
0x78 | CPU_HALTED | CPU halted
0x79 | ALWAYS_ACTIVE | Always asserted
| RW | 0x78

### TOP:EVENT:SWEV

Address offset | 0x0000 0F00
Physical address | 0x4008 3F00 | Instance | EVENT
Description | Set or Clear Software Events
Type | RW

Bits | Field Name | Description | Type | Reset
31:25 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x00
24 | SWEV3 | Writing &quot;1&quot; to this bit when the value is &quot;0&quot; triggers the Software 3 event. | RW | 0
23:17 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x00
16 | SWEV2 | Writing &quot;1&quot; to this bit when the value is &quot;0&quot; triggers the Software 2 event. | RW | 0
15:9 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x00
8 | SWEV1 | Writing &quot;1&quot; to this bit when the value is &quot;0&quot; triggers the Software 1 event. | RW | 0
7:1 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x00
0 | SWEV0 | Writing &quot;1&quot; to this bit when the value is &quot;0&quot; triggers the Software 0 event. | RW | 0