## IOC

Instance: IOC
Component: IOC
Base address: 0x40081000

IO Controller (IOC) - configures all the DIOs and resides in the MCU domain.

### TOP:IOC Register Summary

Register Name | Type | Register Width (Bits) | Register Reset | Address Offset | Physical Address
IOCFG0 | RW | 32 | 0x0000 6000 | 0x0000 0000 | 0x4008 1000
IOCFG1 | RW | 32 | 0x0000 6000 | 0x0000 0004 | 0x4008 1004
IOCFG2 | RW | 32 | 0x0000 6000 | 0x0000 0008 | 0x4008 1008
IOCFG3 | RW | 32 | 0x0000 6000 | 0x0000 000C | 0x4008 100C
IOCFG4 | RW | 32 | 0x0000 6000 | 0x0000 0010 | 0x4008 1010
IOCFG5 | RW | 32 | 0x0000 6000 | 0x0000 0014 | 0x4008 1014
IOCFG6 | RW | 32 | 0x0000 6000 | 0x0000 0018 | 0x4008 1018
IOCFG7 | RW | 32 | 0x0000 6000 | 0x0000 001C | 0x4008 101C
IOCFG8 | RW | 32 | 0x0000 6000 | 0x0000 0020 | 0x4008 1020
IOCFG9 | RW | 32 | 0x0000 6000 | 0x0000 0024 | 0x4008 1024
IOCFG10 | RW | 32 | 0x0000 6000 | 0x0000 0028 | 0x4008 1028
IOCFG11 | RW | 32 | 0x0000 6000 | 0x0000 002C | 0x4008 102C
IOCFG12 | RW | 32 | 0x0000 6000 | 0x0000 0030 | 0x4008 1030
IOCFG13 | RW | 32 | 0x0000 6000 | 0x0000 0034 | 0x4008 1034
IOCFG14 | RW | 32 | 0x0000 6000 | 0x0000 0038 | 0x4008 1038
IOCFG15 | RW | 32 | 0x0000 6000 | 0x0000 003C | 0x4008 103C
IOCFG16 | RW | 32 | 0x0008 6000 | 0x0000 0040 | 0x4008 1040
IOCFG17 | RW | 32 | 0x0010 6000 | 0x0000 0044 | 0x4008 1044
IOCFG18 | RW | 32 | 0x0000 6000 | 0x0000 0048 | 0x4008 1048
IOCFG19 | RW | 32 | 0x0000 6000 | 0x0000 004C | 0x4008 104C
IOCFG20 | RW | 32 | 0x0000 6000 | 0x0000 0050 | 0x4008 1050
IOCFG21 | RW | 32 | 0x0000 6000 | 0x0000 0054 | 0x4008 1054
IOCFG22 | RW | 32 | 0x0000 6000 | 0x0000 0058 | 0x4008 1058
IOCFG23 | RW | 32 | 0x0000 6000 | 0x0000 005C | 0x4008 105C
IOCFG24 | RW | 32 | 0x0000 6000 | 0x0000 0060 | 0x4008 1060
IOCFG25 | RW | 32 | 0x0000 6000 | 0x0000 0064 | 0x4008 1064
IOCFG26 | RW | 32 | 0x0000 6000 | 0x0000 0068 | 0x4008 1068
IOCFG27 | RW | 32 | 0x0000 6000 | 0x0000 006C | 0x4008 106C
IOCFG28 | RW | 32 | 0x0000 6000 | 0x0000 0070 | 0x4008 1070
IOCFG29 | RW | 32 | 0x0000 6000 | 0x0000 0074 | 0x4008 1074
IOCFG30 | RW | 32 | 0x0000 6000 | 0x0000 0078 | 0x4008 1078
IOCFG31 | RW | 32 | 0x0000 6000 | 0x0000 007C | 0x4008 107C

### TOP:IOC Register Descriptions

### TOP:IOC:IOCFG0

Address offset | 0x0000 0000
Physical address | 0x4008 1000 | Instance | IOC
Description | Configuration of DIO0
Type | RW

Bits | Field Name | Description | Type | Reset
31 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0
30 | HYST_EN | 0: Input hysteresis disable 1: Input hysteresis enable | RW | 0
29 | IE | 0: Input disabled 1: Input enabled Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be ignored. | RW | 0
28:27 | WU_CFG | If DIO is configured GPIO or non-AON peripheral signals, i.e. PORT_ID 0x00 or >0x08: 00: No wake-up 01: No wake-up 10: Wakes up from shutdown if this pad is going low. 11: Wakes up from shutdown if this pad is going high. If IO is configured for AON peripheral signals or AUX ie. PORT_ID 0x01-0x08, this register only sets wakeup enable or not. 00, 01: Wakeup disabled 10, 11: Wakeup enabled Polarity is controlled from AON registers. Note:When the MSB is set, the IOC will deactivate the output enable for the DIO. | RW | 0x0
26:24 | IOMODE | IO Mode N/A for IO configured for AON periph. signals and AUX ie. PORT_ID 0x01-0x08 AUX has its own open_source/drain configuration. 0x2: Reserved. Undefined behavior. 0x3: Reserved. Undefined behavior.
Value | ENUM name | Description
0x0 | NORMAL | Normal input / output
0x1 | INV | Inverted input / ouput
0x4 | OPENDR | Open Drain, Normal input / output
0x5 | OPENDR_INV | Open Drain Inverted input / output
0x6 | OPENSRC | Open Source Normal input / outut
0x7 | OPENSRC_INV | Open Source Inverted input/output
| RW | 0x0
23:21 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0
20 | Reserved |  | RW | 0
19 | Reserved |  | RW | 0
18 | EDGE_IRQ_EN | 0: No interrupt generation 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled) | RW | 0
17:16 | EDGE_DET | Enable generation of edge detection events on this IO
Value | ENUM name | Description
0x0 | NONE | No edge detection
0x1 | NEG | Negative edge detection
0x2 | POS | Positive edge detection
0x3 | BOTH | Positive and negative edge detection
| RW | 0x0
15 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0
14:13 | PULL_CTL | Pull control
Value | ENUM name | Description
0x1 | DWN | Pull down
0x2 | UP | Pull up
0x3 | DIS | No pull
| RW | 0x3
12 | SLEW_RED | 0: Normal slew rate 1: Enables reduced slew rate in output driver. | RW | 0
11:10 | IOCURR | Selects IO current in combination with IOSTR
Value | ENUM name | Description
0x0 | 2MA | 2 mA
0x1 | 4MA | 4 mA
0x2 | 4_8MA | 4 or 8 mA 8 mA if IO is double drive strength
| RW | 0x0
9:8 | IOSTR | Select drive strength IO
Value | ENUM name | Description
0x0 | AUTO | Automatic drive strength (2/4/8 mA@VDDS)
0x1 | MIN | Minimum drive strength (2/4/8 mA@3.3V)
0x2 | MED | Medium drive strength (2/4/8 mA@2.5V)
0x3 | MAX | Maximum drive strength (2/4/8 mA@1.8V)
| RW | 0x0
7:6 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0
5:0 | PORT_ID | Selects usage for DIO0
Value | ENUM name | Description
0x00 | GPIO | General Purpose IO
0x01 | AON_SCS | AON SPI-S SCS
0x02 | AON_SCK | AON SPI-S SCK
0x03 | AON_SDI | AON SPI-S SDI
0x04 | AON_SDO | AON SPI-S SDO
0x07 | AON_CLK32K | AON 32 KHz clock (SCLK_LF)
0x08 | AUX_IO | AUX IO
0x09 | SSI0_RX | SSI0 RX
0x0A | SSI0_TX | SSI0 TX
0x0B | SSI0_FSS | SSI0 FSS
0x0C | SSI0_CLK | SSI0 CLK
0x0D | I2C_MSSDA | I2C Data
0x0E | I2C_MSSCL | I2C Clock
0x0F | UART0_RX | UART0 RX
0x10 | UART0_TX | UART0 TX
0x11 | UART0_CTS | UART0 CTS
0x12 | UART0_RTS | UART0 RTS
0x17 | PORT_EVENT0 | PORT EVENT 0 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x18 | PORT_EVENT1 | PORT EVENT 1 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x19 | PORT_EVENT2 | PORT EVENT 2 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x1A | PORT_EVENT3 | PORT EVENT 3 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x1B | PORT_EVENT4 | PORT EVENT 4 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x1C | PORT_EVENT5 | PORT EVENT 5 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x1D | PORT_EVENT6 | PORT EVENT 6 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x1E | PORT_EVENT7 | PORT EVENT 7 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x20 | CPU_SWV | CPU SWV
0x21 | SSI1_RX | SSI1 RX
0x22 | SSI1_TX | SSI1 TX
0x23 | SSI1_FSS | SSI1 FSS
0x24 | SSI1_CLK | SSI1 CLK
0x25 | I2S_AD0 | I2S Data 0
0x26 | I2S_AD1 | I2S Data 1
0x27 | I2S_WCLK | I2S WCLK
0x28 | I2S_BCLK | I2S BCLK
0x29 | I2S_MCLK | I2S MCLK
0x2E | RFC_TRC | RF Core Trace
0x2F | RFC_GPO0 | RF Core Data Out 0
0x30 | RFC_GPO1 | RF Core Data Out 1
0x31 | RFC_GPO2 | RF Core Data Out 2
0x32 | RFC_GPO3 | RF Core Data Out 3
0x33 | RFC_GPI0 | RF Core Data In 0
0x34 | RFC_GPI1 | RF Core Data In 1
0x35 | RFC_SMI_DL_OUT | RF Core SMI Data Link Out
0x36 | RFC_SMI_DL_IN | RF Core SMI Data Link In
0x37 | RFC_SMI_CL_OUT | RF Core SMI Command Link Out
0x38 | RFC_SMI_CL_IN | RF Core SMI Command Link In
| RW | 0x00

### TOP:IOC:IOCFG1

Address offset | 0x0000 0004
Physical address | 0x4008 1004 | Instance | IOC
Description | Configuration of DIO1
Type | RW

Bits | Field Name | Description | Type | Reset
31 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0
30 | HYST_EN | 0: Input hysteresis disable 1: Input hysteresis enable | RW | 0
29 | IE | 0: Input disabled 1: Input enabled Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be ignored. | RW | 0
28:27 | WU_CFG | If DIO is configured GPIO or non-AON peripheral signals, i.e. PORT_ID 0x00 or >0x08: 00: No wake-up 01: No wake-up 10: Wakes up from shutdown if this pad is going low. 11: Wakes up from shutdown if this pad is going high. If IO is configured for AON peripheral signals or AUX ie. PORT_ID 0x01-0x08, this register only sets wakeup enable or not. 00, 01: Wakeup disabled 10, 11: Wakeup enabled Polarity is controlled from AON registers. Note:When the MSB is set, the IOC will deactivate the output enable for the DIO. | RW | 0x0
26:24 | IOMODE | IO Mode N/A for IO configured for AON periph. signals and AUX ie. PORT_ID 0x01-0x08 AUX has its own open_source/drain configuration. 0x2: Reserved. Undefined behavior. 0x3: Reserved. Undefined behavior.
Value | ENUM name | Description
0x0 | NORMAL | Normal input / output
0x1 | INV | Inverted input / ouput
0x4 | OPENDR | Open Drain, Normal input / output
0x5 | OPENDR_INV | Open Drain Inverted input / output
0x6 | OPENSRC | Open Source Normal input / output
0x7 | OPENSRC_INV | Open Source Inverted input / output
| RW | 0x0
23:21 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0
20 | Reserved |  | RW | 0
19 | Reserved |  | RW | 0
18 | EDGE_IRQ_EN | 0: No interrupt generation 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled) | RW | 0
17:16 | EDGE_DET | Enable generation of edge detection events on this IO
Value | ENUM name | Description
0x0 | NONE | No edge detection
0x1 | NEG | Negative edge detection
0x2 | POS | Positive edge detection
0x3 | BOTH | Positive and negative edge detection
| RW | 0x0
15 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0
14:13 | PULL_CTL | Pull control
Value | ENUM name | Description
0x1 | DWN | Pull down
0x2 | UP | Pull up
0x3 | DIS | No pull
| RW | 0x3
12 | SLEW_RED | 0: Normal slew rate 1: Enables reduced slew rate in output driver. | RW | 0
11:10 | IOCURR | Selects IO current in combination with IOSTR
Value | ENUM name | Description
0x0 | 2MA | 2 mA
0x1 | 4MA | 4 mA
0x2 | 4_8MA | 4 or 8 mA 8 mA if IO is double drive strength
| RW | 0x0
9:8 | IOSTR | Select drive strength IO
Value | ENUM name | Description
0x0 | AUTO | Automatic drive strength (2/4/8 mA@VDDS)
0x1 | MIN | Minimum drive strength (2/4/8 mA@3.3V)
0x2 | MED | Medium drive strength (2/4/8 mA@2.5V)
0x3 | MAX | Maximum drive strength (2/4/8 mA@1.8V)
| RW | 0x0
7:6 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0
5:0 | PORT_ID | Selects usage for DIO1
Value | ENUM name | Description
0x00 | GPIO | General Purpose IO
0x01 | AON_SCS | AON SPI-S SCS
0x02 | AON_SCK | AON SPI-S SCK
0x03 | AON_SDI | AON SPI-S SDI
0x04 | AON_SDO | AON SPI-S SDO
0x07 | AON_CLK32K | AON 32 KHz clock (SCLK_LF)
0x08 | AUX_IO | AUX IO
0x09 | SSI0_RX | SSI0 RX
0x0A | SSI0_TX | SSI0 TX
0x0B | SSI0_FSS | SSI0 FSS
0x0C | SSI0_CLK | SSI0 CLK
0x0D | I2C_MSSDA | I2C Data
0x0E | I2C_MSSCL | I2C Clock
0x0F | UART0_RX | UART0 RX
0x10 | UART0_TX | UART0 TX
0x11 | UART0_CTS | UART0 CTS
0x12 | UART0_RTS | UART0 RTS
0x17 | PORT_EVENT0 | PORT EVENT 0 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x18 | PORT_EVENT1 | PORT EVENT 1 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x19 | PORT_EVENT2 | PORT EVENT 2 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x1A | PORT_EVENT3 | PORT EVENT 3 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x1B | PORT_EVENT4 | PORT EVENT 4 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x1C | PORT_EVENT5 | PORT EVENT 5 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x1D | PORT_EVENT6 | PORT EVENT 6 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x1E | PORT_EVENT7 | PORT EVENT 7 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x20 | CPU_SWV | CPU SWV
0x21 | SSI1_RX | SSI1 RX
0x22 | SSI1_TX | SSI1 TX
0x23 | SSI1_FSS | SSI1 FSS
0x24 | SSI1_CLK | SSI1 CLK
0x25 | I2S_AD0 | I2S Data 0
0x26 | I2S_AD1 | I2S Data 1
0x27 | I2S_WCLK | I2S WCLK
0x28 | I2S_BCLK | I2S BCLK
0x29 | I2S_MCLK | I2S MCLK
0x2E | RFC_TRC | RF Core Trace
0x2F | RFC_GPO0 | RF Core Data Out 0
0x30 | RFC_GPO1 | RF Core Data Out 1
0x31 | RFC_GPO2 | RF Core Data Out 2
0x32 | RFC_GPO3 | RF Core Data Out 3
0x33 | RFC_GPI0 | RF Core Data In 0
0x34 | RFC_GPI1 | RF Core Data In 1
0x35 | RFC_SMI_DL_OUT | RF Core SMI Data Link Out
0x36 | RFC_SMI_DL_IN | RF Core SMI Data Link In
0x37 | RFC_SMI_CL_OUT | RF Core SMI Command Link Out
0x38 | RFC_SMI_CL_IN | RF Core SMI Command Link In
| RW | 0x00

### TOP:IOC:IOCFG2

Address offset | 0x0000 0008
Physical address | 0x4008 1008 | Instance | IOC
Description | Configuration of DIO2
Type | RW

Bits | Field Name | Description | Type | Reset
31 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0
30 | HYST_EN | 0: Input hysteresis disable 1: Input hysteresis enable | RW | 0
29 | IE | 0: Input disabled 1: Input enabled Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be ignored. | RW | 0
28:27 | WU_CFG | If DIO is configured GPIO or non-AON peripheral signals, i.e. PORT_ID 0x00 or >0x08: 00: No wake-up 01: No wake-up 10: Wakes up from shutdown if this pad is going low. 11: Wakes up from shutdown if this pad is going high. If IO is configured for AON peripheral signals or AUX ie. PORT_ID 0x01-0x08, this register only sets wakeup enable or not. 00, 01: Wakeup disabled 10, 11: Wakeup enabled Polarity is controlled from AON registers. Note:When the MSB is set, the IOC will deactivate the output enable for the DIO. | RW | 0x0
26:24 | IOMODE | IO Mode N/A for IO configured for AON periph. signals and AUX ie. PORT_ID 0x01-0x08 AUX has its own open_source/drain configuration. 0x2: Reserved. Undefined behavior. 0x3: Reserved. Undefined behavior.
Value | ENUM name | Description
0x0 | NORMAL | Normal input / output
0x1 | INV | Inverted input / ouput
0x4 | OPENDR | Open Drain, Normal input / output
0x5 | OPENDR_INV | Open Drain Inverted input / output
0x6 | OPENSRC | Open Source Normal input / output
0x7 | OPENSRC_INV | Open Source Inverted input / output
| RW | 0x0
23:21 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0
20 | Reserved |  | RW | 0
19 | Reserved |  | RW | 0
18 | EDGE_IRQ_EN | 0: No interrupt generation 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled) | RW | 0
17:16 | EDGE_DET | Enable generation of edge detection events on this IO
Value | ENUM name | Description
0x0 | NONE | No edge detection
0x1 | NEG | Negative edge detection
0x2 | POS | Positive edge detection
0x3 | BOTH | Positive and negative edge detection
| RW | 0x0
15 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0
14:13 | PULL_CTL | Pull control
Value | ENUM name | Description
0x1 | DWN | Pull down
0x2 | UP | Pull up
0x3 | DIS | No pull
| RW | 0x3
12 | SLEW_RED | 0: Normal slew rate 1: Enables reduced slew rate in output driver. | RW | 0
11:10 | IOCURR | Selects IO current in combination with IOSTR
Value | ENUM name | Description
0x0 | 2MA | 2 mA
0x1 | 4MA | 4 mA
0x2 | 4_8MA | 4 or 8 mA 8 mA if IO is double drive strength
| RW | 0x0
9:8 | IOSTR | Select drive strength IO
Value | ENUM name | Description
0x0 | AUTO | Automatic drive strength (2/4/8 mA@VDDS)
0x1 | MIN | Minimum drive strength (2/4/8 mA@3.3V)
0x2 | MED | Medium drive strength (2/4/8 mA@2.5V)
0x3 | MAX | Maximum drive strength (2/4/8 mA@1.8V)
| RW | 0x0
7:6 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0
5:0 | PORT_ID | Selects usage for DIO2
Value | ENUM name | Description
0x00 | GPIO | General Purpose IO
0x01 | AON_SCS | AON SPI-S SCS
0x02 | AON_SCK | AON SPI-S SCK
0x03 | AON_SDI | AON SPI-S SDI
0x04 | AON_SDO | AON SPI-S SDO
0x07 | AON_CLK32K | AON 32 KHz clock (SCLK_LF)
0x08 | AUX_IO | AUX IO
0x09 | SSI0_RX | SSI0 RX
0x0A | SSI0_TX | SSI0 TX
0x0B | SSI0_FSS | SSI0 FSS
0x0C | SSI0_CLK | SSI0 CLK
0x0D | I2C_MSSDA | I2C Data
0x0E | I2C_MSSCL | I2C Clock
0x0F | UART0_RX | UART0 RX
0x10 | UART0_TX | UART0 TX
0x11 | UART0_CTS | UART0 CTS
0x12 | UART0_RTS | UART0 RTS
0x17 | PORT_EVENT0 | PORT EVENT 0 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x18 | PORT_EVENT1 | PORT EVENT 1 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x19 | PORT_EVENT2 | PORT EVENT 2 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x1A | PORT_EVENT3 | PORT EVENT 3 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x1B | PORT_EVENT4 | PORT EVENT 4 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x1C | PORT_EVENT5 | PORT EVENT 5 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x1D | PORT_EVENT6 | PORT EVENT 6 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x1E | PORT_EVENT7 | PORT EVENT 7 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x20 | CPU_SWV | CPU SWV
0x21 | SSI1_RX | SSI1 RX
0x22 | SSI1_TX | SSI1 TX
0x23 | SSI1_FSS | SSI1 FSS
0x24 | SSI1_CLK | SSI1 CLK
0x25 | I2S_AD0 | I2S Data 0
0x26 | I2S_AD1 | I2S Data 1
0x27 | I2S_WCLK | I2S WCLK
0x28 | I2S_BCLK | I2S BCLK
0x29 | I2S_MCLK | I2S MCLK
0x2E | RFC_TRC | RF Core Trace
0x2F | RFC_GPO0 | RF Core Data Out 0
0x30 | RFC_GPO1 | RF Core Data Out 1
0x31 | RFC_GPO2 | RF Core Data Out 2
0x32 | RFC_GPO3 | RF Core Data Out 3
0x33 | RFC_GPI0 | RF Core Data In 0
0x34 | RFC_GPI1 | RF Core Data In 1
0x35 | RFC_SMI_DL_OUT | RF Core SMI Data Link Out
0x36 | RFC_SMI_DL_IN | RF Core SMI Data Link In
0x37 | RFC_SMI_CL_OUT | RF Core SMI Command Link Out
0x38 | RFC_SMI_CL_IN | RF Core SMI Command Link In
| RW | 0x00

### TOP:IOC:IOCFG3

Address offset | 0x0000 000C
Physical address | 0x4008 100C | Instance | IOC
Description | Configuration of DIO3
Type | RW

Bits | Field Name | Description | Type | Reset
31 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0
30 | HYST_EN | 0: Input hysteresis disable 1: Input hysteresis enable | RW | 0
29 | IE | 0: Input disabled 1: Input enabled Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be ignored. | RW | 0
28:27 | WU_CFG | If DIO is configured GPIO or non-AON peripheral signals, i.e. PORT_ID 0x00 or >0x08: 00: No wake-up 01: No wake-up 10: Wakes up from shutdown if this pad is going low. 11: Wakes up from shutdown if this pad is going high. If IO is configured for AON peripheral signals or AUX ie. PORT_ID 0x01-0x08, this register only sets wakeup enable or not. 00, 01: Wakeup disabled 10, 11: Wakeup enabled Polarity is controlled from AON registers. Note:When the MSB is set, the IOC will deactivate the output enable for the DIO. | RW | 0x0
26:24 | IOMODE | IO Mode N/A for IO configured for AON periph. signals and AUX ie. PORT_ID 0x01-0x08 AUX has its own open_source/drain configuration. 0x2: Reserved. Undefined behavior. 0x3: Reserved. Undefined behavior.
Value | ENUM name | Description
0x0 | NORMAL | Normal input / output
0x1 | INV | Inverted input / ouput
0x4 | OPENDR | Open Drain, Normal input / output
0x5 | OPENDR_INV | Open Drain Inverted input / output
0x6 | OPENSRC | Open Source Normal input / output
0x7 | OPENSRC_INV | Open Source Inverted input / output
| RW | 0x0
23:21 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0
20 | Reserved |  | RW | 0
19 | Reserved |  | RW | 0
18 | EDGE_IRQ_EN | 0: No interrupt generation 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled) | RW | 0
17:16 | EDGE_DET | Enable generation of edge detection events on this IO
Value | ENUM name | Description
0x0 | NONE | No edge detection
0x1 | NEG | Negative edge detection
0x2 | POS | Positive edge detection
0x3 | BOTH | Positive and negative edge detection
| RW | 0x0
15 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0
14:13 | PULL_CTL | Pull control
Value | ENUM name | Description
0x1 | DWN | Pull down
0x2 | UP | Pull up
0x3 | DIS | No pull
| RW | 0x3
12 | SLEW_RED | 0: Normal slew rate 1: Enables reduced slew rate in output driver. | RW | 0
11:10 | IOCURR | Selects IO current in combination with IOSTR
Value | ENUM name | Description
0x0 | 2MA | 2 mA
0x1 | 4MA | 4 mA
0x2 | 4_8MA | 4 or 8 mA 8 mA if IO is double drive strength
| RW | 0x0
9:8 | IOSTR | Select drive strength IO
Value | ENUM name | Description
0x0 | AUTO | Automatic drive strength (2/4/8 mA@VDDS)
0x1 | MIN | Minimum drive strength (2/4/8 mA@3.3V)
0x2 | MED | Medium drive strength (2/4/8 mA@2.5V)
0x3 | MAX | Maximum drive strength (2/4/8 mA@1.8V)
| RW | 0x0
7:6 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0
5:0 | PORT_ID | Selects usage for DIO3
Value | ENUM name | Description
0x00 | GPIO | General Purpose IO
0x01 | AON_SCS | AON SPI-S SCS
0x02 | AON_SCK | AON SPI-S SCK
0x03 | AON_SDI | AON SPI-S SDI
0x04 | AON_SDO | AON SPI-S SDO
0x07 | AON_CLK32K | AON 32 KHz clock (SCLK_LF)
0x08 | AUX_IO | AUX IO
0x09 | SSI0_RX | SSI0 RX
0x0A | SSI0_TX | SSI0 TX
0x0B | SSI0_FSS | SSI0 FSS
0x0C | SSI0_CLK | SSI0 CLK
0x0D | I2C_MSSDA | I2C Data
0x0E | I2C_MSSCL | I2C Clock
0x0F | UART0_RX | UART0 RX
0x10 | UART0_TX | UART0 TX
0x11 | UART0_CTS | UART0 CTS
0x12 | UART0_RTS | UART0 RTS
0x17 | PORT_EVENT0 | PORT EVENT 0 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x18 | PORT_EVENT1 | PORT EVENT 1 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x19 | PORT_EVENT2 | PORT EVENT 2 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x1A | PORT_EVENT3 | PORT EVENT 3 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x1B | PORT_EVENT4 | PORT EVENT 4 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x1C | PORT_EVENT5 | PORT EVENT 5 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x1D | PORT_EVENT6 | PORT EVENT 6 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x1E | PORT_EVENT7 | PORT EVENT 7 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x20 | CPU_SWV | CPU SWV
0x21 | SSI1_RX | SSI1 RX
0x22 | SSI1_TX | SSI1 TX
0x23 | SSI1_FSS | SSI1 FSS
0x24 | SSI1_CLK | SSI1 CLK
0x25 | I2S_AD0 | I2S Data 0
0x26 | I2S_AD1 | I2S Data 1
0x27 | I2S_WCLK | I2S WCLK
0x28 | I2S_BCLK | I2S BCLK
0x29 | I2S_MCLK | I2S MCLK
0x2E | RFC_TRC | RF Core Trace
0x2F | RFC_GPO0 | RF Core Data Out 0
0x30 | RFC_GPO1 | RF Core Data Out 1
0x31 | RFC_GPO2 | RF Core Data Out 2
0x32 | RFC_GPO3 | RF Core Data Out 3
0x33 | RFC_GPI0 | RF Core Data In 0
0x34 | RFC_GPI1 | RF Core Data In 1
0x35 | RFC_SMI_DL_OUT | RF Core SMI Data Link Out
0x36 | RFC_SMI_DL_IN | RF Core SMI Data Link In
0x37 | RFC_SMI_CL_OUT | RF Core SMI Command Link Out
0x38 | RFC_SMI_CL_IN | RF Core SMI Command Link In
| RW | 0x00

### TOP:IOC:IOCFG4

Address offset | 0x0000 0010
Physical address | 0x4008 1010 | Instance | IOC
Description | Configuration of DIO4
Type | RW

Bits | Field Name | Description | Type | Reset
31 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0
30 | HYST_EN | 0: Input hysteresis disable 1: Input hysteresis enable | RW | 0
29 | IE | 0: Input disabled 1: Input enabled Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be ignored. | RW | 0
28:27 | WU_CFG | If DIO is configured GPIO or non-AON peripheral signals, i.e. PORT_ID 0x00 or >0x08: 00: No wake-up 01: No wake-up 10: Wakes up from shutdown if this pad is going low. 11: Wakes up from shutdown if this pad is going high. If IO is configured for AON peripheral signals or AUX ie. PORT_ID 0x01-0x08, this register only sets wakeup enable or not. 00, 01: Wakeup disabled 10, 11: Wakeup enabled Polarity is controlled from AON registers. Note:When the MSB is set, the IOC will deactivate the output enable for the DIO. | RW | 0x0
26:24 | IOMODE | IO Mode N/A for IO configured for AON periph. signals and AUX ie. PORT_ID 0x01-0x08 AUX has its own open_source/drain configuration. 0x2: Reserved. Undefined behavior. 0x3: Reserved. Undefined behavior.
Value | ENUM name | Description
0x0 | NORMAL | Normal input / output
0x1 | INV | Inverted input / ouput
0x4 | OPENDR | Open Drain, Normal input / output
0x5 | OPENDR_INV | Open Drain Inverted input / output
0x6 | OPENSRC | Open Source Normal input / output
0x7 | OPENSRC_INV | Open Source Inverted input / output
| RW | 0x0
23:21 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0
20 | Reserved |  | RW | 0
19 | Reserved |  | RW | 0
18 | EDGE_IRQ_EN | 0: No interrupt generation 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled) | RW | 0
17:16 | EDGE_DET | Enable generation of edge detection events on this IO
Value | ENUM name | Description
0x0 | NONE | No edge detection
0x1 | NEG | Negative edge detection
0x2 | POS | Positive edge detection
0x3 | BOTH | Positive and negative edge detection
| RW | 0x0
15 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0
14:13 | PULL_CTL | Pull control
Value | ENUM name | Description
0x1 | DWN | Pull down
0x2 | UP | Pull up
0x3 | DIS | No pull
| RW | 0x3
12 | SLEW_RED | 0: Normal slew rate 1: Enables reduced slew rate in output driver. | RW | 0
11:10 | IOCURR | Selects IO current in combination with IOSTR
Value | ENUM name | Description
0x0 | 2MA | 2 mA
0x1 | 4MA | 4 mA
0x2 | 4_8MA | 4 or 8 mA 8 mA if IO is double drive strength
| RW | 0x0
9:8 | IOSTR | Select drive strength IO
Value | ENUM name | Description
0x0 | AUTO | Automatic drive strength (2/4/8 mA@VDDS)
0x1 | MIN | Minimum drive strength (2/4/8 mA@3.3V)
0x2 | MED | Medium drive strength (2/4/8 mA@2.5V)
0x3 | MAX | Maximum drive strength (2/4/8 mA@1.8V)
| RW | 0x0
7:6 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0
5:0 | PORT_ID | Selects usage for DIO4
Value | ENUM name | Description
0x00 | GPIO | General Purpose IO
0x01 | AON_SCS | AON SPI-S SCS
0x02 | AON_SCK | AON SPI-S SCK
0x03 | AON_SDI | AON SPI-S SDI
0x04 | AON_SDO | AON SPI-S SDO
0x07 | AON_CLK32K | AON 32 KHz clock (SCLK_LF)
0x08 | AUX_IO | AUX IO
0x09 | SSI0_RX | SSI0 RX
0x0A | SSI0_TX | SSI0 TX
0x0B | SSI0_FSS | SSI0 FSS
0x0C | SSI0_CLK | SSI0 CLK
0x0D | I2C_MSSDA | I2C Data
0x0E | I2C_MSSCL | I2C Clock
0x0F | UART0_RX | UART0 RX
0x10 | UART0_TX | UART0 TX
0x11 | UART0_CTS | UART0 CTS
0x12 | UART0_RTS | UART0 RTS
0x17 | PORT_EVENT0 | PORT EVENT 0 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x18 | PORT_EVENT1 | PORT EVENT 1 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x19 | PORT_EVENT2 | PORT EVENT 2 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x1A | PORT_EVENT3 | PORT EVENT 3 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x1B | PORT_EVENT4 | PORT EVENT 4 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x1C | PORT_EVENT5 | PORT EVENT 5 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x1D | PORT_EVENT6 | PORT EVENT 6 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x1E | PORT_EVENT7 | PORT EVENT 7 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x20 | CPU_SWV | CPU SWV
0x21 | SSI1_RX | SSI1 RX
0x22 | SSI1_TX | SSI1 TX
0x23 | SSI1_FSS | SSI1 FSS
0x24 | SSI1_CLK | SSI1 CLK
0x25 | I2S_AD0 | I2S Data 0
0x26 | I2S_AD1 | I2S Data 1
0x27 | I2S_WCLK | I2S WCLK
0x28 | I2S_BCLK | I2S BCLK
0x29 | I2S_MCLK | I2S MCLK
0x2E | RFC_TRC | RF Core Trace
0x2F | RFC_GPO0 | RF Core Data Out 0
0x30 | RFC_GPO1 | RF Core Data Out 1
0x31 | RFC_GPO2 | RF Core Data Out 2
0x32 | RFC_GPO3 | RF Core Data Out 3
0x33 | RFC_GPI0 | RF Core Data In 0
0x34 | RFC_GPI1 | RF Core Data In 1
0x35 | RFC_SMI_DL_OUT | RF Core SMI Data Link Out
0x36 | RFC_SMI_DL_IN | RF Core SMI Data Link In
0x37 | RFC_SMI_CL_OUT | RF Core SMI Command Link Out
0x38 | RFC_SMI_CL_IN | RF Core SMI Command Link In
| RW | 0x00

### TOP:IOC:IOCFG5

Address offset | 0x0000 0014
Physical address | 0x4008 1014 | Instance | IOC
Description | Configuration of DIO5
Type | RW

Bits | Field Name | Description | Type | Reset
31 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0
30 | HYST_EN | 0: Input hysteresis disable 1: Input hysteresis enable | RW | 0
29 | IE | 0: Input disabled 1: Input enabled Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be ignored. | RW | 0
28:27 | WU_CFG | If DIO is configured GPIO or non-AON peripheral signals, i.e. PORT_ID 0x00 or >0x08: 00: No wake-up 01: No wake-up 10: Wakes up from shutdown if this pad is going low. 11: Wakes up from shutdown if this pad is going high. If IO is configured for AON peripheral signals or AUX ie. PORT_ID 0x01-0x08, this register only sets wakeup enable or not. 00, 01: Wakeup disabled 10, 11: Wakeup enabled Polarity is controlled from AON registers. Note:When the MSB is set, the IOC will deactivate the output enable for the DIO. | RW | 0x0
26:24 | IOMODE | IO Mode N/A for IO configured for AON periph. signals and AUX ie. PORT_ID 0x01-0x08 AUX has its own open_source/drain configuration. 0x2: Reserved. Undefined behavior. 0x3: Reserved. Undefined behavior.
Value | ENUM name | Description
0x0 | NORMAL | Normal input / output
0x1 | INV | Inverted input / ouput
0x4 | OPENDR | Open Drain, Normal input / output
0x5 | OPENDR_INV | Open Drain Inverted input / output
0x6 | OPENSRC | Open Source Normal input / output
0x7 | OPENSRC_INV | Open Source Inverted input / output
| RW | 0x0
23:21 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0
20 | Reserved |  | RW | 0
19 | Reserved |  | RW | 0
18 | EDGE_IRQ_EN | 0: No interrupt generation 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled) | RW | 0
17:16 | EDGE_DET | Enable generation of edge detection events on this IO
Value | ENUM name | Description
0x0 | NONE | No edge detection
0x1 | NEG | Negative edge detection
0x2 | POS | Positive edge detection
0x3 | BOTH | Positive and negative edge detection
| RW | 0x0
15 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0
14:13 | PULL_CTL | Pull control
Value | ENUM name | Description
0x1 | DWN | Pull down
0x2 | UP | Pull up
0x3 | DIS | No pull
| RW | 0x3
12 | SLEW_RED | 0: Normal slew rate 1: Enables reduced slew rate in output driver. | RW | 0
11:10 | IOCURR | Selects IO current in combination with IOSTR
Value | ENUM name | Description
0x0 | 2MA | 2 mA
0x1 | 4MA | 4 mA
0x2 | 4_8MA | 4 or 8 mA 8 mA if IO is double drive strength
| RW | 0x0
9:8 | IOSTR | Select drive strength IO
Value | ENUM name | Description
0x0 | AUTO | Automatic drive strength (2/4/8 mA@VDDS)
0x1 | MIN | Minimum drive strength (2/4/8 mA@3.3V)
0x2 | MED | Medium drive strength (2/4/8 mA@2.5V)
0x3 | MAX | Maximum drive strength (2/4/8 mA@1.8V)
| RW | 0x0
7:6 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0
5:0 | PORT_ID | Selects usage for DIO5
Value | ENUM name | Description
0x00 | GPIO | General Purpose IO
0x01 | AON_SCS | AON SPI-S SCS
0x02 | AON_SCK | AON SPI-S SCK
0x03 | AON_SDI | AON SPI-S SDI
0x04 | AON_SDO | AON SPI-S SDO
0x07 | AON_CLK32K | AON 32 KHz clock (SCLK_LF)
0x08 | AUX_IO | AUX IO
0x09 | SSI0_RX | SSI0 RX
0x0A | SSI0_TX | SSI0 TX
0x0B | SSI0_FSS | SSI0 FSS
0x0C | SSI0_CLK | SSI0 CLK
0x0D | I2C_MSSDA | I2C Data
0x0E | I2C_MSSCL | I2C Clock
0x0F | UART0_RX | UART0 RX
0x10 | UART0_TX | UART0 TX
0x11 | UART0_CTS | UART0 CTS
0x12 | UART0_RTS | UART0 RTS
0x17 | PORT_EVENT0 | PORT EVENT 0 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x18 | PORT_EVENT1 | PORT EVENT 1 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x19 | PORT_EVENT2 | PORT EVENT 2 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x1A | PORT_EVENT3 | PORT EVENT 3 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x1B | PORT_EVENT4 | PORT EVENT 4 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x1C | PORT_EVENT5 | PORT EVENT 5 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x1D | PORT_EVENT6 | PORT EVENT 6 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x1E | PORT_EVENT7 | PORT EVENT 7 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x20 | CPU_SWV | CPU SWV
0x21 | SSI1_RX | SSI1 RX
0x22 | SSI1_TX | SSI1 TX
0x23 | SSI1_FSS | SSI1 FSS
0x24 | SSI1_CLK | SSI1 CLK
0x25 | I2S_AD0 | I2S Data 0
0x26 | I2S_AD1 | I2S Data 1
0x27 | I2S_WCLK | I2S WCLK
0x28 | I2S_BCLK | I2S BCLK
0x29 | I2S_MCLK | I2S MCLK
0x2E | RFC_TRC | RF Core Trace
0x2F | RFC_GPO0 | RF Core Data Out 0
0x30 | RFC_GPO1 | RF Core Data Out 1
0x31 | RFC_GPO2 | RF Core Data Out 2
0x32 | RFC_GPO3 | RF Core Data Out 3
0x33 | RFC_GPI0 | RF Core Data In 0
0x34 | RFC_GPI1 | RF Core Data In 1
0x35 | RFC_SMI_DL_OUT | RF Core SMI Data Link Out
0x36 | RFC_SMI_DL_IN | RF Core SMI Data Link In
0x37 | RFC_SMI_CL_OUT | RF Core SMI Command Link Out
0x38 | RFC_SMI_CL_IN | RF Core SMI Command Link In
| RW | 0x00

### TOP:IOC:IOCFG6

Address offset | 0x0000 0018
Physical address | 0x4008 1018 | Instance | IOC
Description | Configuration of DIO6
Type | RW

Bits | Field Name | Description | Type | Reset
31 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0
30 | HYST_EN | 0: Input hysteresis disable 1: Input hysteresis enable | RW | 0
29 | IE | 0: Input disabled 1: Input enabled Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be ignored. | RW | 0
28:27 | WU_CFG | If DIO is configured GPIO or non-AON peripheral signals, i.e. PORT_ID 0x00 or >0x08: 00: No wake-up 01: No wake-up 10: Wakes up from shutdown if this pad is going low. 11: Wakes up from shutdown if this pad is going high. If IO is configured for AON peripheral signals or AUX ie. PORT_ID 0x01-0x08, this register only sets wakeup enable or not. 00, 01: Wakeup disabled 10, 11: Wakeup enabled Polarity is controlled from AON registers. Note:When the MSB is set, the IOC will deactivate the output enable for the DIO. | RW | 0x0
26:24 | IOMODE | IO Mode N/A for IO configured for AON periph. signals and AUX ie. PORT_ID 0x01-0x08 AUX has its own open_source/drain configuration. 0x2: Reserved. Undefined behavior. 0x3: Reserved. Undefined behavior.
Value | ENUM name | Description
0x0 | NORMAL | Normal input / output
0x1 | INV | Inverted input / ouput
0x4 | OPENDR | Open Drain, Normal input / output
0x5 | OPENDR_INV | Open Drain Inverted input / output
0x6 | OPENSRC | Open Source Normal input / output
0x7 | OPENSRC_INV | Open Source Inverted input / output
| RW | 0x0
23:21 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0
20 | Reserved |  | RW | 0
19 | Reserved |  | RW | 0
18 | EDGE_IRQ_EN | 0: No interrupt generation 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled) | RW | 0
17:16 | EDGE_DET | Enable generation of edge detection events on this IO
Value | ENUM name | Description
0x0 | NONE | No edge detection
0x1 | NEG | Negative edge detection
0x2 | POS | Positive edge detection
0x3 | BOTH | Positive and negative edge detection
| RW | 0x0
15 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0
14:13 | PULL_CTL | Pull control
Value | ENUM name | Description
0x1 | DWN | Pull down
0x2 | UP | Pull up
0x3 | DIS | No pull
| RW | 0x3
12 | SLEW_RED | 0: Normal slew rate 1: Enables reduced slew rate in output driver. | RW | 0
11:10 | IOCURR | Selects IO current in combination with IOSTR
Value | ENUM name | Description
0x0 | 2MA | 2 mA
0x1 | 4MA | 4 mA
0x2 | 4_8MA | 4 or 8 mA 8 mA if IO is double drive strength
| RW | 0x0
9:8 | IOSTR | Select drive strength IO
Value | ENUM name | Description
0x0 | AUTO | Automatic drive strength (2/4/8 mA@VDDS)
0x1 | MIN | Minimum drive strength (2/4/8 mA@3.3V)
0x2 | MED | Medium drive strength (2/4/8 mA@2.5V)
0x3 | MAX | Maximum drive strength (2/4/8 mA@1.8V)
| RW | 0x0
7:6 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0
5:0 | PORT_ID | Selects usage for DIO6
Value | ENUM name | Description
0x00 | GPIO | General Purpose IO
0x01 | AON_SCS | AON SPI-S SCS
0x02 | AON_SCK | AON SPI-S SCK
0x03 | AON_SDI | AON SPI-S SDI
0x04 | AON_SDO | AON SPI-S SDO
0x07 | AON_CLK32K | AON 32 KHz clock (SCLK_LF)
0x08 | AUX_IO | AUX IO
0x09 | SSI0_RX | SSI0 RX
0x0A | SSI0_TX | SSI0 TX
0x0B | SSI0_FSS | SSI0 FSS
0x0C | SSI0_CLK | SSI0 CLK
0x0D | I2C_MSSDA | I2C Data
0x0E | I2C_MSSCL | I2C Clock
0x0F | UART0_RX | UART0 RX
0x10 | UART0_TX | UART0 TX
0x11 | UART0_CTS | UART0 CTS
0x12 | UART0_RTS | UART0 RTS
0x17 | PORT_EVENT0 | PORT EVENT 0 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x18 | PORT_EVENT1 | PORT EVENT 1 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x19 | PORT_EVENT2 | PORT EVENT 2 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x1A | PORT_EVENT3 | PORT EVENT 3 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x1B | PORT_EVENT4 | PORT EVENT 4 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x1C | PORT_EVENT5 | PORT EVENT 5 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x1D | PORT_EVENT6 | PORT EVENT 6 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x1E | PORT_EVENT7 | PORT EVENT 7 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x20 | CPU_SWV | CPU SWV
0x21 | SSI1_RX | SSI1 RX
0x22 | SSI1_TX | SSI1 TX
0x23 | SSI1_FSS | SSI1 FSS
0x24 | SSI1_CLK | SSI1 CLK
0x25 | I2S_AD0 | I2S Data 0
0x26 | I2S_AD1 | I2S Data 1
0x27 | I2S_WCLK | I2S WCLK
0x28 | I2S_BCLK | I2S BCLK
0x29 | I2S_MCLK | I2S MCLK
0x2E | RFC_TRC | RF Core Trace
0x2F | RFC_GPO0 | RF Core Data Out 0
0x30 | RFC_GPO1 | RF Core Data Out 1
0x31 | RFC_GPO2 | RF Core Data Out 2
0x32 | RFC_GPO3 | RF Core Data Out 3
0x33 | RFC_GPI0 | RF Core Data In 0
0x34 | RFC_GPI1 | RF Core Data In 1
0x35 | RFC_SMI_DL_OUT | RF Core SMI Data Link Out
0x36 | RFC_SMI_DL_IN | RF Core SMI Data Link In
0x37 | RFC_SMI_CL_OUT | RF Core SMI Command Link Out
0x38 | RFC_SMI_CL_IN | RF Core SMI Command Link In
| RW | 0x00

### TOP:IOC:IOCFG7

Address offset | 0x0000 001C
Physical address | 0x4008 101C | Instance | IOC
Description | Configuration of DIO7
Type | RW

Bits | Field Name | Description | Type | Reset
31 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0
30 | HYST_EN | 0: Input hysteresis disable 1: Input hysteresis enable | RW | 0
29 | IE | 0: Input disabled 1: Input enabled Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be ignored. | RW | 0
28:27 | WU_CFG | If DIO is configured GPIO or non-AON peripheral signals, i.e. PORT_ID 0x00 or >0x08: 00: No wake-up 01: No wake-up 10: Wakes up from shutdown if this pad is going low. 11: Wakes up from shutdown if this pad is going high. If IO is configured for AON peripheral signals or AUX ie. PORT_ID 0x01-0x08, this register only sets wakeup enable or not. 00, 01: Wakeup disabled 10, 11: Wakeup enabled Polarity is controlled from AON registers. Note:When the MSB is set, the IOC will deactivate the output enable for the DIO. | RW | 0x0
26:24 | IOMODE | IO Mode N/A for IO configured for AON periph. signals and AUX ie. PORT_ID 0x01-0x08 AUX has its own open_source/drain configuration. 0x2: Reserved. Undefined behavior. 0x3: Reserved. Undefined behavior.
Value | ENUM name | Description
0x0 | NORMAL | Normal input / output
0x1 | INV | Inverted input / ouput
0x4 | OPENDR | Open Drain, Normal input / output
0x5 | OPENDR_INV | Open Drain Inverted input / output
0x6 | OPENSRC | Open Source Normal input / output
0x7 | OPENSRC_INV | Open Source Inverted input / output
| RW | 0x0
23:21 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0
20 | Reserved |  | RW | 0
19 | Reserved |  | RW | 0
18 | EDGE_IRQ_EN | 0: No interrupt generation 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled) | RW | 0
17:16 | EDGE_DET | Enable generation of edge detection events on this IO
Value | ENUM name | Description
0x0 | NONE | No edge detection
0x1 | NEG | Negative edge detection
0x2 | POS | Positive edge detection
0x3 | BOTH | Positive and negative edge detection
| RW | 0x0
15 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0
14:13 | PULL_CTL | Pull control
Value | ENUM name | Description
0x1 | DWN | Pull down
0x2 | UP | Pull up
0x3 | DIS | No pull
| RW | 0x3
12 | SLEW_RED | 0: Normal slew rate 1: Enables reduced slew rate in output driver. | RW | 0
11:10 | IOCURR | Selects IO current in combination with IOSTR
Value | ENUM name | Description
0x0 | 2MA | 2 mA
0x1 | 4MA | 4 mA
0x2 | 4_8MA | 4 or 8 mA 8 mA if IO is double drive strength
| RW | 0x0
9:8 | IOSTR | Select drive strength IO
Value | ENUM name | Description
0x0 | AUTO | Automatic drive strength (2/4/8 mA@VDDS)
0x1 | MIN | Minimum drive strength (2/4/8 mA@3.3V)
0x2 | MED | Medium drive strength (2/4/8 mA@2.5V)
0x3 | MAX | Maximum drive strength (2/4/8 mA@1.8V)
| RW | 0x0
7:6 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0
5:0 | PORT_ID | Selects usage for DIO7
Value | ENUM name | Description
0x00 | GPIO | General Purpose IO
0x01 | AON_SCS | AON SPI-S SCS
0x02 | AON_SCK | AON SPI-S SCK
0x03 | AON_SDI | AON SPI-S SDI
0x04 | AON_SDO | AON SPI-S SDO
0x07 | AON_CLK32K | AON 32 KHz clock (SCLK_LF)
0x08 | AUX_IO | AUX IO
0x09 | SSI0_RX | SSI0 RX
0x0A | SSI0_TX | SSI0 TX
0x0B | SSI0_FSS | SSI0 FSS
0x0C | SSI0_CLK | SSI0 CLK
0x0D | I2C_MSSDA | I2C Data
0x0E | I2C_MSSCL | I2C Clock
0x0F | UART0_RX | UART0 RX
0x10 | UART0_TX | UART0 TX
0x11 | UART0_CTS | UART0 CTS
0x12 | UART0_RTS | UART0 RTS
0x17 | PORT_EVENT0 | PORT EVENT 0 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x18 | PORT_EVENT1 | PORT EVENT 1 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x19 | PORT_EVENT2 | PORT EVENT 2 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x1A | PORT_EVENT3 | PORT EVENT 3 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x1B | PORT_EVENT4 | PORT EVENT 4 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x1C | PORT_EVENT5 | PORT EVENT 5 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x1D | PORT_EVENT6 | PORT EVENT 6 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x1E | PORT_EVENT7 | PORT EVENT 7 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x20 | CPU_SWV | CPU SWV
0x21 | SSI1_RX | SSI1 RX
0x22 | SSI1_TX | SSI1 TX
0x23 | SSI1_FSS | SSI1 FSS
0x24 | SSI1_CLK | SSI1 CLK
0x25 | I2S_AD0 | I2S Data 0
0x26 | I2S_AD1 | I2S Data 1
0x27 | I2S_WCLK | I2S WCLK
0x28 | I2S_BCLK | I2S BCLK
0x29 | I2S_MCLK | I2S MCLK
0x2E | RFC_TRC | RF Core Trace
0x2F | RFC_GPO0 | RF Core Data Out 0
0x30 | RFC_GPO1 | RF Core Data Out 1
0x31 | RFC_GPO2 | RF Core Data Out 2
0x32 | RFC_GPO3 | RF Core Data Out 3
0x33 | RFC_GPI0 | RF Core Data In 0
0x34 | RFC_GPI1 | RF Core Data In 1
0x35 | RFC_SMI_DL_OUT | RF Core SMI Data Link Out
0x36 | RFC_SMI_DL_IN | RF Core SMI Data Link In
0x37 | RFC_SMI_CL_OUT | RF Core SMI Command Link Out
0x38 | RFC_SMI_CL_IN | RF Core SMI Command Link In
| RW | 0x00

### TOP:IOC:IOCFG8

Address offset | 0x0000 0020
Physical address | 0x4008 1020 | Instance | IOC
Description | Configuration of DIO8
Type | RW

Bits | Field Name | Description | Type | Reset
31 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0
30 | HYST_EN | 0: Input hysteresis disable 1: Input hysteresis enable | RW | 0
29 | IE | 0: Input disabled 1: Input enabled Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be ignored. | RW | 0
28:27 | WU_CFG | If DIO is configured GPIO or non-AON peripheral signals, i.e. PORT_ID 0x00 or >0x08: 00: No wake-up 01: No wake-up 10: Wakes up from shutdown if this pad is going low. 11: Wakes up from shutdown if this pad is going high. If IO is configured for AON peripheral signals or AUX ie. PORT_ID 0x01-0x08, this register only sets wakeup enable or not. 00, 01: Wakeup disabled 10, 11: Wakeup enabled Polarity is controlled from AON registers. Note:When the MSB is set, the IOC will deactivate the output enable for the DIO. | RW | 0x0
26:24 | IOMODE | IO Mode N/A for IO configured for AON periph. signals and AUX ie. PORT_ID 0x01-0x08 AUX has its own open_source/drain configuration. 0x2: Reserved. Undefined behavior. 0x3: Reserved. Undefined behavior.
Value | ENUM name | Description
0x0 | NORMAL | Normal input / output
0x1 | INV | Inverted input / ouput
0x4 | OPENDR | Open Drain, Normal input / output
0x5 | OPENDR_INV | Open Drain Inverted input / output
0x6 | OPENSRC | Open Source Normal input / output
0x7 | OPENSRC_INV | Open Source Inverted input / output
| RW | 0x0
23:21 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0
20 | Reserved |  | RW | 0
19 | Reserved |  | RW | 0
18 | EDGE_IRQ_EN | 0: No interrupt generation 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled) | RW | 0
17:16 | EDGE_DET | Enable generation of edge detection events on this IO
Value | ENUM name | Description
0x0 | NONE | No edge detection
0x1 | NEG | Negative edge detection
0x2 | POS | Positive edge detection
0x3 | BOTH | Positive and negative edge detection
| RW | 0x0
15 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0
14:13 | PULL_CTL | Pull control
Value | ENUM name | Description
0x1 | DWN | Pull down
0x2 | UP | Pull up
0x3 | DIS | No pull
| RW | 0x3
12 | SLEW_RED | 0: Normal slew rate 1: Enables reduced slew rate in output driver. | RW | 0
11:10 | IOCURR | Selects IO current in combination with IOSTR
Value | ENUM name | Description
0x0 | 2MA | 2 mA
0x1 | 4MA | 4 mA
0x2 | 4_8MA | 4 or 8 mA 8 mA if IO is double drive strength
| RW | 0x0
9:8 | IOSTR | Select drive strength IO
Value | ENUM name | Description
0x0 | AUTO | Automatic drive strength (2/4/8 mA@VDDS)
0x1 | MIN | Minimum drive strength (2/4/8 mA@3.3V)
0x2 | MED | Medium drive strength (2/4/8 mA@2.5V)
0x3 | MAX | Maximum drive strength (2/4/8 mA@1.8V)
| RW | 0x0
7:6 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0
5:0 | PORT_ID | Selects usage for DIO8
Value | ENUM name | Description
0x00 | GPIO | General Purpose IO
0x01 | AON_SCS | AON SPI-S SCS
0x02 | AON_SCK | AON SPI-S SCK
0x03 | AON_SDI | AON SPI-S SDI
0x04 | AON_SDO | AON SPI-S SDO
0x07 | AON_CLK32K | AON 32 KHz clock (SCLK_LF)
0x08 | AUX_IO | AUX IO
0x09 | SSI0_RX | SSI0 RX
0x0A | SSI0_TX | SSI0 TX
0x0B | SSI0_FSS | SSI0 FSS
0x0C | SSI0_CLK | SSI0 CLK
0x0D | I2C_MSSDA | I2C Data
0x0E | I2C_MSSCL | I2C Clock
0x0F | UART0_RX | UART0 RX
0x10 | UART0_TX | UART0 TX
0x11 | UART0_CTS | UART0 CTS
0x12 | UART0_RTS | UART0 RTS
0x17 | PORT_EVENT0 | PORT EVENT 0 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x18 | PORT_EVENT1 | PORT EVENT 1 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x19 | PORT_EVENT2 | PORT EVENT 2 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x1A | PORT_EVENT3 | PORT EVENT 3 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x1B | PORT_EVENT4 | PORT EVENT 4 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x1C | PORT_EVENT5 | PORT EVENT 5 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x1D | PORT_EVENT6 | PORT EVENT 6 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x1E | PORT_EVENT7 | PORT EVENT 7 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x20 | CPU_SWV | CPU SWV
0x21 | SSI1_RX | SSI1 RX
0x22 | SSI1_TX | SSI1 TX
0x23 | SSI1_FSS | SSI1 FSS
0x24 | SSI1_CLK | SSI1 CLK
0x25 | I2S_AD0 | I2S Data 0
0x26 | I2S_AD1 | I2S Data 1
0x27 | I2S_WCLK | I2S WCLK
0x28 | I2S_BCLK | I2S BCLK
0x29 | I2S_MCLK | I2S MCLK
0x2E | RFC_TRC | RF Core Trace
0x2F | RFC_GPO0 | RF Core Data Out 0
0x30 | RFC_GPO1 | RF Core Data Out 1
0x31 | RFC_GPO2 | RF Core Data Out 2
0x32 | RFC_GPO3 | RF Core Data Out 3
0x33 | RFC_GPI0 | RF Core Data In 0
0x34 | RFC_GPI1 | RF Core Data In 1
0x35 | RFC_SMI_DL_OUT | RF Core SMI Data Link Out
0x36 | RFC_SMI_DL_IN | RF Core SMI Data Link In
0x37 | RFC_SMI_CL_OUT | RF Core SMI Command Link Out
0x38 | RFC_SMI_CL_IN | RF Core SMI Command Link In
| RW | 0x00

### TOP:IOC:IOCFG9

Address offset | 0x0000 0024
Physical address | 0x4008 1024 | Instance | IOC
Description | Configuration of DIO9
Type | RW

Bits | Field Name | Description | Type | Reset
31 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0
30 | HYST_EN | 0: Input hysteresis disable 1: Input hysteresis enable | RW | 0
29 | IE | 0: Input disabled 1: Input enabled Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be ignored. | RW | 0
28:27 | WU_CFG | If DIO is configured GPIO or non-AON peripheral signals, i.e. PORT_ID 0x00 or >0x08: 00: No wake-up 01: No wake-up 10: Wakes up from shutdown if this pad is going low. 11: Wakes up from shutdown if this pad is going high. If IO is configured for AON peripheral signals or AUX ie. PORT_ID 0x01-0x08, this register only sets wakeup enable or not. 00, 01: Wakeup disabled 10, 11: Wakeup enabled Polarity is controlled from AON registers. Note:When the MSB is set, the IOC will deactivate the output enable for the DIO. | RW | 0x0
26:24 | IOMODE | IO Mode N/A for IO configured for AON periph. signals and AUX ie. PORT_ID 0x01-0x08 AUX has its own open_source/drain configuration. 0x2: Reserved. Undefined behavior. 0x3: Reserved. Undefined behavior.
Value | ENUM name | Description
0x0 | NORMAL | Normal input / output
0x1 | INV | Inverted input / ouput
0x4 | OPENDR | Open Drain, Normal input / output
0x5 | OPENDR_INV | Open Drain Inverted input / output
0x6 | OPENSRC | Open Source Normal input / output
0x7 | OPENSRC_INV | Open Source Inverted input / output
| RW | 0x0
23:21 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0
20 | Reserved |  | RW | 0
19 | Reserved |  | RW | 0
18 | EDGE_IRQ_EN | 0: No interrupt generation 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled) | RW | 0
17:16 | EDGE_DET | Enable generation of edge detection events on this IO
Value | ENUM name | Description
0x0 | NONE | No edge detection
0x1 | NEG | Negative edge detection
0x2 | POS | Positive edge detection
0x3 | BOTH | Positive and negative edge detection
| RW | 0x0
15 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0
14:13 | PULL_CTL | Pull control
Value | ENUM name | Description
0x1 | DWN | Pull down
0x2 | UP | Pull up
0x3 | DIS | No pull
| RW | 0x3
12 | SLEW_RED | 0: Normal slew rate 1: Enables reduced slew rate in output driver. | RW | 0
11:10 | IOCURR | Selects IO current in combination with IOSTR
Value | ENUM name | Description
0x0 | 2MA | 2 mA
0x1 | 4MA | 4 mA
0x2 | 4_8MA | 4 or 8 mA 8 mA if IO is double drive strength
| RW | 0x0
9:8 | IOSTR | Select drive strength IO
Value | ENUM name | Description
0x0 | AUTO | Automatic drive strength (2/4/8 mA@VDDS)
0x1 | MIN | Minimum drive strength (2/4/8 mA@3.3V)
0x2 | MED | Medium drive strength (2/4/8 mA@2.5V)
0x3 | MAX | Maximum drive strength (2/4/8 mA@1.8V)
| RW | 0x0
7:6 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0
5:0 | PORT_ID | Selects usage for DIO9
Value | ENUM name | Description
0x00 | GPIO | General Purpose IO
0x01 | AON_SCS | AON SPI-S SCS
0x02 | AON_SCK | AON SPI-S SCK
0x03 | AON_SDI | AON SPI-S SDI
0x04 | AON_SDO | AON SPI-S SDO
0x07 | AON_CLK32K | AON 32 KHz clock (SCLK_LF)
0x08 | AUX_IO | AUX IO
0x09 | SSI0_RX | SSI0 RX
0x0A | SSI0_TX | SSI0 TX
0x0B | SSI0_FSS | SSI0 FSS
0x0C | SSI0_CLK | SSI0 CLK
0x0D | I2C_MSSDA | I2C Data
0x0E | I2C_MSSCL | I2C Clock
0x0F | UART0_RX | UART0 RX
0x10 | UART0_TX | UART0 TX
0x11 | UART0_CTS | UART0 CTS
0x12 | UART0_RTS | UART0 RTS
0x17 | PORT_EVENT0 | PORT EVENT 0 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x18 | PORT_EVENT1 | PORT EVENT 1 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x19 | PORT_EVENT2 | PORT EVENT 2 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x1A | PORT_EVENT3 | PORT EVENT 3 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x1B | PORT_EVENT4 | PORT EVENT 4 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x1C | PORT_EVENT5 | PORT EVENT 5 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x1D | PORT_EVENT6 | PORT EVENT 6 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x1E | PORT_EVENT7 | PORT EVENT 7 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x20 | CPU_SWV | CPU SWV
0x21 | SSI1_RX | SSI1 RX
0x22 | SSI1_TX | SSI1 TX
0x23 | SSI1_FSS | SSI1 FSS
0x24 | SSI1_CLK | SSI1 CLK
0x25 | I2S_AD0 | I2S Data 0
0x26 | I2S_AD1 | I2S Data 1
0x27 | I2S_WCLK | I2S WCLK
0x28 | I2S_BCLK | I2S BCLK
0x29 | I2S_MCLK | I2S MCLK
0x2E | RFC_TRC | RF Core Trace
0x2F | RFC_GPO0 | RF Core Data Out 0
0x30 | RFC_GPO1 | RF Core Data Out 1
0x31 | RFC_GPO2 | RF Core Data Out 2
0x32 | RFC_GPO3 | RF Core Data Out 3
0x33 | RFC_GPI0 | RF Core Data In 0
0x34 | RFC_GPI1 | RF Core Data In 1
0x35 | RFC_SMI_DL_OUT | RF Core SMI Data Link Out
0x36 | RFC_SMI_DL_IN | RF Core SMI Data Link In
0x37 | RFC_SMI_CL_OUT | RF Core SMI Command Link Out
0x38 | RFC_SMI_CL_IN | RF Core SMI Command Link In
| RW | 0x00

### TOP:IOC:IOCFG10

Address offset | 0x0000 0028
Physical address | 0x4008 1028 | Instance | IOC
Description | Configuration of DIO10
Type | RW

Bits | Field Name | Description | Type | Reset
31 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0
30 | HYST_EN | 0: Input hysteresis disable 1: Input hysteresis enable | RW | 0
29 | IE | 0: Input disabled 1: Input enabled Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be ignored. | RW | 0
28:27 | WU_CFG | If DIO is configured GPIO or non-AON peripheral signals, i.e. PORT_ID 0x00 or >0x08: 00: No wake-up 01: No wake-up 10: Wakes up from shutdown if this pad is going low. 11: Wakes up from shutdown if this pad is going high. If IO is configured for AON peripheral signals or AUX ie. PORT_ID 0x01-0x08, this register only sets wakeup enable or not. 00, 01: Wakeup disabled 10, 11: Wakeup enabled Polarity is controlled from AON registers. Note:When the MSB is set, the IOC will deactivate the output enable for the DIO. | RW | 0x0
26:24 | IOMODE | IO Mode N/A for IO configured for AON periph. signals and AUX ie. PORT_ID 0x01-0x08 AUX has its own open_source/drain configuration. 0x2: Reserved. Undefined behavior. 0x3: Reserved. Undefined behavior.
Value | ENUM name | Description
0x0 | NORMAL | Normal input / output
0x1 | INV | Inverted input / ouput
0x4 | OPENDR | Open Drain, Normal input / output
0x5 | OPENDR_INV | Open Drain Inverted input / output
0x6 | OPENSRC | Open Source Normal input / output
0x7 | OPENSRC_INV | Open Source Inverted input / output
| RW | 0x0
23:21 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0
20 | Reserved |  | RW | 0
19 | Reserved |  | RW | 0
18 | EDGE_IRQ_EN | 0: No interrupt generation 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled) | RW | 0
17:16 | EDGE_DET | Enable generation of edge detection events on this IO
Value | ENUM name | Description
0x0 | NONE | No edge detection
0x1 | NEG | Negative edge detection
0x2 | POS | Positive edge detection
0x3 | BOTH | Positive and negative edge detection
| RW | 0x0
15 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0
14:13 | PULL_CTL | Pull control
Value | ENUM name | Description
0x1 | DWN | Pull down
0x2 | UP | Pull up
0x3 | DIS | No pull
| RW | 0x3
12 | SLEW_RED | 0: Normal slew rate 1: Enables reduced slew rate in output driver. | RW | 0
11:10 | IOCURR | Selects IO current in combination with IOSTR
Value | ENUM name | Description
0x0 | 2MA | 2 mA
0x1 | 4MA | 4 mA
0x2 | 4_8MA | 4 or 8 mA 8 mA if IO is double drive strength
| RW | 0x0
9:8 | IOSTR | Select drive strength IO
Value | ENUM name | Description
0x0 | AUTO | Automatic drive strength (2/4/8 mA@VDDS)
0x1 | MIN | Minimum drive strength (2/4/8 mA@3.3V)
0x2 | MED | Medium drive strength (2/4/8 mA@2.5V)
0x3 | MAX | Maximum drive strength (2/4/8 mA@1.8V)
| RW | 0x0
7:6 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0
5:0 | PORT_ID | Selects usage for DIO10
Value | ENUM name | Description
0x00 | GPIO | General Purpose IO
0x01 | AON_SCS | AON SPI-S SCS
0x02 | AON_SCK | AON SPI-S SCK
0x03 | AON_SDI | AON SPI-S SDI
0x04 | AON_SDO | AON SPI-S SDO
0x07 | AON_CLK32K | AON 32 KHz clock (SCLK_LF)
0x08 | AUX_IO | AUX IO
0x09 | SSI0_RX | SSI0 RX
0x0A | SSI0_TX | SSI0 TX
0x0B | SSI0_FSS | SSI0 FSS
0x0C | SSI0_CLK | SSI0 CLK
0x0D | I2C_MSSDA | I2C Data
0x0E | I2C_MSSCL | I2C Clock
0x0F | UART0_RX | UART0 RX
0x10 | UART0_TX | UART0 TX
0x11 | UART0_CTS | UART0 CTS
0x12 | UART0_RTS | UART0 RTS
0x17 | PORT_EVENT0 | PORT EVENT 0 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x18 | PORT_EVENT1 | PORT EVENT 1 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x19 | PORT_EVENT2 | PORT EVENT 2 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x1A | PORT_EVENT3 | PORT EVENT 3 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x1B | PORT_EVENT4 | PORT EVENT 4 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x1C | PORT_EVENT5 | PORT EVENT 5 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x1D | PORT_EVENT6 | PORT EVENT 6 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x1E | PORT_EVENT7 | PORT EVENT 7 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x20 | CPU_SWV | CPU SWV
0x21 | SSI1_RX | SSI1 RX
0x22 | SSI1_TX | SSI1 TX
0x23 | SSI1_FSS | SSI1 FSS
0x24 | SSI1_CLK | SSI1 CLK
0x25 | I2S_AD0 | I2S Data 0
0x26 | I2S_AD1 | I2S Data 1
0x27 | I2S_WCLK | I2S WCLK
0x28 | I2S_BCLK | I2S BCLK
0x29 | I2S_MCLK | I2S MCLK
0x2E | RFC_TRC | RF Core Trace
0x2F | RFC_GPO0 | RF Core Data Out 0
0x30 | RFC_GPO1 | RF Core Data Out 1
0x31 | RFC_GPO2 | RF Core Data Out 2
0x32 | RFC_GPO3 | RF Core Data Out 3
0x33 | RFC_GPI0 | RF Core Data In 0
0x34 | RFC_GPI1 | RF Core Data In 1
0x35 | RFC_SMI_DL_OUT | RF Core SMI Data Link Out
0x36 | RFC_SMI_DL_IN | RF Core SMI Data Link In
0x37 | RFC_SMI_CL_OUT | RF Core SMI Command Link Out
0x38 | RFC_SMI_CL_IN | RF Core SMI Command Link In
| RW | 0x00

### TOP:IOC:IOCFG11

Address offset | 0x0000 002C
Physical address | 0x4008 102C | Instance | IOC
Description | Configuration of DIO11
Type | RW

Bits | Field Name | Description | Type | Reset
31 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0
30 | HYST_EN | 0: Input hysteresis disable 1: Input hysteresis enable | RW | 0
29 | IE | 0: Input disabled 1: Input enabled Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be ignored. | RW | 0
28:27 | WU_CFG | If DIO is configured GPIO or non-AON peripheral signals, i.e. PORT_ID 0x00 or >0x08: 00: No wake-up 01: No wake-up 10: Wakes up from shutdown if this pad is going low. 11: Wakes up from shutdown if this pad is going high. If IO is configured for AON peripheral signals or AUX ie. PORT_ID 0x01-0x08, this register only sets wakeup enable or not. 00, 01: Wakeup disabled 10, 11: Wakeup enabled Polarity is controlled from AON registers. Note:When the MSB is set, the IOC will deactivate the output enable for the DIO. | RW | 0x0
26:24 | IOMODE | IO Mode N/A for IO configured for AON periph. signals and AUX ie. PORT_ID 0x01-0x08 AUX has its own open_source/drain configuration. 0x2: Reserved. Undefined behavior. 0x3: Reserved. Undefined behavior.
Value | ENUM name | Description
0x0 | NORMAL | Normal input / output
0x1 | INV | Inverted input / ouput
0x4 | OPENDR | Open Drain, Normal input / output
0x5 | OPENDR_INV | Open Drain Inverted input / output
0x6 | OPENSRC | Open Source Normal input / output
0x7 | OPENSRC_INV | Open Source Inverted input / output
| RW | 0x0
23:21 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0
20 | Reserved |  | RW | 0
19 | Reserved |  | RW | 0
18 | EDGE_IRQ_EN | 0: No interrupt generation 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled) | RW | 0
17:16 | EDGE_DET | Enable generation of edge detection events on this IO
Value | ENUM name | Description
0x0 | NONE | No edge detection
0x1 | NEG | Negative edge detection
0x2 | POS | Positive edge detection
0x3 | BOTH | Positive and negative edge detection
| RW | 0x0
15 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0
14:13 | PULL_CTL | Pull control
Value | ENUM name | Description
0x1 | DWN | Pull down
0x2 | UP | Pull up
0x3 | DIS | No pull
| RW | 0x3
12 | SLEW_RED | 0: Normal slew rate 1: Enables reduced slew rate in output driver. | RW | 0
11:10 | IOCURR | Selects IO current in combination with IOSTR
Value | ENUM name | Description
0x0 | 2MA | 2 mA
0x1 | 4MA | 4 mA
0x2 | 4_8MA | 4 or 8 mA 8 mA if IO is double drive strength
| RW | 0x0
9:8 | IOSTR | Select drive strength IO
Value | ENUM name | Description
0x0 | AUTO | Automatic drive strength (2/4/8 mA@VDDS)
0x1 | MIN | Minimum drive strength (2/4/8 mA@3.3V)
0x2 | MED | Medium drive strength (2/4/8 mA@2.5V)
0x3 | MAX | Maximum drive strength (2/4/8 mA@1.8V)
| RW | 0x0
7:6 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0
5:0 | PORT_ID | Selects usage for DIO11
Value | ENUM name | Description
0x00 | GPIO | General Purpose IO
0x01 | AON_SCS | AON SPI-S SCS
0x02 | AON_SCK | AON SPI-S SCK
0x03 | AON_SDI | AON SPI-S SDI
0x04 | AON_SDO | AON SPI-S SDO
0x07 | AON_CLK32K | AON 32 KHz clock (SCLK_LF)
0x08 | AUX_IO | AUX IO
0x09 | SSI0_RX | SSI0 RX
0x0A | SSI0_TX | SSI0 TX
0x0B | SSI0_FSS | SSI0 FSS
0x0C | SSI0_CLK | SSI0 CLK
0x0D | I2C_MSSDA | I2C Data
0x0E | I2C_MSSCL | I2C Clock
0x0F | UART0_RX | UART0 RX
0x10 | UART0_TX | UART0 TX
0x11 | UART0_CTS | UART0 CTS
0x12 | UART0_RTS | UART0 RTS
0x17 | PORT_EVENT0 | PORT EVENT 0 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x18 | PORT_EVENT1 | PORT EVENT 1 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x19 | PORT_EVENT2 | PORT EVENT 2 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x1A | PORT_EVENT3 | PORT EVENT 3 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x1B | PORT_EVENT4 | PORT EVENT 4 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x1C | PORT_EVENT5 | PORT EVENT 5 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x1D | PORT_EVENT6 | PORT EVENT 6 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x1E | PORT_EVENT7 | PORT EVENT 7 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x20 | CPU_SWV | CPU SWV
0x21 | SSI1_RX | SSI1 RX
0x22 | SSI1_TX | SSI1 TX
0x23 | SSI1_FSS | SSI1 FSS
0x24 | SSI1_CLK | SSI1 CLK
0x25 | I2S_AD0 | I2S Data 0
0x26 | I2S_AD1 | I2S Data 1
0x27 | I2S_WCLK | I2S WCLK
0x28 | I2S_BCLK | I2S BCLK
0x29 | I2S_MCLK | I2S MCLK
0x2E | RFC_TRC | RF Core Trace
0x2F | RFC_GPO0 | RF Core Data Out 0
0x30 | RFC_GPO1 | RF Core Data Out 1
0x31 | RFC_GPO2 | RF Core Data Out 2
0x32 | RFC_GPO3 | RF Core Data Out 3
0x33 | RFC_GPI0 | RF Core Data In 0
0x34 | RFC_GPI1 | RF Core Data In 1
0x35 | RFC_SMI_DL_OUT | RF Core SMI Data Link Out
0x36 | RFC_SMI_DL_IN | RF Core SMI Data Link In
0x37 | RFC_SMI_CL_OUT | RF Core SMI Command Link Out
0x38 | RFC_SMI_CL_IN | RF Core SMI Command Link In
| RW | 0x00

### TOP:IOC:IOCFG12

Address offset | 0x0000 0030
Physical address | 0x4008 1030 | Instance | IOC
Description | Configuration of DIO12
Type | RW

Bits | Field Name | Description | Type | Reset
31 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0
30 | HYST_EN | 0: Input hysteresis disable 1: Input hysteresis enable | RW | 0
29 | IE | 0: Input disabled 1: Input enabled Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be ignored. | RW | 0
28:27 | WU_CFG | If DIO is configured GPIO or non-AON peripheral signals, i.e. PORT_ID 0x00 or >0x08: 00: No wake-up 01: No wake-up 10: Wakes up from shutdown if this pad is going low. 11: Wakes up from shutdown if this pad is going high. If IO is configured for AON peripheral signals or AUX ie. PORT_ID 0x01-0x08, this register only sets wakeup enable or not. 00, 01: Wakeup disabled 10, 11: Wakeup enabled Polarity is controlled from AON registers. Note:When the MSB is set, the IOC will deactivate the output enable for the DIO. | RW | 0x0
26:24 | IOMODE | IO Mode N/A for IO configured for AON periph. signals and AUX ie. PORT_ID 0x01-0x08 AUX has its own open_source/drain configuration. 0x2: Reserved. Undefined behavior. 0x3: Reserved. Undefined behavior.
Value | ENUM name | Description
0x0 | NORMAL | Normal input / output
0x1 | INV | Inverted input / ouput
0x4 | OPENDR | Open Drain, Normal input / output
0x5 | OPENDR_INV | Open Drain Inverted input / output
0x6 | OPENSRC | Open Source Normal input / output
0x7 | OPENSRC_INV | Open Source Inverted input / output
| RW | 0x0
23:21 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0
20 | Reserved |  | RW | 0
19 | Reserved |  | RW | 0
18 | EDGE_IRQ_EN | 0: No interrupt generation 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled) | RW | 0
17:16 | EDGE_DET | Enable generation of edge detection events on this IO
Value | ENUM name | Description
0x0 | NONE | No edge detection
0x1 | NEG | Negative edge detection
0x2 | POS | Positive edge detection
0x3 | BOTH | Positive and negative edge detection
| RW | 0x0
15 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0
14:13 | PULL_CTL | Pull control
Value | ENUM name | Description
0x1 | DWN | Pull down
0x2 | UP | Pull up
0x3 | DIS | No pull
| RW | 0x3
12 | SLEW_RED | 0: Normal slew rate 1: Enables reduced slew rate in output driver. | RW | 0
11:10 | IOCURR | Selects IO current in combination with IOSTR
Value | ENUM name | Description
0x0 | 2MA | 2 mA
0x1 | 4MA | 4 mA
0x2 | 4_8MA | 4 or 8 mA 8 mA if IO is double drive strength
| RW | 0x0
9:8 | IOSTR | Select drive strength IO
Value | ENUM name | Description
0x0 | AUTO | Automatic drive strength (2/4/8 mA@VDDS)
0x1 | MIN | Minimum drive strength (2/4/8 mA@3.3V)
0x2 | MED | Medium drive strength (2/4/8 mA@2.5V)
0x3 | MAX | Maximum drive strength (2/4/8 mA@1.8V)
| RW | 0x0
7:6 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0
5:0 | PORT_ID | Selects usage for DIO12
Value | ENUM name | Description
0x00 | GPIO | General Purpose IO
0x01 | AON_SCS | AON SPI-S SCS
0x02 | AON_SCK | AON SPI-S SCK
0x03 | AON_SDI | AON SPI-S SDI
0x04 | AON_SDO | AON SPI-S SDO
0x07 | AON_CLK32K | AON 32 KHz clock (SCLK_LF)
0x08 | AUX_IO | AUX IO
0x09 | SSI0_RX | SSI0 RX
0x0A | SSI0_TX | SSI0 TX
0x0B | SSI0_FSS | SSI0 FSS
0x0C | SSI0_CLK | SSI0 CLK
0x0D | I2C_MSSDA | I2C Data
0x0E | I2C_MSSCL | I2C Clock
0x0F | UART0_RX | UART0 RX
0x10 | UART0_TX | UART0 TX
0x11 | UART0_CTS | UART0 CTS
0x12 | UART0_RTS | UART0 RTS
0x17 | PORT_EVENT0 | PORT EVENT 0 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x18 | PORT_EVENT1 | PORT EVENT 1 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x19 | PORT_EVENT2 | PORT EVENT 2 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x1A | PORT_EVENT3 | PORT EVENT 3 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x1B | PORT_EVENT4 | PORT EVENT 4 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x1C | PORT_EVENT5 | PORT EVENT 5 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x1D | PORT_EVENT6 | PORT EVENT 6 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x1E | PORT_EVENT7 | PORT EVENT 7 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x20 | CPU_SWV | CPU SWV
0x21 | SSI1_RX | SSI1 RX
0x22 | SSI1_TX | SSI1 TX
0x23 | SSI1_FSS | SSI1 FSS
0x24 | SSI1_CLK | SSI1 CLK
0x25 | I2S_AD0 | I2S Data 0
0x26 | I2S_AD1 | I2S Data 1
0x27 | I2S_WCLK | I2S WCLK
0x28 | I2S_BCLK | I2S BCLK
0x29 | I2S_MCLK | I2S MCLK
0x2E | RFC_TRC | RF Core Trace
0x2F | RFC_GPO0 | RF Core Data Out 0
0x30 | RFC_GPO1 | RF Core Data Out 1
0x31 | RFC_GPO2 | RF Core Data Out 2
0x32 | RFC_GPO3 | RF Core Data Out 3
0x33 | RFC_GPI0 | RF Core Data In 0
0x34 | RFC_GPI1 | RF Core Data In 1
0x35 | RFC_SMI_DL_OUT | RF Core SMI Data Link Out
0x36 | RFC_SMI_DL_IN | RF Core SMI Data Link In
0x37 | RFC_SMI_CL_OUT | RF Core SMI Command Link Out
0x38 | RFC_SMI_CL_IN | RF Core SMI Command Link In
| RW | 0x00

### TOP:IOC:IOCFG13

Address offset | 0x0000 0034
Physical address | 0x4008 1034 | Instance | IOC
Description | Configuration of DIO13
Type | RW

Bits | Field Name | Description | Type | Reset
31 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0
30 | HYST_EN | 0: Input hysteresis disable 1: Input hysteresis enable | RW | 0
29 | IE | 0: Input disabled 1: Input enabled Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be ignored. | RW | 0
28:27 | WU_CFG | If DIO is configured GPIO or non-AON peripheral signals, i.e. PORT_ID 0x00 or >0x08: 00: No wake-up 01: No wake-up 10: Wakes up from shutdown if this pad is going low. 11: Wakes up from shutdown if this pad is going high. If IO is configured for AON peripheral signals or AUX ie. PORT_ID 0x01-0x08, this register only sets wakeup enable or not. 00, 01: Wakeup disabled 10, 11: Wakeup enabled Polarity is controlled from AON registers. Note:When the MSB is set, the IOC will deactivate the output enable for the DIO. | RW | 0x0
26:24 | IOMODE | IO Mode N/A for IO configured for AON periph. signals and AUX ie. PORT_ID 0x01-0x08 AUX has its own open_source/drain configuration. 0x2: Reserved. Undefined behavior. 0x3: Reserved. Undefined behavior.
Value | ENUM name | Description
0x0 | NORMAL | Normal input / output
0x1 | INV | Inverted input / ouput
0x4 | OPENDR | Open Drain, Normal input / output
0x5 | OPENDR_INV | Open Drain Inverted input / output
0x6 | OPENSRC | Open Source Normal input / output
0x7 | OPENSRC_INV | Open Source Inverted input / output
| RW | 0x0
23:21 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0
20 | Reserved |  | RW | 0
19 | Reserved |  | RW | 0
18 | EDGE_IRQ_EN | 0: No interrupt generation 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled) | RW | 0
17:16 | EDGE_DET | Enable generation of edge detection events on this IO
Value | ENUM name | Description
0x0 | NONE | No edge detection
0x1 | NEG | Negative edge detection
0x2 | POS | Positive edge detection
0x3 | BOTH | Positive and negative edge detection
| RW | 0x0
15 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0
14:13 | PULL_CTL | Pull control
Value | ENUM name | Description
0x1 | DWN | Pull down
0x2 | UP | Pull up
0x3 | DIS | No pull
| RW | 0x3
12 | SLEW_RED | 0: Normal slew rate 1: Enables reduced slew rate in output driver. | RW | 0
11:10 | IOCURR | Selects IO current in combination with IOSTR
Value | ENUM name | Description
0x0 | 2MA | 2 mA
0x1 | 4MA | 4 mA
0x2 | 4_8MA | 4 or 8 mA 8 mA if IO is double drive strength
| RW | 0x0
9:8 | IOSTR | Select drive strength IO
Value | ENUM name | Description
0x0 | AUTO | Automatic drive strength (2/4/8 mA@VDDS)
0x1 | MIN | Minimum drive strength (2/4/8 mA@3.3V)
0x2 | MED | Medium drive strength (2/4/8 mA@2.5V)
0x3 | MAX | Maximum drive strength (2/4/8 mA@1.8V)
| RW | 0x0
7:6 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0
5:0 | PORT_ID | Selects usage for DIO13
Value | ENUM name | Description
0x00 | GPIO | General Purpose IO
0x01 | AON_SCS | AON SPI-S SCS
0x02 | AON_SCK | AON SPI-S SCK
0x03 | AON_SDI | AON SPI-S SDI
0x04 | AON_SDO | AON SPI-S SDO
0x07 | AON_CLK32K | AON 32 KHz clock (SCLK_LF)
0x08 | AUX_IO | AUX IO
0x09 | SSI0_RX | SSI0 RX
0x0A | SSI0_TX | SSI0 TX
0x0B | SSI0_FSS | SSI0 FSS
0x0C | SSI0_CLK | SSI0 CLK
0x0D | I2C_MSSDA | I2C Data
0x0E | I2C_MSSCL | I2C Clock
0x0F | UART0_RX | UART0 RX
0x10 | UART0_TX | UART0 TX
0x11 | UART0_CTS | UART0 CTS
0x12 | UART0_RTS | UART0 RTS
0x17 | PORT_EVENT0 | PORT EVENT 0 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x18 | PORT_EVENT1 | PORT EVENT 1 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x19 | PORT_EVENT2 | PORT EVENT 2 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x1A | PORT_EVENT3 | PORT EVENT 3 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x1B | PORT_EVENT4 | PORT EVENT 4 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x1C | PORT_EVENT5 | PORT EVENT 5 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x1D | PORT_EVENT6 | PORT EVENT 6 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x1E | PORT_EVENT7 | PORT EVENT 7 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x20 | CPU_SWV | CPU SWV
0x21 | SSI1_RX | SSI1 RX
0x22 | SSI1_TX | SSI1 TX
0x23 | SSI1_FSS | SSI1 FSS
0x24 | SSI1_CLK | SSI1 CLK
0x25 | I2S_AD0 | I2S Data 0
0x26 | I2S_AD1 | I2S Data 1
0x27 | I2S_WCLK | I2S WCLK
0x28 | I2S_BCLK | I2S BCLK
0x29 | I2S_MCLK | I2S MCLK
0x2E | RFC_TRC | RF Core Trace
0x2F | RFC_GPO0 | RF Core Data Out 0
0x30 | RFC_GPO1 | RF Core Data Out 1
0x31 | RFC_GPO2 | RF Core Data Out 2
0x32 | RFC_GPO3 | RF Core Data Out 3
0x33 | RFC_GPI0 | RF Core Data In 0
0x34 | RFC_GPI1 | RF Core Data In 1
0x35 | RFC_SMI_DL_OUT | RF Core SMI Data Link Out
0x36 | RFC_SMI_DL_IN | RF Core SMI Data Link In
0x37 | RFC_SMI_CL_OUT | RF Core SMI Command Link Out
0x38 | RFC_SMI_CL_IN | RF Core SMI Command Link In
| RW | 0x00

### TOP:IOC:IOCFG14

Address offset | 0x0000 0038
Physical address | 0x4008 1038 | Instance | IOC
Description | Configuration of DIO14
Type | RW

Bits | Field Name | Description | Type | Reset
31 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0
30 | HYST_EN | 0: Input hysteresis disable 1: Input hysteresis enable | RW | 0
29 | IE | 0: Input disabled 1: Input enabled Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be ignored. | RW | 0
28:27 | WU_CFG | If DIO is configured GPIO or non-AON peripheral signals, i.e. PORT_ID 0x00 or >0x08: 00: No wake-up 01: No wake-up 10: Wakes up from shutdown if this pad is going low. 11: Wakes up from shutdown if this pad is going high. If IO is configured for AON peripheral signals or AUX ie. PORT_ID 0x01-0x08, this register only sets wakeup enable or not. 00, 01: Wakeup disabled 10, 11: Wakeup enabled Polarity is controlled from AON registers. Note:When the MSB is set, the IOC will deactivate the output enable for the DIO. | RW | 0x0
26:24 | IOMODE | IO Mode N/A for IO configured for AON periph. signals and AUX ie. PORT_ID 0x01-0x08 AUX has its own open_source/drain configuration. 0x2: Reserved. Undefined behavior. 0x3: Reserved. Undefined behavior.
Value | ENUM name | Description
0x0 | NORMAL | Normal input / output
0x1 | INV | Inverted input / ouput
0x4 | OPENDR | Open Drain, Normal input / output
0x5 | OPENDR_INV | Open Drain Inverted input / output
0x6 | OPENSRC | Open Source Normal input / output
0x7 | OPENSRC_INV | Open Source Inverted input / output
| RW | 0x0
23:21 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0
20 | Reserved |  | RW | 0
19 | Reserved |  | RW | 0
18 | EDGE_IRQ_EN | 0: No interrupt generation 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled) | RW | 0
17:16 | EDGE_DET | Enable generation of edge detection events on this IO
Value | ENUM name | Description
0x0 | NONE | No edge detection
0x1 | NEG | Negative edge detection
0x2 | POS | Positive edge detection
0x3 | BOTH | Positive and negative edge detection
| RW | 0x0
15 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0
14:13 | PULL_CTL | Pull control
Value | ENUM name | Description
0x1 | DWN | Pull down
0x2 | UP | Pull up
0x3 | DIS | No pull
| RW | 0x3
12 | SLEW_RED | 0: Normal slew rate 1: Enables reduced slew rate in output driver. | RW | 0
11:10 | IOCURR | Selects IO current in combination with IOSTR
Value | ENUM name | Description
0x0 | 2MA | 2 mA
0x1 | 4MA | 4 mA
0x2 | 4_8MA | 4 or 8 mA 8 mA if IO is double drive strength
| RW | 0x0
9:8 | IOSTR | Select drive strength IO
Value | ENUM name | Description
0x0 | AUTO | Automatic drive strength (2/4/8 mA@VDDS)
0x1 | MIN | Minimum drive strength (2/4/8 mA@3.3V)
0x2 | MED | Medium drive strength (2/4/8 mA@2.5V)
0x3 | MAX | Maximum drive strength (2/4/8 mA@1.8V)
| RW | 0x0
7:6 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0
5:0 | PORT_ID | Selects usage for DIO14
Value | ENUM name | Description
0x00 | GPIO | General Purpose IO
0x01 | AON_SCS | AON SPI-S SCS
0x02 | AON_SCK | AON SPI-S SCK
0x03 | AON_SDI | AON SPI-S SDI
0x04 | AON_SDO | AON SPI-S SDO
0x07 | AON_CLK32K | AON 32 KHz clock (SCLK_LF)
0x08 | AUX_IO | AUX IO
0x09 | SSI0_RX | SSI0 RX
0x0A | SSI0_TX | SSI0 TX
0x0B | SSI0_FSS | SSI0 FSS
0x0C | SSI0_CLK | SSI0 CLK
0x0D | I2C_MSSDA | I2C Data
0x0E | I2C_MSSCL | I2C Clock
0x0F | UART0_RX | UART0 RX
0x10 | UART0_TX | UART0 TX
0x11 | UART0_CTS | UART0 CTS
0x12 | UART0_RTS | UART0 RTS
0x17 | PORT_EVENT0 | PORT EVENT 0 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x18 | PORT_EVENT1 | PORT EVENT 1 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x19 | PORT_EVENT2 | PORT EVENT 2 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x1A | PORT_EVENT3 | PORT EVENT 3 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x1B | PORT_EVENT4 | PORT EVENT 4 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x1C | PORT_EVENT5 | PORT EVENT 5 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x1D | PORT_EVENT6 | PORT EVENT 6 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x1E | PORT_EVENT7 | PORT EVENT 7 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x20 | CPU_SWV | CPU SWV
0x21 | SSI1_RX | SSI1 RX
0x22 | SSI1_TX | SSI1 TX
0x23 | SSI1_FSS | SSI1 FSS
0x24 | SSI1_CLK | SSI1 CLK
0x25 | I2S_AD0 | I2S Data 0
0x26 | I2S_AD1 | I2S Data 1
0x27 | I2S_WCLK | I2S WCLK
0x28 | I2S_BCLK | I2S BCLK
0x29 | I2S_MCLK | I2S MCLK
0x2E | RFC_TRC | RF Core Trace
0x2F | RFC_GPO0 | RF Core Data Out 0
0x30 | RFC_GPO1 | RF Core Data Out 1
0x31 | RFC_GPO2 | RF Core Data Out 2
0x32 | RFC_GPO3 | RF Core Data Out 3
0x33 | RFC_GPI0 | RF Core Data In 0
0x34 | RFC_GPI1 | RF Core Data In 1
0x35 | RFC_SMI_DL_OUT | RF Core SMI Data Link Out
0x36 | RFC_SMI_DL_IN | RF Core SMI Data Link In
0x37 | RFC_SMI_CL_OUT | RF Core SMI Command Link Out
0x38 | RFC_SMI_CL_IN | RF Core SMI Command Link In
| RW | 0x00

### TOP:IOC:IOCFG15

Address offset | 0x0000 003C
Physical address | 0x4008 103C | Instance | IOC
Description | Configuration of DIO15
Type | RW

Bits | Field Name | Description | Type | Reset
31 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0
30 | HYST_EN | 0: Input hysteresis disable 1: Input hysteresis enable | RW | 0
29 | IE | 0: Input disabled 1: Input enabled Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be ignored. | RW | 0
28:27 | WU_CFG | If DIO is configured GPIO or non-AON peripheral signals, i.e. PORT_ID 0x00 or >0x08: 00: No wake-up 01: No wake-up 10: Wakes up from shutdown if this pad is going low. 11: Wakes up from shutdown if this pad is going high. If IO is configured for AON peripheral signals or AUX ie. PORT_ID 0x01-0x08, this register only sets wakeup enable or not. 00, 01: Wakeup disabled 10, 11: Wakeup enabled Polarity is controlled from AON registers. Note:When the MSB is set, the IOC will deactivate the output enable for the DIO. | RW | 0x0
26:24 | IOMODE | IO Mode N/A for IO configured for AON periph. signals and AUX ie. PORT_ID 0x01-0x08 AUX has its own open_source/drain configuration. 0x2: Reserved. Undefined behavior. 0x3: Reserved. Undefined behavior.
Value | ENUM name | Description
0x0 | NORMAL | Normal input / output
0x1 | INV | Inverted input / ouput
0x4 | OPENDR | Open Drain, Normal input / output
0x5 | OPENDR_INV | Open Drain Inverted input / output
0x6 | OPENSRC | Open Source Normal input / output
0x7 | OPENSRC_INV | Open Source Inverted input / output
| RW | 0x0
23:21 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0
20 | Reserved |  | RW | 0
19 | Reserved |  | RW | 0
18 | EDGE_IRQ_EN | 0: No interrupt generation 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled) | RW | 0
17:16 | EDGE_DET | Enable generation of edge detection events on this IO
Value | ENUM name | Description
0x0 | NONE | No edge detection
0x1 | NEG | Negative edge detection
0x2 | POS | Positive edge detection
0x3 | BOTH | Positive and negative edge detection
| RW | 0x0
15 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0
14:13 | PULL_CTL | Pull control
Value | ENUM name | Description
0x1 | DWN | Pull down
0x2 | UP | Pull up
0x3 | DIS | No pull
| RW | 0x3
12 | SLEW_RED | 0: Normal slew rate 1: Enables reduced slew rate in output driver. | RW | 0
11:10 | IOCURR | Selects IO current in combination with IOSTR
Value | ENUM name | Description
0x0 | 2MA | 2 mA
0x1 | 4MA | 4 mA
0x2 | 4_8MA | 4 or 8 mA 8 mA if IO is double drive strength
| RW | 0x0
9:8 | IOSTR | Select drive strength IO
Value | ENUM name | Description
0x0 | AUTO | Automatic drive strength (2/4/8 mA@VDDS)
0x1 | MIN | Minimum drive strength (2/4/8 mA@3.3V)
0x2 | MED | Medium drive strength (2/4/8 mA@2.5V)
0x3 | MAX | Maximum drive strength (2/4/8 mA@1.8V)
| RW | 0x0
7:6 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0
5:0 | PORT_ID | Selects usage for DIO15
Value | ENUM name | Description
0x00 | GPIO | General Purpose IO
0x01 | AON_SCS | AON SPI-S SCS
0x02 | AON_SCK | AON SPI-S SCK
0x03 | AON_SDI | AON SPI-S SDI
0x04 | AON_SDO | AON SPI-S SDO
0x07 | AON_CLK32K | AON 32 KHz clock (SCLK_LF)
0x08 | AUX_IO | AUX IO
0x09 | SSI0_RX | SSI0 RX
0x0A | SSI0_TX | SSI0 TX
0x0B | SSI0_FSS | SSI0 FSS
0x0C | SSI0_CLK | SSI0 CLK
0x0D | I2C_MSSDA | I2C Data
0x0E | I2C_MSSCL | I2C Clock
0x0F | UART0_RX | UART0 RX
0x10 | UART0_TX | UART0 TX
0x11 | UART0_CTS | UART0 CTS
0x12 | UART0_RTS | UART0 RTS
0x17 | PORT_EVENT0 | PORT EVENT 0 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x18 | PORT_EVENT1 | PORT EVENT 1 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x19 | PORT_EVENT2 | PORT EVENT 2 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x1A | PORT_EVENT3 | PORT EVENT 3 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x1B | PORT_EVENT4 | PORT EVENT 4 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x1C | PORT_EVENT5 | PORT EVENT 5 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x1D | PORT_EVENT6 | PORT EVENT 6 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x1E | PORT_EVENT7 | PORT EVENT 7 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x20 | CPU_SWV | CPU SWV
0x21 | SSI1_RX | SSI1 RX
0x22 | SSI1_TX | SSI1 TX
0x23 | SSI1_FSS | SSI1 FSS
0x24 | SSI1_CLK | SSI1 CLK
0x25 | I2S_AD0 | I2S Data 0
0x26 | I2S_AD1 | I2S Data 1
0x27 | I2S_WCLK | I2S WCLK
0x28 | I2S_BCLK | I2S BCLK
0x29 | I2S_MCLK | I2S MCLK
0x2E | RFC_TRC | RF Core Trace
0x2F | RFC_GPO0 | RF Core Data Out 0
0x30 | RFC_GPO1 | RF Core Data Out 1
0x31 | RFC_GPO2 | RF Core Data Out 2
0x32 | RFC_GPO3 | RF Core Data Out 3
0x33 | RFC_GPI0 | RF Core Data In 0
0x34 | RFC_GPI1 | RF Core Data In 1
0x35 | RFC_SMI_DL_OUT | RF Core SMI Data Link Out
0x36 | RFC_SMI_DL_IN | RF Core SMI Data Link In
0x37 | RFC_SMI_CL_OUT | RF Core SMI Command Link Out
0x38 | RFC_SMI_CL_IN | RF Core SMI Command Link In
| RW | 0x00

### TOP:IOC:IOCFG16

Address offset | 0x0000 0040
Physical address | 0x4008 1040 | Instance | IOC
Description | Configuration of DIO16
Type | RW

Bits | Field Name | Description | Type | Reset
31 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0
30 | HYST_EN | 0: Input hysteresis disable 1: Input hysteresis enable | RW | 0
29 | IE | 0: Input disabled 1: Input enabled Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be ignored. | RW | 0
28:27 | WU_CFG | If DIO is configured GPIO or non-AON peripheral signals, i.e. PORT_ID 0x00 or >0x08: 00: No wake-up 01: No wake-up 10: Wakes up from shutdown if this pad is going low. 11: Wakes up from shutdown if this pad is going high. If IO is configured for AON peripheral signals or AUX ie. PORT_ID 0x01-0x08, this register only sets wakeup enable or not. 00, 01: Wakeup disabled 10, 11: Wakeup enabled Polarity is controlled from AON registers. Note:When the MSB is set, the IOC will deactivate the output enable for the DIO. | RW | 0x0
26:24 | IOMODE | IO Mode N/A for IO configured for AON periph. signals and AUX ie. PORT_ID 0x01-0x08 AUX has its own open_source/drain configuration. 0x2: Reserved. Undefined behavior. 0x3: Reserved. Undefined behavior.
Value | ENUM name | Description
0x0 | NORMAL | Normal input / output
0x1 | INV | Inverted input / ouput
0x4 | OPENDR | Open Drain, Normal input / output
0x5 | OPENDR_INV | Open Drain Inverted input / output
0x6 | OPENSRC | Open Source Normal input / output
0x7 | OPENSRC_INV | Open Source Inverted input / output
| RW | 0x0
23:21 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0
20 | Reserved |  | RW | 0
19 | TDO | 0: IO disabled as JTAG TDO 1: IO enabled as JTAG TDO | RW | 1
18 | EDGE_IRQ_EN | 0: No interrupt generation 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled) | RW | 0
17:16 | EDGE_DET | Enable generation of edge detection events on this IO
Value | ENUM name | Description
0x0 | NONE | No edge detection
0x1 | NEG | Negative edge detection
0x2 | POS | Positive edge detection
0x3 | BOTH | Positive and negative edge detection
| RW | 0x0
15 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0
14:13 | PULL_CTL | Pull control
Value | ENUM name | Description
0x1 | DWN | Pull down
0x2 | UP | Pull up
0x3 | DIS | No pull
| RW | 0x3
12 | SLEW_RED | 0: Normal slew rate 1: Enables reduced slew rate in output driver. | RW | 0
11:10 | IOCURR | Selects IO current in combination with IOSTR
Value | ENUM name | Description
0x0 | 2MA | 2 mA
0x1 | 4MA | 4 mA
0x2 | 4_8MA | 4 or 8 mA 8 mA if IO is double drive strength
| RW | 0x0
9:8 | IOSTR | Select drive strength IO
Value | ENUM name | Description
0x0 | AUTO | Automatic drive strength (2/4/8 mA@VDDS)
0x1 | MIN | Minimum drive strength (2/4/8 mA@3.3V)
0x2 | MED | Medium drive strength (2/4/8 mA@2.5V)
0x3 | MAX | Maximum drive strength (2/4/8 mA@1.8V)
| RW | 0x0
7:6 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0
5:0 | PORT_ID | Selects usage for DIO16
Value | ENUM name | Description
0x00 | GPIO | General Purpose IO
0x01 | AON_SCS | AON SPI-S SCS
0x02 | AON_SCK | AON SPI-S SCK
0x03 | AON_SDI | AON SPI-S SDI
0x04 | AON_SDO | AON SPI-S SDO
0x07 | AON_CLK32K | AON 32 KHz clock (SCLK_LF)
0x08 | AUX_IO | AUX IO
0x09 | SSI0_RX | SSI0 RX
0x0A | SSI0_TX | SSI0 TX
0x0B | SSI0_FSS | SSI0 FSS
0x0C | SSI0_CLK | SSI0 CLK
0x0D | I2C_MSSDA | I2C Data
0x0E | I2C_MSSCL | I2C Clock
0x0F | UART0_RX | UART0 RX
0x10 | UART0_TX | UART0 TX
0x11 | UART0_CTS | UART0 CTS
0x12 | UART0_RTS | UART0 RTS
0x17 | PORT_EVENT0 | PORT EVENT 0 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x18 | PORT_EVENT1 | PORT EVENT 1 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x19 | PORT_EVENT2 | PORT EVENT 2 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x1A | PORT_EVENT3 | PORT EVENT 3 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x1B | PORT_EVENT4 | PORT EVENT 4 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x1C | PORT_EVENT5 | PORT EVENT 5 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x1D | PORT_EVENT6 | PORT EVENT 6 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x1E | PORT_EVENT7 | PORT EVENT 7 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x20 | CPU_SWV | CPU SWV
0x21 | SSI1_RX | SSI1 RX
0x22 | SSI1_TX | SSI1 TX
0x23 | SSI1_FSS | SSI1 FSS
0x24 | SSI1_CLK | SSI1 CLK
0x25 | I2S_AD0 | I2S Data 0
0x26 | I2S_AD1 | I2S Data 1
0x27 | I2S_WCLK | I2S WCLK
0x28 | I2S_BCLK | I2S BCLK
0x29 | I2S_MCLK | I2S MCLK
0x2E | RFC_TRC | RF Core Trace
0x2F | RFC_GPO0 | RF Core Data Out 0
0x30 | RFC_GPO1 | RF Core Data Out 1
0x31 | RFC_GPO2 | RF Core Data Out 2
0x32 | RFC_GPO3 | RF Core Data Out 3
0x33 | RFC_GPI0 | RF Core Data In 0
0x34 | RFC_GPI1 | RF Core Data In 1
0x35 | RFC_SMI_DL_OUT | RF Core SMI Data Link Out
0x36 | RFC_SMI_DL_IN | RF Core SMI Data Link In
0x37 | RFC_SMI_CL_OUT | RF Core SMI Command Link Out
0x38 | RFC_SMI_CL_IN | RF Core SMI Command Link In
| RW | 0x00

### TOP:IOC:IOCFG17

Address offset | 0x0000 0044
Physical address | 0x4008 1044 | Instance | IOC
Description | Configuration of DIO17
Type | RW

Bits | Field Name | Description | Type | Reset
31 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0
30 | HYST_EN | 0: Input hysteresis disable 1: Input hysteresis enable | RW | 0
29 | IE | 0: Input disabled 1: Input enabled Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be ignored. | RW | 0
28:27 | WU_CFG | If DIO is configured GPIO or non-AON peripheral signals, i.e. PORT_ID 0x00 or >0x08: 00: No wake-up 01: No wake-up 10: Wakes up from shutdown if this pad is going low. 11: Wakes up from shutdown if this pad is going high. If IO is configured for AON peripheral signals or AUX ie. PORT_ID 0x01-0x08, this register only sets wakeup enable or not. 00, 01: Wakeup disabled 10, 11: Wakeup enabled Polarity is controlled from AON registers. Note:When the MSB is set, the IOC will deactivate the output enable for the DIO. | RW | 0x0
26:24 | IOMODE | IO Mode N/A for IO configured for AON periph. signals and AUX ie. PORT_ID 0x01-0x08 AUX has its own open_source/drain configuration. 0x2: Reserved. Undefined behavior. 0x3: Reserved. Undefined behavior.
Value | ENUM name | Description
0x0 | NORMAL | Normal input / output
0x1 | INV | Inverted input / ouput
0x4 | OPENDR | Open Drain, Normal input / output
0x5 | OPENDR_INV | Open Drain Inverted input / output
0x6 | OPENSRC | Open Source Normal input / output
0x7 | OPENSRC_INV | Open Source Inverted input / output
| RW | 0x0
23:21 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0
20 | TDI | 0: IO disabled as JTAG TDI 1: IO enabled as JTAG TDI | RW | 1
19 | Reserved |  | RW | 0
18 | EDGE_IRQ_EN | 0: No interrupt generation 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled) | RW | 0
17:16 | EDGE_DET | Enable generation of edge detection events on this IO
Value | ENUM name | Description
0x0 | NONE | No edge detection
0x1 | NEG | Negative edge detection
0x2 | POS | Positive edge detection
0x3 | BOTH | Positive and negative edge detection
| RW | 0x0
15 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0
14:13 | PULL_CTL | Pull control
Value | ENUM name | Description
0x1 | DWN | Pull down
0x2 | UP | Pull up
0x3 | DIS | No pull
| RW | 0x3
12 | SLEW_RED | 0: Normal slew rate 1: Enables reduced slew rate in output driver. | RW | 0
11:10 | IOCURR | Selects IO current in combination with IOSTR
Value | ENUM name | Description
0x0 | 2MA | 2 mA
0x1 | 4MA | 4 mA
0x2 | 4_8MA | 4 or 8 mA 8 mA if IO is double drive strength
| RW | 0x0
9:8 | IOSTR | Select drive strength IO
Value | ENUM name | Description
0x0 | AUTO | Automatic drive strength (2/4/8 mA@VDDS)
0x1 | MIN | Minimum drive strength (2/4/8 mA@3.3V)
0x2 | MED | Medium drive strength (2/4/8 mA@2.5V)
0x3 | MAX | Maximum drive strength (2/4/8 mA@1.8V)
| RW | 0x0
7:6 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0
5:0 | PORT_ID | Selects usage for DIO17
Value | ENUM name | Description
0x00 | GPIO | General Purpose IO
0x01 | AON_SCS | AON SPI-S SCS
0x02 | AON_SCK | AON SPI-S SCK
0x03 | AON_SDI | AON SPI-S SDI
0x04 | AON_SDO | AON SPI-S SDO
0x07 | AON_CLK32K | AON 32 KHz clock (SCLK_LF)
0x08 | AUX_IO | AUX IO
0x09 | SSI0_RX | SSI0 RX
0x0A | SSI0_TX | SSI0 TX
0x0B | SSI0_FSS | SSI0 FSS
0x0C | SSI0_CLK | SSI0 CLK
0x0D | I2C_MSSDA | I2C Data
0x0E | I2C_MSSCL | I2C Clock
0x0F | UART0_RX | UART0 RX
0x10 | UART0_TX | UART0 TX
0x11 | UART0_CTS | UART0 CTS
0x12 | UART0_RTS | UART0 RTS
0x17 | PORT_EVENT0 | PORT EVENT 0 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x18 | PORT_EVENT1 | PORT EVENT 1 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x19 | PORT_EVENT2 | PORT EVENT 2 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x1A | PORT_EVENT3 | PORT EVENT 3 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x1B | PORT_EVENT4 | PORT EVENT 4 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x1C | PORT_EVENT5 | PORT EVENT 5 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x1D | PORT_EVENT6 | PORT EVENT 6 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x1E | PORT_EVENT7 | PORT EVENT 7 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x20 | CPU_SWV | CPU SWV
0x21 | SSI1_RX | SSI1 RX
0x22 | SSI1_TX | SSI1 TX
0x23 | SSI1_FSS | SSI1 FSS
0x24 | SSI1_CLK | SSI1 CLK
0x25 | I2S_AD0 | I2S Data 0
0x26 | I2S_AD1 | I2S Data 1
0x27 | I2S_WCLK | I2S WCLK
0x28 | I2S_BCLK | I2S BCLK
0x29 | I2S_MCLK | I2S MCLK
0x2E | RFC_TRC | RF Core Trace
0x2F | RFC_GPO0 | RF Core Data Out 0
0x30 | RFC_GPO1 | RF Core Data Out 1
0x31 | RFC_GPO2 | RF Core Data Out 2
0x32 | RFC_GPO3 | RF Core Data Out 3
0x33 | RFC_GPI0 | RF Core Data In 0
0x34 | RFC_GPI1 | RF Core Data In 1
0x35 | RFC_SMI_DL_OUT | RF Core SMI Data Link Out
0x36 | RFC_SMI_DL_IN | RF Core SMI Data Link In
0x37 | RFC_SMI_CL_OUT | RF Core SMI Command Link Out
0x38 | RFC_SMI_CL_IN | RF Core SMI Command Link In
| RW | 0x00

### TOP:IOC:IOCFG18

Address offset | 0x0000 0048
Physical address | 0x4008 1048 | Instance | IOC
Description | Configuration of DIO18
Type | RW

Bits | Field Name | Description | Type | Reset
31 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0
30 | HYST_EN | 0: Input hysteresis disable 1: Input hysteresis enable | RW | 0
29 | IE | 0: Input disabled 1: Input enabled Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be ignored. | RW | 0
28:27 | WU_CFG | If DIO is configured GPIO or non-AON peripheral signals, i.e. PORT_ID 0x00 or >0x08: 00: No wake-up 01: No wake-up 10: Wakes up from shutdown if this pad is going low. 11: Wakes up from shutdown if this pad is going high. If IO is configured for AON peripheral signals or AUX ie. PORT_ID 0x01-0x08, this register only sets wakeup enable or not. 00, 01: Wakeup disabled 10, 11: Wakeup enabled Polarity is controlled from AON registers. Note:When the MSB is set, the IOC will deactivate the output enable for the DIO. | RW | 0x0
26:24 | IOMODE | IO Mode N/A for IO configured for AON periph. signals and AUX ie. PORT_ID 0x01-0x08 AUX has its own open_source/drain configuration. 0x2: Reserved. Undefined behavior. 0x3: Reserved. Undefined behavior.
Value | ENUM name | Description
0x0 | NORMAL | Normal input / output
0x1 | INV | Inverted input / ouput
0x4 | OPENDR | Open Drain, Normal input / output
0x5 | OPENDR_INV | Open Drain Inverted input / output
0x6 | OPENSRC | Open Source Normal input / output
0x7 | OPENSRC_INV | Open Source Inverted input / output
| RW | 0x0
23:21 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0
20 | Reserved |  | RW | 0
19 | Reserved |  | RW | 0
18 | EDGE_IRQ_EN | 0: No interrupt generation 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled) | RW | 0
17:16 | EDGE_DET | Enable generation of edge detection events on this IO
Value | ENUM name | Description
0x0 | NONE | No edge detection
0x1 | NEG | Negative edge detection
0x2 | POS | Positive edge detection
0x3 | BOTH | Positive and negative edge detection
| RW | 0x0
15 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0
14:13 | PULL_CTL | Pull control
Value | ENUM name | Description
0x1 | DWN | Pull down
0x2 | UP | Pull up
0x3 | DIS | No pull
| RW | 0x3
12 | SLEW_RED | 0: Normal slew rate 1: Enables reduced slew rate in output driver. | RW | 0
11:10 | IOCURR | Selects IO current in combination with IOSTR
Value | ENUM name | Description
0x0 | 2MA | 2 mA
0x1 | 4MA | 4 mA
0x2 | 4_8MA | 4 or 8 mA 8 mA if IO is double drive strength
| RW | 0x0
9:8 | IOSTR | Select drive strength IO
Value | ENUM name | Description
0x0 | AUTO | Automatic drive strength (2/4/8 mA@VDDS)
0x1 | MIN | Minimum drive strength (2/4/8 mA@3.3V)
0x2 | MED | Medium drive strength (2/4/8 mA@2.5V)
0x3 | MAX | Maximum drive strength (2/4/8 mA@1.8V)
| RW | 0x0
7:6 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0
5:0 | PORT_ID | Selects usage for DIO18
Value | ENUM name | Description
0x00 | GPIO | General Purpose IO
0x01 | AON_SCS | AON SPI-S SCS
0x02 | AON_SCK | AON SPI-S SCK
0x03 | AON_SDI | AON SPI-S SDI
0x04 | AON_SDO | AON SPI-S SDO
0x07 | AON_CLK32K | AON 32 KHz clock (SCLK_LF)
0x08 | AUX_IO | AUX IO
0x09 | SSI0_RX | SSI0 RX
0x0A | SSI0_TX | SSI0 TX
0x0B | SSI0_FSS | SSI0 FSS
0x0C | SSI0_CLK | SSI0 CLK
0x0D | I2C_MSSDA | I2C Data
0x0E | I2C_MSSCL | I2C Clock
0x0F | UART0_RX | UART0 RX
0x10 | UART0_TX | UART0 TX
0x11 | UART0_CTS | UART0 CTS
0x12 | UART0_RTS | UART0 RTS
0x17 | PORT_EVENT0 | PORT EVENT 0 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x18 | PORT_EVENT1 | PORT EVENT 1 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x19 | PORT_EVENT2 | PORT EVENT 2 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x1A | PORT_EVENT3 | PORT EVENT 3 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x1B | PORT_EVENT4 | PORT EVENT 4 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x1C | PORT_EVENT5 | PORT EVENT 5 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x1D | PORT_EVENT6 | PORT EVENT 6 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x1E | PORT_EVENT7 | PORT EVENT 7 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x20 | CPU_SWV | CPU SWV
0x21 | SSI1_RX | SSI1 RX
0x22 | SSI1_TX | SSI1 TX
0x23 | SSI1_FSS | SSI1 FSS
0x24 | SSI1_CLK | SSI1 CLK
0x25 | I2S_AD0 | I2S Data 0
0x26 | I2S_AD1 | I2S Data 1
0x27 | I2S_WCLK | I2S WCLK
0x28 | I2S_BCLK | I2S BCLK
0x29 | I2S_MCLK | I2S MCLK
0x2E | RFC_TRC | RF Core Trace
0x2F | RFC_GPO0 | RF Core Data Out 0
0x30 | RFC_GPO1 | RF Core Data Out 1
0x31 | RFC_GPO2 | RF Core Data Out 2
0x32 | RFC_GPO3 | RF Core Data Out 3
0x33 | RFC_GPI0 | RF Core Data In 0
0x34 | RFC_GPI1 | RF Core Data In 1
0x35 | RFC_SMI_DL_OUT | RF Core SMI Data Link Out
0x36 | RFC_SMI_DL_IN | RF Core SMI Data Link In
0x37 | RFC_SMI_CL_OUT | RF Core SMI Command Link Out
0x38 | RFC_SMI_CL_IN | RF Core SMI Command Link In
| RW | 0x00

### TOP:IOC:IOCFG19

Address offset | 0x0000 004C
Physical address | 0x4008 104C | Instance | IOC
Description | Configuration of DIO19
Type | RW

Bits | Field Name | Description | Type | Reset
31 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0
30 | HYST_EN | 0: Input hysteresis disable 1: Input hysteresis enable | RW | 0
29 | IE | 0: Input disabled 1: Input enabled Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be ignored. | RW | 0
28:27 | WU_CFG | If DIO is configured GPIO or non-AON peripheral signals, i.e. PORT_ID 0x00 or >0x08: 00: No wake-up 01: No wake-up 10: Wakes up from shutdown if this pad is going low. 11: Wakes up from shutdown if this pad is going high. If IO is configured for AON peripheral signals or AUX ie. PORT_ID 0x01-0x08, this register only sets wakeup enable or not. 00, 01: Wakeup disabled 10, 11: Wakeup enabled Polarity is controlled from AON registers. Note:When the MSB is set, the IOC will deactivate the output enable for the DIO. | RW | 0x0
26:24 | IOMODE | IO Mode N/A for IO configured for AON periph. signals and AUX ie. PORT_ID 0x01-0x08 AUX has its own open_source/drain configuration. 0x2: Reserved. Undefined behavior. 0x3: Reserved. Undefined behavior.
Value | ENUM name | Description
0x0 | NORMAL | Normal input / output
0x1 | INV | Inverted input / ouput
0x4 | OPENDR | Open Drain, Normal input / output
0x5 | OPENDR_INV | Open Drain Inverted input / output
0x6 | OPENSRC | Open Source Normal input / output
0x7 | OPENSRC_INV | Open Source Inverted input / output
| RW | 0x0
23:21 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0
20 | Reserved |  | RW | 0
19 | Reserved |  | RW | 0
18 | EDGE_IRQ_EN | 0: No interrupt generation 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled) | RW | 0
17:16 | EDGE_DET | Enable generation of edge detection events on this IO
Value | ENUM name | Description
0x0 | NONE | No edge detection
0x1 | NEG | Negative edge detection
0x2 | POS | Positive edge detection
0x3 | BOTH | Positive and negative edge detection
| RW | 0x0
15 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0
14:13 | PULL_CTL | Pull control
Value | ENUM name | Description
0x1 | DWN | Pull down
0x2 | UP | Pull up
0x3 | DIS | No pull
| RW | 0x3
12 | SLEW_RED | 0: Normal slew rate 1: Enables reduced slew rate in output driver. | RW | 0
11:10 | IOCURR | Selects IO current in combination with IOSTR
Value | ENUM name | Description
0x0 | 2MA | 2 mA
0x1 | 4MA | 4 mA
0x2 | 4_8MA | 4 or 8 mA 8 mA if IO is double drive strength
| RW | 0x0
9:8 | IOSTR | Select drive strength IO
Value | ENUM name | Description
0x0 | AUTO | Automatic drive strength (2/4/8 mA@VDDS)
0x1 | MIN | Minimum drive strength (2/4/8 mA@3.3V)
0x2 | MED | Medium drive strength (2/4/8 mA@2.5V)
0x3 | MAX | Maximum drive strength (2/4/8 mA@1.8V)
| RW | 0x0
7:6 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0
5:0 | PORT_ID | Selects usage for DIO19
Value | ENUM name | Description
0x00 | GPIO | General Purpose IO
0x01 | AON_SCS | AON SPI-S SCS
0x02 | AON_SCK | AON SPI-S SCK
0x03 | AON_SDI | AON SPI-S SDI
0x04 | AON_SDO | AON SPI-S SDO
0x07 | AON_CLK32K | AON 32 KHz clock (SCLK_LF)
0x08 | AUX_IO | AUX IO
0x09 | SSI0_RX | SSI0 RX
0x0A | SSI0_TX | SSI0 TX
0x0B | SSI0_FSS | SSI0 FSS
0x0C | SSI0_CLK | SSI0 CLK
0x0D | I2C_MSSDA | I2C Data
0x0E | I2C_MSSCL | I2C Clock
0x0F | UART0_RX | UART0 RX
0x10 | UART0_TX | UART0 TX
0x11 | UART0_CTS | UART0 CTS
0x12 | UART0_RTS | UART0 RTS
0x17 | PORT_EVENT0 | PORT EVENT 0 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x18 | PORT_EVENT1 | PORT EVENT 1 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x19 | PORT_EVENT2 | PORT EVENT 2 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x1A | PORT_EVENT3 | PORT EVENT 3 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x1B | PORT_EVENT4 | PORT EVENT 4 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x1C | PORT_EVENT5 | PORT EVENT 5 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x1D | PORT_EVENT6 | PORT EVENT 6 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x1E | PORT_EVENT7 | PORT EVENT 7 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x20 | CPU_SWV | CPU SWV
0x21 | SSI1_RX | SSI1 RX
0x22 | SSI1_TX | SSI1 TX
0x23 | SSI1_FSS | SSI1 FSS
0x24 | SSI1_CLK | SSI1 CLK
0x25 | I2S_AD0 | I2S Data 0
0x26 | I2S_AD1 | I2S Data 1
0x27 | I2S_WCLK | I2S WCLK
0x28 | I2S_BCLK | I2S BCLK
0x29 | I2S_MCLK | I2S MCLK
0x2E | RFC_TRC | RF Core Trace
0x2F | RFC_GPO0 | RF Core Data Out 0
0x30 | RFC_GPO1 | RF Core Data Out 1
0x31 | RFC_GPO2 | RF Core Data Out 2
0x32 | RFC_GPO3 | RF Core Data Out 3
0x33 | RFC_GPI0 | RF Core Data In 0
0x34 | RFC_GPI1 | RF Core Data In 1
0x35 | RFC_SMI_DL_OUT | RF Core SMI Data Link Out
0x36 | RFC_SMI_DL_IN | RF Core SMI Data Link In
0x37 | RFC_SMI_CL_OUT | RF Core SMI Command Link Out
0x38 | RFC_SMI_CL_IN | RF Core SMI Command Link In
| RW | 0x00

### TOP:IOC:IOCFG20

Address offset | 0x0000 0050
Physical address | 0x4008 1050 | Instance | IOC
Description | Configuration of DIO20
Type | RW

Bits | Field Name | Description | Type | Reset
31 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0
30 | HYST_EN | 0: Input hysteresis disable 1: Input hysteresis enable | RW | 0
29 | IE | 0: Input disabled 1: Input enabled Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be ignored. | RW | 0
28:27 | WU_CFG | If DIO is configured GPIO or non-AON peripheral signals, i.e. PORT_ID 0x00 or >0x08: 00: No wake-up 01: No wake-up 10: Wakes up from shutdown if this pad is going low. 11: Wakes up from shutdown if this pad is going high. If IO is configured for AON peripheral signals or AUX ie. PORT_ID 0x01-0x08, this register only sets wakeup enable or not. 00, 01: Wakeup disabled 10, 11: Wakeup enabled Polarity is controlled from AON registers. Note:When the MSB is set, the IOC will deactivate the output enable for the DIO. | RW | 0x0
26:24 | IOMODE | IO Mode N/A for IO configured for AON periph. signals and AUX ie. PORT_ID 0x01-0x08 AUX has its own open_source/drain configuration. 0x2: Reserved. Undefined behavior. 0x3: Reserved. Undefined behavior.
Value | ENUM name | Description
0x0 | NORMAL | Normal input / output
0x1 | INV | Inverted input / ouput
0x4 | OPENDR | Open Drain, Normal input / output
0x5 | OPENDR_INV | Open Drain Inverted input / output
0x6 | OPENSRC | Open Source Normal input / output
0x7 | OPENSRC_INV | Open Source Inverted input / output
| RW | 0x0
23:21 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0
20 | Reserved |  | RW | 0
19 | Reserved |  | RW | 0
18 | EDGE_IRQ_EN | 0: No interrupt generation 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled) | RW | 0
17:16 | EDGE_DET | Enable generation of edge detection events on this IO
Value | ENUM name | Description
0x0 | NONE | No edge detection
0x1 | NEG | Negative edge detection
0x2 | POS | Positive edge detection
0x3 | BOTH | Positive and negative edge detection
| RW | 0x0
15 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0
14:13 | PULL_CTL | Pull control
Value | ENUM name | Description
0x1 | DWN | Pull down
0x2 | UP | Pull up
0x3 | DIS | No pull
| RW | 0x3
12 | SLEW_RED | 0: Normal slew rate 1: Enables reduced slew rate in output driver. | RW | 0
11:10 | IOCURR | Selects IO current in combination with IOSTR
Value | ENUM name | Description
0x0 | 2MA | 2 mA
0x1 | 4MA | 4 mA
0x2 | 4_8MA | 4 or 8 mA 8 mA if IO is double drive strength
| RW | 0x0
9:8 | IOSTR | Select drive strength IO
Value | ENUM name | Description
0x0 | AUTO | Automatic drive strength (2/4/8 mA@VDDS)
0x1 | MIN | Minimum drive strength (2/4/8 mA@3.3V)
0x2 | MED | Medium drive strength (2/4/8 mA@2.5V)
0x3 | MAX | Maximum drive strength (2/4/8 mA@1.8V)
| RW | 0x0
7:6 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0
5:0 | PORT_ID | Selects usage for DIO20
Value | ENUM name | Description
0x00 | GPIO | General Purpose IO
0x01 | AON_SCS | AON SPI-S SCS
0x02 | AON_SCK | AON SPI-S SCK
0x03 | AON_SDI | AON SPI-S SDI
0x04 | AON_SDO | AON SPI-S SDO
0x07 | AON_CLK32K | AON 32 KHz clock (SCLK_LF)
0x08 | AUX_IO | AUX IO
0x09 | SSI0_RX | SSI0 RX
0x0A | SSI0_TX | SSI0 TX
0x0B | SSI0_FSS | SSI0 FSS
0x0C | SSI0_CLK | SSI0 CLK
0x0D | I2C_MSSDA | I2C Data
0x0E | I2C_MSSCL | I2C Clock
0x0F | UART0_RX | UART0 RX
0x10 | UART0_TX | UART0 TX
0x11 | UART0_CTS | UART0 CTS
0x12 | UART0_RTS | UART0 RTS
0x17 | PORT_EVENT0 | PORT EVENT 0 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x18 | PORT_EVENT1 | PORT EVENT 1 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x19 | PORT_EVENT2 | PORT EVENT 2 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x1A | PORT_EVENT3 | PORT EVENT 3 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x1B | PORT_EVENT4 | PORT EVENT 4 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x1C | PORT_EVENT5 | PORT EVENT 5 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x1D | PORT_EVENT6 | PORT EVENT 6 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x1E | PORT_EVENT7 | PORT EVENT 7 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x20 | CPU_SWV | CPU SWV
0x21 | SSI1_RX | SSI1 RX
0x22 | SSI1_TX | SSI1 TX
0x23 | SSI1_FSS | SSI1 FSS
0x24 | SSI1_CLK | SSI1 CLK
0x25 | I2S_AD0 | I2S Data 0
0x26 | I2S_AD1 | I2S Data 1
0x27 | I2S_WCLK | I2S WCLK
0x28 | I2S_BCLK | I2S BCLK
0x29 | I2S_MCLK | I2S MCLK
0x2E | RFC_TRC | RF Core Trace
0x2F | RFC_GPO0 | RF Core Data Out 0
0x30 | RFC_GPO1 | RF Core Data Out 1
0x31 | RFC_GPO2 | RF Core Data Out 2
0x32 | RFC_GPO3 | RF Core Data Out 3
0x33 | RFC_GPI0 | RF Core Data In 0
0x34 | RFC_GPI1 | RF Core Data In 1
0x35 | RFC_SMI_DL_OUT | RF Core SMI Data Link Out
0x36 | RFC_SMI_DL_IN | RF Core SMI Data Link In
0x37 | RFC_SMI_CL_OUT | RF Core SMI Command Link Out
0x38 | RFC_SMI_CL_IN | RF Core SMI Command Link In
| RW | 0x00

### TOP:IOC:IOCFG21

Address offset | 0x0000 0054
Physical address | 0x4008 1054 | Instance | IOC
Description | Configuration of DIO21
Type | RW

Bits | Field Name | Description | Type | Reset
31 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0
30 | HYST_EN | 0: Input hysteresis disable 1: Input hysteresis enable | RW | 0
29 | IE | 0: Input disabled 1: Input enabled Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be ignored. | RW | 0
28:27 | WU_CFG | If DIO is configured GPIO or non-AON peripheral signals, i.e. PORT_ID 0x00 or >0x08: 00: No wake-up 01: No wake-up 10: Wakes up from shutdown if this pad is going low. 11: Wakes up from shutdown if this pad is going high. If IO is configured for AON peripheral signals or AUX ie. PORT_ID 0x01-0x08, this register only sets wakeup enable or not. 00, 01: Wakeup disabled 10, 11: Wakeup enabled Polarity is controlled from AON registers. Note:When the MSB is set, the IOC will deactivate the output enable for the DIO. | RW | 0x0
26:24 | IOMODE | IO Mode N/A for IO configured for AON periph. signals and AUX ie. PORT_ID 0x01-0x08 AUX has its own open_source/drain configuration. 0x2: Reserved. Undefined behavior. 0x3: Reserved. Undefined behavior.
Value | ENUM name | Description
0x0 | NORMAL | Normal input / output
0x1 | INV | Inverted input / ouput
0x4 | OPENDR | Open Drain, Normal input / output
0x5 | OPENDR_INV | Open Drain Inverted input / output
0x6 | OPENSRC | Open Source Normal input / output
0x7 | OPENSRC_INV | Open Source Inverted input / output
| RW | 0x0
23:21 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0
20 | Reserved |  | RW | 0
19 | Reserved |  | RW | 0
18 | EDGE_IRQ_EN | 0: No interrupt generation 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled) | RW | 0
17:16 | EDGE_DET | Enable generation of edge detection events on this IO
Value | ENUM name | Description
0x0 | NONE | No edge detection
0x1 | NEG | Negative edge detection
0x2 | POS | Positive edge detection
0x3 | BOTH | Positive and negative edge detection
| RW | 0x0
15 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0
14:13 | PULL_CTL | Pull control
Value | ENUM name | Description
0x1 | DWN | Pull down
0x2 | UP | Pull up
0x3 | DIS | No pull
| RW | 0x3
12 | SLEW_RED | 0: Normal slew rate 1: Enables reduced slew rate in output driver. | RW | 0
11:10 | IOCURR | Selects IO current in combination with IOSTR
Value | ENUM name | Description
0x0 | 2MA | 2 mA
0x1 | 4MA | 4 mA
0x2 | 4_8MA | 4 or 8 mA 8 mA if IO is double drive strength
| RW | 0x0
9:8 | IOSTR | Select drive strength IO
Value | ENUM name | Description
0x0 | AUTO | Automatic drive strength (2/4/8 mA@VDDS)
0x1 | MIN | Minimum drive strength (2/4/8 mA@3.3V)
0x2 | MED | Medium drive strength (2/4/8 mA@2.5V)
0x3 | MAX | Maximum drive strength (2/4/8 mA@1.8V)
| RW | 0x0
7:6 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0
5:0 | PORT_ID | Selects usage for DIO21
Value | ENUM name | Description
0x00 | GPIO | General Purpose IO
0x01 | AON_SCS | AON SPI-S SCS
0x02 | AON_SCK | AON SPI-S SCK
0x03 | AON_SDI | AON SPI-S SDI
0x04 | AON_SDO | AON SPI-S SDO
0x07 | AON_CLK32K | AON 32 KHz clock (SCLK_LF)
0x08 | AUX_IO | AUX IO
0x09 | SSI0_RX | SSI0 RX
0x0A | SSI0_TX | SSI0 TX
0x0B | SSI0_FSS | SSI0 FSS
0x0C | SSI0_CLK | SSI0 CLK
0x0D | I2C_MSSDA | I2C Data
0x0E | I2C_MSSCL | I2C Clock
0x0F | UART0_RX | UART0 RX
0x10 | UART0_TX | UART0 TX
0x11 | UART0_CTS | UART0 CTS
0x12 | UART0_RTS | UART0 RTS
0x17 | PORT_EVENT0 | PORT EVENT 0 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x18 | PORT_EVENT1 | PORT EVENT 1 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x19 | PORT_EVENT2 | PORT EVENT 2 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x1A | PORT_EVENT3 | PORT EVENT 3 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x1B | PORT_EVENT4 | PORT EVENT 4 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x1C | PORT_EVENT5 | PORT EVENT 5 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x1D | PORT_EVENT6 | PORT EVENT 6 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x1E | PORT_EVENT7 | PORT EVENT 7 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x20 | CPU_SWV | CPU SWV
0x21 | SSI1_RX | SSI1 RX
0x22 | SSI1_TX | SSI1 TX
0x23 | SSI1_FSS | SSI1 FSS
0x24 | SSI1_CLK | SSI1 CLK
0x25 | I2S_AD0 | I2S Data 0
0x26 | I2S_AD1 | I2S Data 1
0x27 | I2S_WCLK | I2S WCLK
0x28 | I2S_BCLK | I2S BCLK
0x29 | I2S_MCLK | I2S MCLK
0x2E | RFC_TRC | RF Core Trace
0x2F | RFC_GPO0 | RF Core Data Out 0
0x30 | RFC_GPO1 | RF Core Data Out 1
0x31 | RFC_GPO2 | RF Core Data Out 2
0x32 | RFC_GPO3 | RF Core Data Out 3
0x33 | RFC_GPI0 | RF Core Data In 0
0x34 | RFC_GPI1 | RF Core Data In 1
0x35 | RFC_SMI_DL_OUT | RF Core SMI Data Link Out
0x36 | RFC_SMI_DL_IN | RF Core SMI Data Link In
0x37 | RFC_SMI_CL_OUT | RF Core SMI Command Link Out
0x38 | RFC_SMI_CL_IN | RF Core SMI Command Link In
| RW | 0x00

### TOP:IOC:IOCFG22

Address offset | 0x0000 0058
Physical address | 0x4008 1058 | Instance | IOC
Description | Configuration of DIO22
Type | RW

Bits | Field Name | Description | Type | Reset
31 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0
30 | HYST_EN | 0: Input hysteresis disable 1: Input hysteresis enable | RW | 0
29 | IE | 0: Input disabled 1: Input enabled Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be ignored. | RW | 0
28:27 | WU_CFG | If DIO is configured GPIO or non-AON peripheral signals, i.e. PORT_ID 0x00 or >0x08: 00: No wake-up 01: No wake-up 10: Wakes up from shutdown if this pad is going low. 11: Wakes up from shutdown if this pad is going high. If IO is configured for AON peripheral signals or AUX ie. PORT_ID 0x01-0x08, this register only sets wakeup enable or not. 00, 01: Wakeup disabled 10, 11: Wakeup enabled Polarity is controlled from AON registers. Note:When the MSB is set, the IOC will deactivate the output enable for the DIO. | RW | 0x0
26:24 | IOMODE | IO Mode N/A for IO configured for AON periph. signals and AUX ie. PORT_ID 0x01-0x08 AUX has its own open_source/drain configuration. 0x2: Reserved. Undefined behavior. 0x3: Reserved. Undefined behavior.
Value | ENUM name | Description
0x0 | NORMAL | Normal input / output
0x1 | INV | Inverted input / ouput
0x4 | OPENDR | Open Drain, Normal input / output
0x5 | OPENDR_INV | Open Drain Inverted input / output
0x6 | OPENSRC | Open Source Normal input / output
0x7 | OPENSRC_INV | Open Source Inverted input / output
| RW | 0x0
23:21 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0
20 | Reserved |  | RW | 0
19 | Reserved |  | RW | 0
18 | EDGE_IRQ_EN | 0: No interrupt generation 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled) | RW | 0
17:16 | EDGE_DET | Enable generation of edge detection events on this IO
Value | ENUM name | Description
0x0 | NONE | No edge detection
0x1 | NEG | Negative edge detection
0x2 | POS | Positive edge detection
0x3 | BOTH | Positive and negative edge detection
| RW | 0x0
15 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0
14:13 | PULL_CTL | Pull control
Value | ENUM name | Description
0x1 | DWN | Pull down
0x2 | UP | Pull up
0x3 | DIS | No pull
| RW | 0x3
12 | SLEW_RED | 0: Normal slew rate 1: Enables reduced slew rate in output driver. | RW | 0
11:10 | IOCURR | Selects IO current in combination with IOSTR
Value | ENUM name | Description
0x0 | 2MA | 2 mA
0x1 | 4MA | 4 mA
0x2 | 4_8MA | 4 or 8 mA 8 mA if IO is double drive strength
| RW | 0x0
9:8 | IOSTR | Select drive strength IO
Value | ENUM name | Description
0x0 | AUTO | Automatic drive strength (2/4/8 mA@VDDS)
0x1 | MIN | Minimum drive strength (2/4/8 mA@3.3V)
0x2 | MED | Medium drive strength (2/4/8 mA@2.5V)
0x3 | MAX | Maximum drive strength (2/4/8 mA@1.8V)
| RW | 0x0
7:6 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0
5:0 | PORT_ID | Selects usage for DIO22
Value | ENUM name | Description
0x00 | GPIO | General Purpose IO
0x01 | AON_SCS | AON SPI-S SCS
0x02 | AON_SCK | AON SPI-S SCK
0x03 | AON_SDI | AON SPI-S SDI
0x04 | AON_SDO | AON SPI-S SDO
0x07 | AON_CLK32K | AON 32 KHz clock (SCLK_LF)
0x08 | AUX_IO | AUX IO
0x09 | SSI0_RX | SSI0 RX
0x0A | SSI0_TX | SSI0 TX
0x0B | SSI0_FSS | SSI0 FSS
0x0C | SSI0_CLK | SSI0 CLK
0x0D | I2C_MSSDA | I2C Data
0x0E | I2C_MSSCL | I2C Clock
0x0F | UART0_RX | UART0 RX
0x10 | UART0_TX | UART0 TX
0x11 | UART0_CTS | UART0 CTS
0x12 | UART0_RTS | UART0 RTS
0x17 | PORT_EVENT0 | PORT EVENT 0 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x18 | PORT_EVENT1 | PORT EVENT 1 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x19 | PORT_EVENT2 | PORT EVENT 2 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x1A | PORT_EVENT3 | PORT EVENT 3 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x1B | PORT_EVENT4 | PORT EVENT 4 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x1C | PORT_EVENT5 | PORT EVENT 5 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x1D | PORT_EVENT6 | PORT EVENT 6 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x1E | PORT_EVENT7 | PORT EVENT 7 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x20 | CPU_SWV | CPU SWV
0x21 | SSI1_RX | SSI1 RX
0x22 | SSI1_TX | SSI1 TX
0x23 | SSI1_FSS | SSI1 FSS
0x24 | SSI1_CLK | SSI1 CLK
0x25 | I2S_AD0 | I2S Data 0
0x26 | I2S_AD1 | I2S Data 1
0x27 | I2S_WCLK | I2S WCLK
0x28 | I2S_BCLK | I2S BCLK
0x29 | I2S_MCLK | I2S MCLK
0x2E | RFC_TRC | RF Core Trace
0x2F | RFC_GPO0 | RF Core Data Out 0
0x30 | RFC_GPO1 | RF Core Data Out 1
0x31 | RFC_GPO2 | RF Core Data Out 2
0x32 | RFC_GPO3 | RF Core Data Out 3
0x33 | RFC_GPI0 | RF Core Data In 0
0x34 | RFC_GPI1 | RF Core Data In 1
0x35 | RFC_SMI_DL_OUT | RF Core SMI Data Link Out
0x36 | RFC_SMI_DL_IN | RF Core SMI Data Link In
0x37 | RFC_SMI_CL_OUT | RF Core SMI Command Link Out
0x38 | RFC_SMI_CL_IN | RF Core SMI Command Link In
| RW | 0x00

### TOP:IOC:IOCFG23

Address offset | 0x0000 005C
Physical address | 0x4008 105C | Instance | IOC
Description | Configuration of DIO23
Type | RW

Bits | Field Name | Description | Type | Reset
31 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0
30 | HYST_EN | 0: Input hysteresis disable 1: Input hysteresis enable | RW | 0
29 | IE | 0: Input disabled 1: Input enabled Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be ignored. | RW | 0
28:27 | WU_CFG | If DIO is configured GPIO or non-AON peripheral signals, i.e. PORT_ID 0x00 or >0x08: 00: No wake-up 01: No wake-up 10: Wakes up from shutdown if this pad is going low. 11: Wakes up from shutdown if this pad is going high. If IO is configured for AON peripheral signals or AUX ie. PORT_ID 0x01-0x08, this register only sets wakeup enable or not. 00, 01: Wakeup disabled 10, 11: Wakeup enabled Polarity is controlled from AON registers. Note:When the MSB is set, the IOC will deactivate the output enable for the DIO. | RW | 0x0
26:24 | IOMODE | IO Mode N/A for IO configured for AON periph. signals and AUX ie. PORT_ID 0x01-0x08 AUX has its own open_source/drain configuration. 0x2: Reserved. Undefined behavior. 0x3: Reserved. Undefined behavior.
Value | ENUM name | Description
0x0 | NORMAL | Normal input / output
0x1 | INV | Inverted input / ouput
0x4 | OPENDR | Open Drain, Normal input / output
0x5 | OPENDR_INV | Open Drain Inverted input / output
0x6 | OPENSRC | Open Source Normal input / output
0x7 | OPENSRC_INV | Open Source Inverted input / output
| RW | 0x0
23:21 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0
20 | Reserved |  | RW | 0
19 | Reserved |  | RW | 0
18 | EDGE_IRQ_EN | 0: No interrupt generation 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled) | RW | 0
17:16 | EDGE_DET | Enable generation of edge detection events on this IO
Value | ENUM name | Description
0x0 | NONE | No edge detection
0x1 | NEG | Negative edge detection
0x2 | POS | Positive edge detection
0x3 | BOTH | Positive and negative edge detection
| RW | 0x0
15 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0
14:13 | PULL_CTL | Pull control
Value | ENUM name | Description
0x1 | DWN | Pull down
0x2 | UP | Pull up
0x3 | DIS | No pull
| RW | 0x3
12 | SLEW_RED | 0: Normal slew rate 1: Enables reduced slew rate in output driver. | RW | 0
11:10 | IOCURR | Selects IO current in combination with IOSTR
Value | ENUM name | Description
0x0 | 2MA | 2 mA
0x1 | 4MA | 4 mA
0x2 | 4_8MA | 4 or 8 mA 8 mA if IO is double drive strength
| RW | 0x0
9:8 | IOSTR | Select drive strength IO
Value | ENUM name | Description
0x0 | AUTO | Automatic drive strength (2/4/8 mA@VDDS)
0x1 | MIN | Minimum drive strength (2/4/8 mA@3.3V)
0x2 | MED | Medium drive strength (2/4/8 mA@2.5V)
0x3 | MAX | Maximum drive strength (2/4/8 mA@1.8V)
| RW | 0x0
7:6 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0
5:0 | PORT_ID | Selects usage for DIO23
Value | ENUM name | Description
0x00 | GPIO | General Purpose IO
0x01 | AON_SCS | AON SPI-S SCS
0x02 | AON_SCK | AON SPI-S SCK
0x03 | AON_SDI | AON SPI-S SDI
0x04 | AON_SDO | AON SPI-S SDO
0x07 | AON_CLK32K | AON 32 KHz clock (SCLK_LF)
0x08 | AUX_IO | AUX IO
0x09 | SSI0_RX | SSI0 RX
0x0A | SSI0_TX | SSI0 TX
0x0B | SSI0_FSS | SSI0 FSS
0x0C | SSI0_CLK | SSI0 CLK
0x0D | I2C_MSSDA | I2C Data
0x0E | I2C_MSSCL | I2C Clock
0x0F | UART0_RX | UART0 RX
0x10 | UART0_TX | UART0 TX
0x11 | UART0_CTS | UART0 CTS
0x12 | UART0_RTS | UART0 RTS
0x17 | PORT_EVENT0 | PORT EVENT 0 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x18 | PORT_EVENT1 | PORT EVENT 1 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x19 | PORT_EVENT2 | PORT EVENT 2 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x1A | PORT_EVENT3 | PORT EVENT 3 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x1B | PORT_EVENT4 | PORT EVENT 4 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x1C | PORT_EVENT5 | PORT EVENT 5 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x1D | PORT_EVENT6 | PORT EVENT 6 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x1E | PORT_EVENT7 | PORT EVENT 7 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x20 | CPU_SWV | CPU SWV
0x21 | SSI1_RX | SSI1 RX
0x22 | SSI1_TX | SSI1 TX
0x23 | SSI1_FSS | SSI1 FSS
0x24 | SSI1_CLK | SSI1 CLK
0x25 | I2S_AD0 | I2S Data 0
0x26 | I2S_AD1 | I2S Data 1
0x27 | I2S_WCLK | I2S WCLK
0x28 | I2S_BCLK | I2S BCLK
0x29 | I2S_MCLK | I2S MCLK
0x2E | RFC_TRC | RF Core Trace
0x2F | RFC_GPO0 | RF Core Data Out 0
0x30 | RFC_GPO1 | RF Core Data Out 1
0x31 | RFC_GPO2 | RF Core Data Out 2
0x32 | RFC_GPO3 | RF Core Data Out 3
0x33 | RFC_GPI0 | RF Core Data In 0
0x34 | RFC_GPI1 | RF Core Data In 1
0x35 | RFC_SMI_DL_OUT | RF Core SMI Data Link Out
0x36 | RFC_SMI_DL_IN | RF Core SMI Data Link In
0x37 | RFC_SMI_CL_OUT | RF Core SMI Command Link Out
0x38 | RFC_SMI_CL_IN | RF Core SMI Command Link In
| RW | 0x00

### TOP:IOC:IOCFG24

Address offset | 0x0000 0060
Physical address | 0x4008 1060 | Instance | IOC
Description | Configuration of DIO24
Type | RW

Bits | Field Name | Description | Type | Reset
31 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0
30 | HYST_EN | 0: Input hysteresis disable 1: Input hysteresis enable | RW | 0
29 | IE | 0: Input disabled 1: Input enabled Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be ignored. | RW | 0
28:27 | WU_CFG | If DIO is configured GPIO or non-AON peripheral signals, i.e. PORT_ID 0x00 or >0x08: 00: No wake-up 01: No wake-up 10: Wakes up from shutdown if this pad is going low. 11: Wakes up from shutdown if this pad is going high. If IO is configured for AON peripheral signals or AUX ie. PORT_ID 0x01-0x08, this register only sets wakeup enable or not. 00, 01: Wakeup disabled 10, 11: Wakeup enabled Polarity is controlled from AON registers. Note:When the MSB is set, the IOC will deactivate the output enable for the DIO. | RW | 0x0
26:24 | IOMODE | IO Mode N/A for IO configured for AON periph. signals and AUX ie. PORT_ID 0x01-0x08 AUX has its own open_source/drain configuration. 0x2: Reserved. Undefined behavior. 0x3: Reserved. Undefined behavior.
Value | ENUM name | Description
0x0 | NORMAL | Normal input / output
0x1 | INV | Inverted input / ouput
0x4 | OPENDR | Open Drain, Normal input / output
0x5 | OPENDR_INV | Open Drain Inverted input / output
0x6 | OPENSRC | Open Source Normal input / output
0x7 | OPENSRC_INV | Open Source Inverted input / output
| RW | 0x0
23:21 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0
20 | Reserved |  | RW | 0
19 | Reserved |  | RW | 0
18 | EDGE_IRQ_EN | 0: No interrupt generation 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled) | RW | 0
17:16 | EDGE_DET | Enable generation of edge detection events on this IO
Value | ENUM name | Description
0x0 | NONE | No edge detection
0x1 | NEG | Negative edge detection
0x2 | POS | Positive edge detection
0x3 | BOTH | Positive and negative edge detection
| RW | 0x0
15 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0
14:13 | PULL_CTL | Pull control
Value | ENUM name | Description
0x1 | DWN | Pull down
0x2 | UP | Pull up
0x3 | DIS | No pull
| RW | 0x3
12 | SLEW_RED | 0: Normal slew rate 1: Enables reduced slew rate in output driver. | RW | 0
11:10 | IOCURR | Selects IO current in combination with IOSTR
Value | ENUM name | Description
0x0 | 2MA | 2 mA
0x1 | 4MA | 4 mA
0x2 | 4_8MA | 4 or 8 mA 8 mA if IO is double drive strength
| RW | 0x0
9:8 | IOSTR | Select drive strength IO
Value | ENUM name | Description
0x0 | AUTO | Automatic drive strength (2/4/8 mA@VDDS)
0x1 | MIN | Minimum drive strength (2/4/8 mA@3.3V)
0x2 | MED | Medium drive strength (2/4/8 mA@2.5V)
0x3 | MAX | Maximum drive strength (2/4/8 mA@1.8V)
| RW | 0x0
7:6 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0
5:0 | PORT_ID | Selects usage for DIO24
Value | ENUM name | Description
0x00 | GPIO | General Purpose IO
0x01 | AON_SCS | AON SPI-S SCS
0x02 | AON_SCK | AON SPI-S SCK
0x03 | AON_SDI | AON SPI-S SDI
0x04 | AON_SDO | AON SPI-S SDO
0x07 | AON_CLK32K | AON 32 KHz clock (SCLK_LF)
0x08 | AUX_IO | AUX IO
0x09 | SSI0_RX | SSI0 RX
0x0A | SSI0_TX | SSI0 TX
0x0B | SSI0_FSS | SSI0 FSS
0x0C | SSI0_CLK | SSI0 CLK
0x0D | I2C_MSSDA | I2C Data
0x0E | I2C_MSSCL | I2C Clock
0x0F | UART0_RX | UART0 RX
0x10 | UART0_TX | UART0 TX
0x11 | UART0_CTS | UART0 CTS
0x12 | UART0_RTS | UART0 RTS
0x17 | PORT_EVENT0 | PORT EVENT 0 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x18 | PORT_EVENT1 | PORT EVENT 1 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x19 | PORT_EVENT2 | PORT EVENT 2 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x1A | PORT_EVENT3 | PORT EVENT 3 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x1B | PORT_EVENT4 | PORT EVENT 4 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x1C | PORT_EVENT5 | PORT EVENT 5 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x1D | PORT_EVENT6 | PORT EVENT 6 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x1E | PORT_EVENT7 | PORT EVENT 7 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x20 | CPU_SWV | CPU SWV
0x21 | SSI1_RX | SSI1 RX
0x22 | SSI1_TX | SSI1 TX
0x23 | SSI1_FSS | SSI1 FSS
0x24 | SSI1_CLK | SSI1 CLK
0x25 | I2S_AD0 | I2S Data 0
0x26 | I2S_AD1 | I2S Data 1
0x27 | I2S_WCLK | I2S WCLK
0x28 | I2S_BCLK | I2S BCLK
0x29 | I2S_MCLK | I2S MCLK
0x2E | RFC_TRC | RF Core Trace
0x2F | RFC_GPO0 | RF Core Data Out 0
0x30 | RFC_GPO1 | RF Core Data Out 1
0x31 | RFC_GPO2 | RF Core Data Out 2
0x32 | RFC_GPO3 | RF Core Data Out 3
0x33 | RFC_GPI0 | RF Core Data In 0
0x34 | RFC_GPI1 | RF Core Data In 1
0x35 | RFC_SMI_DL_OUT | RF Core SMI Data Link Out
0x36 | RFC_SMI_DL_IN | RF Core SMI Data Link In
0x37 | RFC_SMI_CL_OUT | RF Core SMI Command Link Out
0x38 | RFC_SMI_CL_IN | RF Core SMI Command Link In
| RW | 0x00

### TOP:IOC:IOCFG25

Address offset | 0x0000 0064
Physical address | 0x4008 1064 | Instance | IOC
Description | Configuration of DIO25
Type | RW

Bits | Field Name | Description | Type | Reset
31 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0
30 | HYST_EN | 0: Input hysteresis disable 1: Input hysteresis enable | RW | 0
29 | IE | 0: Input disabled 1: Input enabled Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be ignored. | RW | 0
28:27 | WU_CFG | If DIO is configured GPIO or non-AON peripheral signals, i.e. PORT_ID 0x00 or >0x08: 00: No wake-up 01: No wake-up 10: Wakes up from shutdown if this pad is going low. 11: Wakes up from shutdown if this pad is going high. If IO is configured for AON peripheral signals or AUX ie. PORT_ID 0x01-0x08, this register only sets wakeup enable or not. 00, 01: Wakeup disabled 10, 11: Wakeup enabled Polarity is controlled from AON registers. Note:When the MSB is set, the IOC will deactivate the output enable for the DIO. | RW | 0x0
26:24 | IOMODE | IO Mode N/A for IO configured for AON periph. signals and AUX ie. PORT_ID 0x01-0x08 AUX has its own open_source/drain configuration. 0x2: Reserved. Undefined behavior. 0x3: Reserved. Undefined behavior.
Value | ENUM name | Description
0x0 | NORMAL | Normal input / output
0x1 | INV | Inverted input / ouput
0x4 | OPENDR | Open Drain, Normal input / output
0x5 | OPENDR_INV | Open Drain Inverted input / output
0x6 | OPENSRC | Open Source Normal input / output
0x7 | OPENSRC_INV | Open Source Inverted input / output
| RW | 0x0
23:21 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0
20 | Reserved |  | RW | 0
19 | Reserved |  | RW | 0
18 | EDGE_IRQ_EN | 0: No interrupt generation 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled) | RW | 0
17:16 | EDGE_DET | Enable generation of edge detection events on this IO
Value | ENUM name | Description
0x0 | NONE | No edge detection
0x1 | NEG | Negative edge detection
0x2 | POS | Positive edge detection
0x3 | BOTH | Positive and negative edge detection
| RW | 0x0
15 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0
14:13 | PULL_CTL | Pull control
Value | ENUM name | Description
0x1 | DWN | Pull down
0x2 | UP | Pull up
0x3 | DIS | No pull
| RW | 0x3
12 | SLEW_RED | 0: Normal slew rate 1: Enables reduced slew rate in output driver. | RW | 0
11:10 | IOCURR | Selects IO current in combination with IOSTR
Value | ENUM name | Description
0x0 | 2MA | 2 mA
0x1 | 4MA | 4 mA
0x2 | 4_8MA | 4 or 8 mA 8 mA if IO is double drive strength
| RW | 0x0
9:8 | IOSTR | Select drive strength IO
Value | ENUM name | Description
0x0 | AUTO | Automatic drive strength (2/4/8 mA@VDDS)
0x1 | MIN | Minimum drive strength (2/4/8 mA@3.3V)
0x2 | MED | Medium drive strength (2/4/8 mA@2.5V)
0x3 | MAX | Maximum drive strength (2/4/8 mA@1.8V)
| RW | 0x0
7:6 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0
5:0 | PORT_ID | Selects usage for DIO25
Value | ENUM name | Description
0x00 | GPIO | General Purpose IO
0x01 | AON_SCS | AON SPI-S SCS
0x02 | AON_SCK | AON SPI-S SCK
0x03 | AON_SDI | AON SPI-S SDI
0x04 | AON_SDO | AON SPI-S SDO
0x07 | AON_CLK32K | AON 32 KHz clock (SCLK_LF)
0x08 | AUX_IO | AUX IO
0x09 | SSI0_RX | SSI0 RX
0x0A | SSI0_TX | SSI0 TX
0x0B | SSI0_FSS | SSI0 FSS
0x0C | SSI0_CLK | SSI0 CLK
0x0D | I2C_MSSDA | I2C Data
0x0E | I2C_MSSCL | I2C Clock
0x0F | UART0_RX | UART0 RX
0x10 | UART0_TX | UART0 TX
0x11 | UART0_CTS | UART0 CTS
0x12 | UART0_RTS | UART0 RTS
0x17 | PORT_EVENT0 | PORT EVENT 0 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x18 | PORT_EVENT1 | PORT EVENT 1 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x19 | PORT_EVENT2 | PORT EVENT 2 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x1A | PORT_EVENT3 | PORT EVENT 3 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x1B | PORT_EVENT4 | PORT EVENT 4 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x1C | PORT_EVENT5 | PORT EVENT 5 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x1D | PORT_EVENT6 | PORT EVENT 6 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x1E | PORT_EVENT7 | PORT EVENT 7 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x20 | CPU_SWV | CPU SWV
0x21 | SSI1_RX | SSI1 RX
0x22 | SSI1_TX | SSI1 TX
0x23 | SSI1_FSS | SSI1 FSS
0x24 | SSI1_CLK | SSI1 CLK
0x25 | I2S_AD0 | I2S Data 0
0x26 | I2S_AD1 | I2S Data 1
0x27 | I2S_WCLK | I2S WCLK
0x28 | I2S_BCLK | I2S BCLK
0x29 | I2S_MCLK | I2S MCLK
0x2E | RFC_TRC | RF Core Trace
0x2F | RFC_GPO0 | RF Core Data Out 0
0x30 | RFC_GPO1 | RF Core Data Out 1
0x31 | RFC_GPO2 | RF Core Data Out 2
0x32 | RFC_GPO3 | RF Core Data Out 3
0x33 | RFC_GPI0 | RF Core Data In 0
0x34 | RFC_GPI1 | RF Core Data In 1
0x35 | RFC_SMI_DL_OUT | RF Core SMI Data Link Out
0x36 | RFC_SMI_DL_IN | RF Core SMI Data Link In
0x37 | RFC_SMI_CL_OUT | RF Core SMI Command Link Out
0x38 | RFC_SMI_CL_IN | RF Core SMI Command Link In
| RW | 0x00

### TOP:IOC:IOCFG26

Address offset | 0x0000 0068
Physical address | 0x4008 1068 | Instance | IOC
Description | Configuration of DIO26
Type | RW

Bits | Field Name | Description | Type | Reset
31 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0
30 | HYST_EN | 0: Input hysteresis disable 1: Input hysteresis enable | RW | 0
29 | IE | 0: Input disabled 1: Input enabled Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be ignored. | RW | 0
28:27 | WU_CFG | If DIO is configured GPIO or non-AON peripheral signals, i.e. PORT_ID 0x00 or >0x08: 00: No wake-up 01: No wake-up 10: Wakes up from shutdown if this pad is going low. 11: Wakes up from shutdown if this pad is going high. If IO is configured for AON peripheral signals or AUX ie. PORT_ID 0x01-0x08, this register only sets wakeup enable or not. 00, 01: Wakeup disabled 10, 11: Wakeup enabled Polarity is controlled from AON registers. Note:When the MSB is set, the IOC will deactivate the output enable for the DIO. | RW | 0x0
26:24 | IOMODE | IO Mode N/A for IO configured for AON periph. signals and AUX ie. PORT_ID 0x01-0x08 AUX has its own open_source/drain configuration. 0x2: Reserved. Undefined behavior. 0x3: Reserved. Undefined behavior.
Value | ENUM name | Description
0x0 | NORMAL | Normal input / output
0x1 | INV | Inverted input / ouput
0x4 | OPENDR | Open Drain, Normal input / output
0x5 | OPENDR_INV | Open Drain Inverted input / output
0x6 | OPENSRC | Open Source Normal input / output
0x7 | OPENSRC_INV | Open Source Inverted input / output
| RW | 0x0
23:21 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0
20 | Reserved |  | RW | 0
19 | Reserved |  | RW | 0
18 | EDGE_IRQ_EN | 0: No interrupt generation 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled) | RW | 0
17:16 | EDGE_DET | Enable generation of edge detection events on this IO
Value | ENUM name | Description
0x0 | NONE | No edge detection
0x1 | NEG | Negative edge detection
0x2 | POS | Positive edge detection
0x3 | BOTH | Positive and negative edge detection
| RW | 0x0
15 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0
14:13 | PULL_CTL | Pull control
Value | ENUM name | Description
0x1 | DWN | Pull down
0x2 | UP | Pull up
0x3 | DIS | No pull
| RW | 0x3
12 | SLEW_RED | 0: Normal slew rate 1: Enables reduced slew rate in output driver. | RW | 0
11:10 | IOCURR | Selects IO current in combination with IOSTR
Value | ENUM name | Description
0x0 | 2MA | 2 mA
0x1 | 4MA | 4 mA
0x2 | 4_8MA | 4 or 8 mA 8 mA if IO is double drive strength
| RW | 0x0
9:8 | IOSTR | Select drive strength IO
Value | ENUM name | Description
0x0 | AUTO | Automatic drive strength (2/4/8 mA@VDDS)
0x1 | MIN | Minimum drive strength (2/4/8 mA@3.3V)
0x2 | MED | Medium drive strength (2/4/8 mA@2.5V)
0x3 | MAX | Maximum drive strength (2/4/8 mA@1.8V)
| RW | 0x0
7:6 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0
5:0 | PORT_ID | Selects usage for DIO26
Value | ENUM name | Description
0x00 | GPIO | General Purpose IO
0x01 | AON_SCS | AON SPI-S SCS
0x02 | AON_SCK | AON SPI-S SCK
0x03 | AON_SDI | AON SPI-S SDI
0x04 | AON_SDO | AON SPI-S SDO
0x07 | AON_CLK32K | AON 32 KHz clock (SCLK_LF)
0x08 | AUX_IO | AUX IO
0x09 | SSI0_RX | SSI0 RX
0x0A | SSI0_TX | SSI0 TX
0x0B | SSI0_FSS | SSI0 FSS
0x0C | SSI0_CLK | SSI0 CLK
0x0D | I2C_MSSDA | I2C Data
0x0E | I2C_MSSCL | I2C Clock
0x0F | UART0_RX | UART0 RX
0x10 | UART0_TX | UART0 TX
0x11 | UART0_CTS | UART0 CTS
0x12 | UART0_RTS | UART0 RTS
0x17 | PORT_EVENT0 | PORT EVENT 0 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x18 | PORT_EVENT1 | PORT EVENT 1 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x19 | PORT_EVENT2 | PORT EVENT 2 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x1A | PORT_EVENT3 | PORT EVENT 3 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x1B | PORT_EVENT4 | PORT EVENT 4 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x1C | PORT_EVENT5 | PORT EVENT 5 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x1D | PORT_EVENT6 | PORT EVENT 6 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x1E | PORT_EVENT7 | PORT EVENT 7 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x20 | CPU_SWV | CPU SWV
0x21 | SSI1_RX | SSI1 RX
0x22 | SSI1_TX | SSI1 TX
0x23 | SSI1_FSS | SSI1 FSS
0x24 | SSI1_CLK | SSI1 CLK
0x25 | I2S_AD0 | I2S Data 0
0x26 | I2S_AD1 | I2S Data 1
0x27 | I2S_WCLK | I2S WCLK
0x28 | I2S_BCLK | I2S BCLK
0x29 | I2S_MCLK | I2S MCLK
0x2E | RFC_TRC | RF Core Trace
0x2F | RFC_GPO0 | RF Core Data Out 0
0x30 | RFC_GPO1 | RF Core Data Out 1
0x31 | RFC_GPO2 | RF Core Data Out 2
0x32 | RFC_GPO3 | RF Core Data Out 3
0x33 | RFC_GPI0 | RF Core Data In 0
0x34 | RFC_GPI1 | RF Core Data In 1
0x35 | RFC_SMI_DL_OUT | RF Core SMI Data Link Out
0x36 | RFC_SMI_DL_IN | RF Core SMI Data Link In
0x37 | RFC_SMI_CL_OUT | RF Core SMI Command Link Out
0x38 | RFC_SMI_CL_IN | RF Core SMI Command Link In
| RW | 0x00

### TOP:IOC:IOCFG27

Address offset | 0x0000 006C
Physical address | 0x4008 106C | Instance | IOC
Description | Configuration of DIO27
Type | RW

Bits | Field Name | Description | Type | Reset
31 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0
30 | HYST_EN | 0: Input hysteresis disable 1: Input hysteresis enable | RW | 0
29 | IE | 0: Input disabled 1: Input enabled Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be ignored. | RW | 0
28:27 | WU_CFG | If DIO is configured GPIO or non-AON peripheral signals, i.e. PORT_ID 0x00 or >0x08: 00: No wake-up 01: No wake-up 10: Wakes up from shutdown if this pad is going low. 11: Wakes up from shutdown if this pad is going high. If IO is configured for AON peripheral signals or AUX ie. PORT_ID 0x01-0x08, this register only sets wakeup enable or not. 00, 01: Wakeup disabled 10, 11: Wakeup enabled Polarity is controlled from AON registers. Note:When the MSB is set, the IOC will deactivate the output enable for the DIO. | RW | 0x0
26:24 | IOMODE | IO Mode N/A for IO configured for AON periph. signals and AUX ie. PORT_ID 0x01-0x08 AUX has its own open_source/drain configuration. 0x2: Reserved. Undefined behavior. 0x3: Reserved. Undefined behavior.
Value | ENUM name | Description
0x0 | NORMAL | Normal input / output
0x1 | INV | Inverted input / ouput
0x4 | OPENDR | Open Drain, Normal input / output
0x5 | OPENDR_INV | Open Drain Inverted input / output
0x6 | OPENSRC | Open Source Normal input / output
0x7 | OPENSRC_INV | Open Source Inverted input / output
| RW | 0x0
23:21 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0
20 | Reserved |  | RW | 0
19 | Reserved |  | RW | 0
18 | EDGE_IRQ_EN | 0: No interrupt generation 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled) | RW | 0
17:16 | EDGE_DET | Enable generation of edge detection events on this IO
Value | ENUM name | Description
0x0 | NONE | No edge detection
0x1 | NEG | Negative edge detection
0x2 | POS | Positive edge detection
0x3 | BOTH | Positive and negative edge detection
| RW | 0x0
15 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0
14:13 | PULL_CTL | Pull control
Value | ENUM name | Description
0x1 | DWN | Pull down
0x2 | UP | Pull up
0x3 | DIS | No pull
| RW | 0x3
12 | SLEW_RED | 0: Normal slew rate 1: Enables reduced slew rate in output driver. | RW | 0
11:10 | IOCURR | Selects IO current in combination with IOSTR
Value | ENUM name | Description
0x0 | 2MA | 2 mA
0x1 | 4MA | 4 mA
0x2 | 4_8MA | 4 or 8 mA 8 mA if IO is double drive strength
| RW | 0x0
9:8 | IOSTR | Select drive strength IO
Value | ENUM name | Description
0x0 | AUTO | Automatic drive strength (2/4/8 mA@VDDS)
0x1 | MIN | Minimum drive strength (2/4/8 mA@3.3V)
0x2 | MED | Medium drive strength (2/4/8 mA@2.5V)
0x3 | MAX | Maximum drive strength (2/4/8 mA@1.8V)
| RW | 0x0
7:6 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0
5:0 | PORT_ID | Selects usage for DIO27
Value | ENUM name | Description
0x00 | GPIO | General Purpose IO
0x01 | AON_SCS | AON SPI-S SCS
0x02 | AON_SCK | AON SPI-S SCK
0x03 | AON_SDI | AON SPI-S SDI
0x04 | AON_SDO | AON SPI-S SDO
0x07 | AON_CLK32K | AON 32 KHz clock (SCLK_LF)
0x08 | AUX_IO | AUX IO
0x09 | SSI0_RX | SSI0 RX
0x0A | SSI0_TX | SSI0 TX
0x0B | SSI0_FSS | SSI0 FSS
0x0C | SSI0_CLK | SSI0 CLK
0x0D | I2C_MSSDA | I2C Data
0x0E | I2C_MSSCL | I2C Clock
0x0F | UART0_RX | UART0 RX
0x10 | UART0_TX | UART0 TX
0x11 | UART0_CTS | UART0 CTS
0x12 | UART0_RTS | UART0 RTS
0x17 | PORT_EVENT0 | PORT EVENT 0 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x18 | PORT_EVENT1 | PORT EVENT 1 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x19 | PORT_EVENT2 | PORT EVENT 2 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x1A | PORT_EVENT3 | PORT EVENT 3 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x1B | PORT_EVENT4 | PORT EVENT 4 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x1C | PORT_EVENT5 | PORT EVENT 5 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x1D | PORT_EVENT6 | PORT EVENT 6 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x1E | PORT_EVENT7 | PORT EVENT 7 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x20 | CPU_SWV | CPU SWV
0x21 | SSI1_RX | SSI1 RX
0x22 | SSI1_TX | SSI1 TX
0x23 | SSI1_FSS | SSI1 FSS
0x24 | SSI1_CLK | SSI1 CLK
0x25 | I2S_AD0 | I2S Data 0
0x26 | I2S_AD1 | I2S Data 1
0x27 | I2S_WCLK | I2S WCLK
0x28 | I2S_BCLK | I2S BCLK
0x29 | I2S_MCLK | I2S MCLK
0x2E | RFC_TRC | RF Core Trace
0x2F | RFC_GPO0 | RF Core Data Out 0
0x30 | RFC_GPO1 | RF Core Data Out 1
0x31 | RFC_GPO2 | RF Core Data Out 2
0x32 | RFC_GPO3 | RF Core Data Out 3
0x33 | RFC_GPI0 | RF Core Data In 0
0x34 | RFC_GPI1 | RF Core Data In 1
0x35 | RFC_SMI_DL_OUT | RF Core SMI Data Link Out
0x36 | RFC_SMI_DL_IN | RF Core SMI Data Link In
0x37 | RFC_SMI_CL_OUT | RF Core SMI Command Link Out
0x38 | RFC_SMI_CL_IN | RF Core SMI Command Link In
| RW | 0x00

### TOP:IOC:IOCFG28

Address offset | 0x0000 0070
Physical address | 0x4008 1070 | Instance | IOC
Description | Configuration of DIO28
Type | RW

Bits | Field Name | Description | Type | Reset
31 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0
30 | HYST_EN | 0: Input hysteresis disable 1: Input hysteresis enable | RW | 0
29 | IE | 0: Input disabled 1: Input enabled Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be ignored. | RW | 0
28:27 | WU_CFG | If DIO is configured GPIO or non-AON peripheral signals, i.e. PORT_ID 0x00 or >0x08: 00: No wake-up 01: No wake-up 10: Wakes up from shutdown if this pad is going low. 11: Wakes up from shutdown if this pad is going high. If IO is configured for AON peripheral signals or AUX ie. PORT_ID 0x01-0x08, this register only sets wakeup enable or not. 00, 01: Wakeup disabled 10, 11: Wakeup enabled Polarity is controlled from AON registers. Note:When the MSB is set, the IOC will deactivate the output enable for the DIO. | RW | 0x0
26:24 | IOMODE | IO Mode N/A for IO configured for AON periph. signals and AUX ie. PORT_ID 0x01-0x08 AUX has its own open_source/drain configuration. 0x2: Reserved. Undefined behavior. 0x3: Reserved. Undefined behavior.
Value | ENUM name | Description
0x0 | NORMAL | Normal input / output
0x1 | INV | Inverted input / ouput
0x4 | OPENDR | Open Drain, Normal input / output
0x5 | OPENDR_INV | Open Drain Inverted input / output
0x6 | OPENSRC | Open Source Normal input / output
0x7 | OPENSRC_INV | Open Source Inverted input / output
| RW | 0x0
23:21 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0
20 | Reserved |  | RW | 0
19 | Reserved |  | RW | 0
18 | EDGE_IRQ_EN | 0: No interrupt generation 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled) | RW | 0
17:16 | EDGE_DET | Enable generation of edge detection events on this IO
Value | ENUM name | Description
0x0 | NONE | No edge detection
0x1 | NEG | Negative edge detection
0x2 | POS | Positive edge detection
0x3 | BOTH | Positive and negative edge detection
| RW | 0x0
15 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0
14:13 | PULL_CTL | Pull control
Value | ENUM name | Description
0x1 | DWN | Pull down
0x2 | UP | Pull up
0x3 | DIS | No pull
| RW | 0x3
12 | SLEW_RED | 0: Normal slew rate 1: Enables reduced slew rate in output driver. | RW | 0
11:10 | IOCURR | Selects IO current in combination with IOSTR
Value | ENUM name | Description
0x0 | 2MA | 2 mA
0x1 | 4MA | 4 mA
0x2 | 4_8MA | 4 or 8 mA 8 mA if IO is double drive strength
| RW | 0x0
9:8 | IOSTR | Select drive strength IO
Value | ENUM name | Description
0x0 | AUTO | Automatic drive strength (2/4/8 mA@VDDS)
0x1 | MIN | Minimum drive strength (2/4/8 mA@3.3V)
0x2 | MED | Medium drive strength (2/4/8 mA@2.5V)
0x3 | MAX | Maximum drive strength (2/4/8 mA@1.8V)
| RW | 0x0
7:6 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0
5:0 | PORT_ID | Selects usage for DIO28
Value | ENUM name | Description
0x00 | GPIO | General Purpose IO
0x01 | AON_SCS | AON SPI-S SCS
0x02 | AON_SCK | AON SPI-S SCK
0x03 | AON_SDI | AON SPI-S SDI
0x04 | AON_SDO | AON SPI-S SDO
0x07 | AON_CLK32K | AON 32 KHz clock (SCLK_LF)
0x08 | AUX_IO | AUX IO
0x09 | SSI0_RX | SSI0 RX
0x0A | SSI0_TX | SSI0 TX
0x0B | SSI0_FSS | SSI0 FSS
0x0C | SSI0_CLK | SSI0 CLK
0x0D | I2C_MSSDA | I2C Data
0x0E | I2C_MSSCL | I2C Clock
0x0F | UART0_RX | UART0 RX
0x10 | UART0_TX | UART0 TX
0x11 | UART0_CTS | UART0 CTS
0x12 | UART0_RTS | UART0 RTS
0x17 | PORT_EVENT0 | PORT EVENT 0 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x18 | PORT_EVENT1 | PORT EVENT 1 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x19 | PORT_EVENT2 | PORT EVENT 2 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x1A | PORT_EVENT3 | PORT EVENT 3 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x1B | PORT_EVENT4 | PORT EVENT 4 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x1C | PORT_EVENT5 | PORT EVENT 5 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x1D | PORT_EVENT6 | PORT EVENT 6 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x1E | PORT_EVENT7 | PORT EVENT 7 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x20 | CPU_SWV | CPU SWV
0x21 | SSI1_RX | SSI1 RX
0x22 | SSI1_TX | SSI1 TX
0x23 | SSI1_FSS | SSI1 FSS
0x24 | SSI1_CLK | SSI1 CLK
0x25 | I2S_AD0 | I2S Data 0
0x26 | I2S_AD1 | I2S Data 1
0x27 | I2S_WCLK | I2S WCLK
0x28 | I2S_BCLK | I2S BCLK
0x29 | I2S_MCLK | I2S MCLK
0x2E | RFC_TRC | RF Core Trace
0x2F | RFC_GPO0 | RF Core Data Out 0
0x30 | RFC_GPO1 | RF Core Data Out 1
0x31 | RFC_GPO2 | RF Core Data Out 2
0x32 | RFC_GPO3 | RF Core Data Out 3
0x33 | RFC_GPI0 | RF Core Data In 0
0x34 | RFC_GPI1 | RF Core Data In 1
0x35 | RFC_SMI_DL_OUT | RF Core SMI Data Link Out
0x36 | RFC_SMI_DL_IN | RF Core SMI Data Link In
0x37 | RFC_SMI_CL_OUT | RF Core SMI Command Link Out
0x38 | RFC_SMI_CL_IN | RF Core SMI Command Link In
| RW | 0x00

### TOP:IOC:IOCFG29

Address offset | 0x0000 0074
Physical address | 0x4008 1074 | Instance | IOC
Description | Configuration of DIO29
Type | RW

Bits | Field Name | Description | Type | Reset
31 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0
30 | HYST_EN | 0: Input hysteresis disable 1: Input hysteresis enable | RW | 0
29 | IE | 0: Input disabled 1: Input enabled Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be ignored. | RW | 0
28:27 | WU_CFG | If DIO is configured GPIO or non-AON peripheral signals, i.e. PORT_ID 0x00 or >0x08: 00: No wake-up 01: No wake-up 10: Wakes up from shutdown if this pad is going low. 11: Wakes up from shutdown if this pad is going high. If IO is configured for AON peripheral signals or AUX ie. PORT_ID 0x01-0x08, this register only sets wakeup enable or not. 00, 01: Wakeup disabled 10, 11: Wakeup enabled Polarity is controlled from AON registers. Note:When the MSB is set, the IOC will deactivate the output enable for the DIO. | RW | 0x0
26:24 | IOMODE | IO Mode N/A for IO configured for AON periph. signals and AUX ie. PORT_ID 0x01-0x08 AUX has its own open_source/drain configuration. 0x2: Reserved. Undefined behavior. 0x3: Reserved. Undefined behavior.
Value | ENUM name | Description
0x0 | NORMAL | Normal input / output
0x1 | INV | Inverted input / ouput
0x4 | OPENDR | Open Drain, Normal input / output
0x5 | OPENDR_INV | Open Drain Inverted input / output
0x6 | OPENSRC | Open Source Normal input / output
0x7 | OPENSRC_INV | Open Source Inverted input / output
| RW | 0x0
23:21 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0
20 | Reserved |  | RW | 0
19 | Reserved |  | RW | 0
18 | EDGE_IRQ_EN | 0: No interrupt generation 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled) | RW | 0
17:16 | EDGE_DET | Enable generation of edge detection events on this IO
Value | ENUM name | Description
0x0 | NONE | No edge detection
0x1 | NEG | Negative edge detection
0x2 | POS | Positive edge detection
0x3 | BOTH | Positive and negative edge detection
| RW | 0x0
15 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0
14:13 | PULL_CTL | Pull control
Value | ENUM name | Description
0x1 | DWN | Pull down
0x2 | UP | Pull up
0x3 | DIS | No pull
| RW | 0x3
12 | SLEW_RED | 0: Normal slew rate 1: Enables reduced slew rate in output driver. | RW | 0
11:10 | IOCURR | Selects IO current in combination with IOSTR
Value | ENUM name | Description
0x0 | 2MA | 2 mA
0x1 | 4MA | 4 mA
0x2 | 4_8MA | 4 or 8 mA 8 mA if IO is double drive strength
| RW | 0x0
9:8 | IOSTR | Select drive strength IO
Value | ENUM name | Description
0x0 | AUTO | Automatic drive strength (2/4/8 mA@VDDS)
0x1 | MIN | Minimum drive strength (2/4/8 mA@3.3V)
0x2 | MED | Medium drive strength (2/4/8 mA@2.5V)
0x3 | MAX | Maximum drive strength (2/4/8 mA@1.8V)
| RW | 0x0
7:6 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0
5:0 | PORT_ID | Selects usage for DIO29
Value | ENUM name | Description
0x00 | GPIO | General Purpose IO
0x01 | AON_SCS | AON SPI-S SCS
0x02 | AON_SCK | AON SPI-S SCK
0x03 | AON_SDI | AON SPI-S SDI
0x04 | AON_SDO | AON SPI-S SDO
0x07 | AON_CLK32K | AON 32 KHz clock (SCLK_LF)
0x08 | AUX_IO | AUX IO
0x09 | SSI0_RX | SSI0 RX
0x0A | SSI0_TX | SSI0 TX
0x0B | SSI0_FSS | SSI0 FSS
0x0C | SSI0_CLK | SSI0 CLK
0x0D | I2C_MSSDA | I2C Data
0x0E | I2C_MSSCL | I2C Clock
0x0F | UART0_RX | UART0 RX
0x10 | UART0_TX | UART0 TX
0x11 | UART0_CTS | UART0 CTS
0x12 | UART0_RTS | UART0 RTS
0x17 | PORT_EVENT0 | PORT EVENT 0 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x18 | PORT_EVENT1 | PORT EVENT 1 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x19 | PORT_EVENT2 | PORT EVENT 2 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x1A | PORT_EVENT3 | PORT EVENT 3 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x1B | PORT_EVENT4 | PORT EVENT 4 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x1C | PORT_EVENT5 | PORT EVENT 5 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x1D | PORT_EVENT6 | PORT EVENT 6 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x1E | PORT_EVENT7 | PORT EVENT 7 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x20 | CPU_SWV | CPU SWV
0x21 | SSI1_RX | SSI1 RX
0x22 | SSI1_TX | SSI1 TX
0x23 | SSI1_FSS | SSI1 FSS
0x24 | SSI1_CLK | SSI1 CLK
0x25 | I2S_AD0 | I2S Data 0
0x26 | I2S_AD1 | I2S Data 1
0x27 | I2S_WCLK | I2S WCLK
0x28 | I2S_BCLK | I2S BCLK
0x29 | I2S_MCLK | I2S MCLK
0x2E | RFC_TRC | RF Core Trace
0x2F | RFC_GPO0 | RF Core Data Out 0
0x30 | RFC_GPO1 | RF Core Data Out 1
0x31 | RFC_GPO2 | RF Core Data Out 2
0x32 | RFC_GPO3 | RF Core Data Out 3
0x33 | RFC_GPI0 | RF Core Data In 0
0x34 | RFC_GPI1 | RF Core Data In 1
0x35 | RFC_SMI_DL_OUT | RF Core SMI Data Link Out
0x36 | RFC_SMI_DL_IN | RF Core SMI Data Link In
0x37 | RFC_SMI_CL_OUT | RF Core SMI Command Link Out
0x38 | RFC_SMI_CL_IN | RF Core SMI Command Link In
| RW | 0x00

### TOP:IOC:IOCFG30

Address offset | 0x0000 0078
Physical address | 0x4008 1078 | Instance | IOC
Description | Configuration of DIO30
Type | RW

Bits | Field Name | Description | Type | Reset
31 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0
30 | HYST_EN | 0: Input hysteresis disable 1: Input hysteresis enable | RW | 0
29 | IE | 0: Input disabled 1: Input enabled Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be ignored. | RW | 0
28:27 | WU_CFG | If DIO is configured GPIO or non-AON peripheral signals, i.e. PORT_ID 0x00 or >0x08: 00: No wake-up 01: No wake-up 10: Wakes up from shutdown if this pad is going low. 11: Wakes up from shutdown if this pad is going high. If IO is configured for AON peripheral signals or AUX ie. PORT_ID 0x01-0x08, this register only sets wakeup enable or not. 00, 01: Wakeup disabled 10, 11: Wakeup enabled Polarity is controlled from AON registers. Note:When the MSB is set, the IOC will deactivate the output enable for the DIO. | RW | 0x0
26:24 | IOMODE | IO Mode N/A for IO configured for AON periph. signals and AUX ie. PORT_ID 0x01-0x08 AUX has its own open_source/drain configuration. 0x2: Reserved. Undefined behavior. 0x3: Reserved. Undefined behavior.
Value | ENUM name | Description
0x0 | NORMAL | Normal input / output
0x1 | INV | Inverted input / ouput
0x4 | OPENDR | Open Drain, Normal input / output
0x5 | OPENDR_INV | Open Drain Inverted input / output
0x6 | OPENSRC | Open Source Normal input / output
0x7 | OPENSRC_INV | Open Source Inverted input / output
| RW | 0x0
23:21 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0
20 | Reserved |  | RW | 0
19 | Reserved |  | RW | 0
18 | EDGE_IRQ_EN | 0: No interrupt generation 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled) | RW | 0
17:16 | EDGE_DET | Enable generation of edge detection events on this IO
Value | ENUM name | Description
0x0 | NONE | No edge detection
0x1 | NEG | Negative edge detection
0x2 | POS | Positive edge detection
0x3 | BOTH | Positive and negative edge detection
| RW | 0x0
15 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0
14:13 | PULL_CTL | Pull control
Value | ENUM name | Description
0x1 | DWN | Pull down
0x2 | UP | Pull up
0x3 | DIS | No pull
| RW | 0x3
12 | SLEW_RED | 0: Normal slew rate 1: Enables reduced slew rate in output driver. | RW | 0
11:10 | IOCURR | Selects IO current in combination with IOSTR
Value | ENUM name | Description
0x0 | 2MA | 2 mA
0x1 | 4MA | 4 mA
0x2 | 4_8MA | 4 or 8 mA 8 mA if IO is double drive strength
| RW | 0x0
9:8 | IOSTR | Select drive strength IO
Value | ENUM name | Description
0x0 | AUTO | Automatic drive strength (2/4/8 mA@VDDS)
0x1 | MIN | Minimum drive strength (2/4/8 mA@3.3V)
0x2 | MED | Medium drive strength (2/4/8 mA@2.5V)
0x3 | MAX | Maximum drive strength (2/4/8 mA@1.8V)
| RW | 0x0
7:6 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0
5:0 | PORT_ID | Selects usage for DIO30
Value | ENUM name | Description
0x00 | GPIO | General Purpose IO
0x01 | AON_SCS | AON SPI-S SCS
0x02 | AON_SCK | AON SPI-S SCK
0x03 | AON_SDI | AON SPI-S SDI
0x04 | AON_SDO | AON SPI-S SDO
0x07 | AON_CLK32K | AON 32 KHz clock (SCLK_LF)
0x08 | AUX_IO | AUX IO
0x09 | SSI0_RX | SSI0 RX
0x0A | SSI0_TX | SSI0 TX
0x0B | SSI0_FSS | SSI0 FSS
0x0C | SSI0_CLK | SSI0 CLK
0x0D | I2C_MSSDA | I2C Data
0x0E | I2C_MSSCL | I2C Clock
0x0F | UART0_RX | UART0 RX
0x10 | UART0_TX | UART0 TX
0x11 | UART0_CTS | UART0 CTS
0x12 | UART0_RTS | UART0 RTS
0x17 | PORT_EVENT0 | PORT EVENT 0 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x18 | PORT_EVENT1 | PORT EVENT 1 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x19 | PORT_EVENT2 | PORT EVENT 2 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x1A | PORT_EVENT3 | PORT EVENT 3 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x1B | PORT_EVENT4 | PORT EVENT 4 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x1C | PORT_EVENT5 | PORT EVENT 5 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x1D | PORT_EVENT6 | PORT EVENT 6 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x1E | PORT_EVENT7 | PORT EVENT 7 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x20 | CPU_SWV | CPU SWV
0x21 | SSI1_RX | SSI1 RX
0x22 | SSI1_TX | SSI1 TX
0x23 | SSI1_FSS | SSI1 FSS
0x24 | SSI1_CLK | SSI1 CLK
0x25 | I2S_AD0 | I2S Data 0
0x26 | I2S_AD1 | I2S Data 1
0x27 | I2S_WCLK | I2S WCLK
0x28 | I2S_BCLK | I2S BCLK
0x29 | I2S_MCLK | I2S MCLK
0x2E | RFC_TRC | RF Core Trace
0x2F | RFC_GPO0 | RF Core Data Out 0
0x30 | RFC_GPO1 | RF Core Data Out 1
0x31 | RFC_GPO2 | RF Core Data Out 2
0x32 | RFC_GPO3 | RF Core Data Out 3
0x33 | RFC_GPI0 | RF Core Data In 0
0x34 | RFC_GPI1 | RF Core Data In 1
0x35 | RFC_SMI_DL_OUT | RF Core SMI Data Link Out
0x36 | RFC_SMI_DL_IN | RF Core SMI Data Link In
0x37 | RFC_SMI_CL_OUT | RF Core SMI Command Link Out
0x38 | RFC_SMI_CL_IN | RF Core SMI Command Link In
| RW | 0x00

### TOP:IOC:IOCFG31

Address offset | 0x0000 007C
Physical address | 0x4008 107C | Instance | IOC
Description | Configuration of DIO31
Type | RW

Bits | Field Name | Description | Type | Reset
31 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0
30 | HYST_EN | 0: Input hysteresis disable 1: Input hysteresis enable | RW | 0
29 | IE | 0: Input disabled 1: Input enabled Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be ignored. | RW | 0
28:27 | WU_CFG | If DIO is configured GPIO or non-AON peripheral signals, i.e. PORT_ID 0x00 or >0x08: 00: No wake-up 01: No wake-up 10: Wakes up from shutdown if this pad is going low. 11: Wakes up from shutdown if this pad is going high. If IO is configured for AON peripheral signals or AUX ie. PORT_ID 0x01-0x08, this register only sets wakeup enable or not. 00, 01: Wakeup disabled 10, 11: Wakeup enabled Polarity is controlled from AON registers. Note:When the MSB is set, the IOC will deactivate the output enable for the DIO. | RW | 0x0
26:24 | IOMODE | IO Mode N/A for IO configured for AON periph. signals and AUX ie. PORT_ID 0x01-0x08 AUX has its own open_source/drain configuration. 0x2: Reserved. Undefined behavior. 0x3: Reserved. Undefined behavior.
Value | ENUM name | Description
0x0 | NORMAL | Normal input / output
0x1 | INV | Inverted input / ouput
0x4 | OPENDR | Open Drain, Normal input / output
0x5 | OPENDR_INV | Open Drain Inverted input / output
0x6 | OPENSRC | Open Source Normal input / output
0x7 | OPENSRC_INV | Open Source Inverted input / output
| RW | 0x0
23:21 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0
20 | Reserved |  | RW | 0
19 | Reserved |  | RW | 0
18 | EDGE_IRQ_EN | 0: No interrupt generation 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled) | RW | 0
17:16 | EDGE_DET | Enable generation of edge detection events on this IO
Value | ENUM name | Description
0x0 | NONE | No edge detection
0x1 | NEG | Negative edge detection
0x2 | POS | Positive edge detection
0x3 | BOTH | Positive and negative edge detection
| RW | 0x0
15 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0
14:13 | PULL_CTL | Pull control
Value | ENUM name | Description
0x1 | DWN | Pull down
0x2 | UP | Pull up
0x3 | DIS | No pull
| RW | 0x3
12 | SLEW_RED | 0: Normal slew rate 1: Enables reduced slew rate in output driver. | RW | 0
11:10 | IOCURR | Selects IO current in combination with IOSTR
Value | ENUM name | Description
0x0 | 2MA | 2 mA
0x1 | 4MA | 4 mA
0x2 | 4_8MA | 4 or 8 mA 8 mA if IO is double drive strength
| RW | 0x0
9:8 | IOSTR | Select drive strength IO
Value | ENUM name | Description
0x0 | AUTO | Automatic drive strength (2/4/8 mA@VDDS)
0x1 | MIN | Minimum drive strength (2/4/8 mA@3.3V)
0x2 | MED | Medium drive strength (2/4/8 mA@2.5V)
0x3 | MAX | Maximum drive strength (2/4/8 mA@1.8V)
| RW | 0x0
7:6 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0
5:0 | PORT_ID | Selects usage for DIO31
Value | ENUM name | Description
0x00 | GPIO | General Purpose IO
0x01 | AON_SCS | AON SPI-S SCS
0x02 | AON_SCK | AON SPI-S SCK
0x03 | AON_SDI | AON SPI-S SDI
0x04 | AON_SDO | AON SPI-S SDO
0x07 | AON_CLK32K | AON 32 KHz clock (SCLK_LF)
0x08 | AUX_IO | AUX IO
0x09 | SSI0_RX | SSI0 RX
0x0A | SSI0_TX | SSI0 TX
0x0B | SSI0_FSS | SSI0 FSS
0x0C | SSI0_CLK | SSI0 CLK
0x0D | I2C_MSSDA | I2C Data
0x0E | I2C_MSSCL | I2C Clock
0x0F | UART0_RX | UART0 RX
0x10 | UART0_TX | UART0 TX
0x11 | UART0_CTS | UART0 CTS
0x12 | UART0_RTS | UART0 RTS
0x17 | PORT_EVENT0 | PORT EVENT 0 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x18 | PORT_EVENT1 | PORT EVENT 1 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x19 | PORT_EVENT2 | PORT EVENT 2 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x1A | PORT_EVENT3 | PORT EVENT 3 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x1B | PORT_EVENT4 | PORT EVENT 4 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x1C | PORT_EVENT5 | PORT EVENT 5 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x1D | PORT_EVENT6 | PORT EVENT 6 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x1E | PORT_EVENT7 | PORT EVENT 7 Can be used as a general purpose IO event by selecting it via registers in the EVENT module, e.g. EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, etc
0x20 | CPU_SWV | CPU SWV
0x21 | SSI1_RX | SSI1 RX
0x22 | SSI1_TX | SSI1 TX
0x23 | SSI1_FSS | SSI1 FSS
0x24 | SSI1_CLK | SSI1 CLK
0x25 | I2S_AD0 | I2S Data 0
0x26 | I2S_AD1 | I2S Data 1
0x27 | I2S_WCLK | I2S WCLK
0x28 | I2S_BCLK | I2S BCLK
0x29 | I2S_MCLK | I2S MCLK
0x2E | RFC_TRC | RF Core Trace
0x2F | RFC_GPO0 | RF Core Data Out 0
0x30 | RFC_GPO1 | RF Core Data Out 1
0x31 | RFC_GPO2 | RF Core Data Out 2
0x32 | RFC_GPO3 | RF Core Data Out 3
0x33 | RFC_GPI0 | RF Core Data In 0
0x34 | RFC_GPI1 | RF Core Data In 1
0x35 | RFC_SMI_DL_OUT | RF Core SMI Data Link Out
0x36 | RFC_SMI_DL_IN | RF Core SMI Data Link In
0x37 | RFC_SMI_CL_OUT | RF Core SMI Command Link Out
0x38 | RFC_SMI_CL_IN | RF Core SMI Command Link In
| RW | 0x00