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cpu.h
Go to the documentation of this file.
1 /******************************************************************************
2 * Filename: cpu.h
3 * Revised: 2015-01-14 12:12:44 +0100 (on, 14 jan 2015)
4 * Revision: 42373
5 *
6 * Description: Defines and prototypes for the CPU instruction wrapper
7 * functions.
8 *
9 * Copyright (c) 2015, Texas Instruments Incorporated
10 * All rights reserved.
11 *
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions are met:
14 *
15 * 1) Redistributions of source code must retain the above copyright notice,
16 * this list of conditions and the following disclaimer.
17 *
18 * 2) Redistributions in binary form must reproduce the above copyright notice,
19 * this list of conditions and the following disclaimer in the documentation
20 * and/or other materials provided with the distribution.
21 *
22 * 3) Neither the name of the ORGANIZATION nor the names of its contributors may
23 * be used to endorse or promote products derived from this software without
24 * specific prior written permission.
25 *
26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
27 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
29 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
30 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
36 * POSSIBILITY OF SUCH DAMAGE.
37 *
38 ******************************************************************************/
39
40 //*****************************************************************************
41 //
44 //
45 //*****************************************************************************
46
47 #ifndef __CPU_H__
48 #define __CPU_H__
49
50 //*****************************************************************************
51 //
52 // If building with a C++ compiler, make all of the definitions in this header
53 // have a C binding.
54 //
55 //*****************************************************************************
56 #ifdef __cplusplus
57 extern "C"
58 {
59 #endif
60
61 #include <stdbool.h>
62 #include <stdint.h>
63 #include <inc/hw_types.h>
64
65 //*****************************************************************************
66 //
67 // Support for DriverLib in ROM:
68 // This section renames all functions that are not "static inline", so that
69 // calling these functions will default to implementation in flash. At the end
70 // of this file a second renaming will change the defaults to implementation in
71 // ROM for available functions.
72 //
73 // To force use of the implementation in flash, e.g. for debugging:
74 // - Globally: Define DRIVERLIB_NOROM at project level
75 // - Per function: Use prefix "NOROM_" when calling the function
76 //
77 // Do not define DRIVERLIB_GENERATE_ROM!
78 //
79 //*****************************************************************************
80 #ifndef DRIVERLIB_GENERATE_ROM
81 #define CPUcpsid NOROM_CPUcpsid
82 #define CPUprimask NOROM_CPUprimask
83 #define CPUcpsie NOROM_CPUcpsie
84 #define CPUbasepriGet NOROM_CPUbasepriGet
85 #define CPUdelay NOROM_CPUdelay
86 #endif
87
88 //*****************************************************************************
89 //
90 // API Functions and prototypes
91 //
92 //*****************************************************************************
93
94 //*****************************************************************************
95 //
102 //
103 //*****************************************************************************
104 extern uint32_t CPUcpsid(void);
105
106 //*****************************************************************************
107 //
116 //
117 //*****************************************************************************
118 extern uint32_t CPUprimask(void);
119
120 //*****************************************************************************
121 //
128 //
129 //*****************************************************************************
130 extern uint32_t CPUcpsie(void);
131
132 //*****************************************************************************
133 //
140 //
141 //*****************************************************************************
142 #if defined(codered) || defined(gcc) || defined(sourcerygxx)
143 __STATIC_INLINE void __attribute__((always_inline))
144 CPUwfi(void)
145 {
146 //
147 // Wait for the next interrupt.
148 //
149 __asm(" wfi\n");
150 }
151 #endif
152 #if defined(__IAR_SYSTEMS_ICC__) || defined(DOXYGEN)
153 __STATIC_INLINE void
154 CPUwfi(void)
155 {
156 //
157 // Wait for the next interrupt.
158 //
159 __asm(" wfi\n");
160 }
161 #endif
162 #if defined(rvmdk) || defined(__ARMCC_VERSION)
163 __asm __STATIC_INLINE void
164 CPUwfi(void)
165 {
166 //
167 // Wait for the next interrupt.
168 //
169 wfi;
170 bx lr
171 }
172 #endif
173 #if defined(__TI_COMPILER_VERSION__)
174 __STATIC_INLINE void
175 CPUwfi(void)
176 {
177 //
178 // Wait for the next interrupt.
179 //
180 __asm(" wfi\n");
181 }
182 #endif
183
184 //*****************************************************************************
185 //
192 //
193 //*****************************************************************************
194 #if defined(codered) || defined(gcc) || defined(sourcerygxx)
195 __STATIC_INLINE void __attribute__((always_inline))
196 CPUwfe(void)
197 {
198 //
199 // Wait for the next event.
200 //
201 __asm(" wfe\n");
202 }
203 #endif
204 #if defined(__IAR_SYSTEMS_ICC__) || defined(DOXYGEN)
205 __STATIC_INLINE void
206 CPUwfe(void)
207 {
208 //
209 // Wait for the next event.
210 //
211 __asm(" wfe\n");
212 }
213 #endif
214 #if defined(rvmdk) || defined(__ARMCC_VERSION)
215 __asm __STATIC_INLINE void
216 CPUwfe(void)
217 {
218 //
219 // Wait for the next event.
220 //
221 wfe;
222 bx lr
223 }
224 #endif
225 #if defined(__TI_COMPILER_VERSION__)
226 __STATIC_INLINE void
227 CPUwfe(void)
228 {
229 //
230 // Wait for the next event.
231 //
232 __asm(" wfe\n");
233 }
234 #endif
235
236 //*****************************************************************************
237 //
244 //
245 //*****************************************************************************
246 #if defined(codered) || defined(gcc) || defined(sourcerygxx)
247 __STATIC_INLINE void __attribute__((always_inline))
248 CPUsev(void)
249 {
250 //
251 // Send event.
252 //
253 __asm(" sev\n");
254 }
255 #endif
256 #if defined(__IAR_SYSTEMS_ICC__) || defined(DOXYGEN)
257 __STATIC_INLINE void
258 CPUsev(void)
259 {
260 //
261 // Send event.
262 //
263 __asm(" sev\n");
264 }
265 #endif
266 #if defined(rvmdk) || defined(__ARMCC_VERSION)
267 __asm __STATIC_INLINE void
268 CPUsev(void)
269 {
270 //
271 // Send event.
272 //
273 sev;
274 bx lr
275 }
276 #endif
277 #if defined(__TI_COMPILER_VERSION__)
278 __STATIC_INLINE void
279 CPUsev(void)
280 {
281 //
282 // Send event.
283 //
284 __asm(" sev\n");
285 }
286 #endif
287
288
289 //*****************************************************************************
290 //
299 //
300 //*****************************************************************************
301 #if defined(gcc)
302 #pragma GCC diagnostic push
303 #pragma GCC diagnostic ignored "-Wattributes"
304 __STATIC_INLINE void __attribute__ ((naked))
305 CPUbasepriSet(uint32_t ui32NewBasepri)
306 {
307 //
308 // Set the BASEPRI register.
309 //
310 __asm(" msr BASEPRI, r0\n"
311 " bx lr\n");
312 }
313 #pragma GCC diagnostic pop
314 #endif
315 #if defined(__IAR_SYSTEMS_ICC__) || defined(DOXYGEN)
316 __STATIC_INLINE void
317 CPUbasepriSet(uint32_t ui32NewBasepri)
318 {
319 //
320 // Set the BASEPRI register.
321 //
322 __asm(" msr BASEPRI, r0\n");
323 }
324 #endif
325 #if defined(rvmdk) || defined(__ARMCC_VERSION)
326 __asm __STATIC_INLINE void
327 CPUbasepriSet(uint32_t ui32NewBasepri)
328 {
329 //
330 // Set the BASEPRI register.
331 //
332 msr BASEPRI, r0;
333 bx lr
334 }
335 #endif
336 #if defined(__TI_COMPILER_VERSION__)
337 __STATIC_INLINE void
338 CPUbasepriSet(uint32_t ui32NewBasepri)
339 {
340 //
341 // Set the BASEPRI register.
342 //
343 __asm(" msr BASEPRI, r0\n");
344 }
345 #endif
346
347 //*****************************************************************************
348 //
355 //
356 //*****************************************************************************
357 extern uint32_t CPUbasepriGet(void);
358
359 //*****************************************************************************
360 //
372 //
373 //*****************************************************************************
374 extern void CPUdelay(uint32_t ui32Count);
375
376 //*****************************************************************************
377 //
378 // Support for DriverLib in ROM:
379 // Redirect to implementation in ROM when available.
380 //
381 //*****************************************************************************
382 #ifndef DRIVERLIB_NOROM
383 #include <driverlib/rom.h>
384 #ifdef ROM_CPUcpsid
385 #undef CPUcpsid
386 #define CPUcpsid ROM_CPUcpsid
387 #endif
388 #ifdef ROM_CPUprimask
389 #undef CPUprimask
390 #define CPUprimask ROM_CPUprimask
391 #endif
392 #ifdef ROM_CPUcpsie
393 #undef CPUcpsie
394 #define CPUcpsie ROM_CPUcpsie
395 #endif
396 #ifdef ROM_CPUbasepriGet
397 #undef CPUbasepriGet
398 #define CPUbasepriGet ROM_CPUbasepriGet
399 #endif
400 #ifdef ROM_CPUdelay
401 #undef CPUdelay
402 #define CPUdelay ROM_CPUdelay
403 #endif
404 #endif
405
406 //*****************************************************************************
407 //
408 // Mark the end of the C bindings section for C++ compilers.
409 //
410 //*****************************************************************************
411 #ifdef __cplusplus
412 }
413 #endif
414
415 #endif // __CPU_H__
416
417 //*****************************************************************************
418 //
421 //
422 //*****************************************************************************
CPUprimask
uint32_t CPUprimask(void)
Get the current interrupt state.
Definition: cpu.c:171
CPUcpsid
uint32_t CPUcpsid(void)
Disable all external interrupts.
Definition: cpu.c:91
CPUsev
__STATIC_INLINE void CPUsev(void)
Send event.
Definition: cpu.h:258
CPUwfi
__STATIC_INLINE void CPUwfi(void)
Wait for interrupt.
Definition: cpu.h:154
CPUwfe
__STATIC_INLINE void CPUwfe(void)
Wait for event.
Definition: cpu.h:206
CPUcpsie
uint32_t CPUcpsie(void)
Enable all external interrupts.
Definition: cpu.c:249
rom.h
CPUbasepriSet
__STATIC_INLINE void CPUbasepriSet(uint32_t ui32NewBasepri)
Update the interrupt priority disable level.
Definition: cpu.h:317
CPUbasepriGet
uint32_t CPUbasepriGet(void)
Get the interrupt priority disable level.
Definition: cpu.c:329
CPUdelay
void CPUdelay(uint32_t ui32Count)
Provide a small delay.
Definition: cpu.c:402