## FLASH

Instance: FLASH
Component: FLASH
Base address: 0x40030000

Flash sub-system registers, includes the Flash Memory Controller (FMC), flash read path, and an integrated Efuse controller and EFUSEROM.

### TOP:FLASH Register Summary

Register Name | Type | Register Width (Bits) | Register Reset | Address Offset | Physical Address
STAT | RO | 32 | 0x0000 0000 | 0x0000 001C | 0x4003 001C
CFG | RW | 32 | 0x0000 0000 | 0x0000 0024 | 0x4003 0024
SYSCODE_START | RW | 32 | 0x0000 0000 | 0x0000 0028 | 0x4003 0028
FLASH_SIZE | RW | 32 | 0x0000 0000 | 0x0000 002C | 0x4003 002C
FWLOCK | RW | 32 | 0x0000 0000 | 0x0000 003C | 0x4003 003C
FWFLAG | RW | 32 | 0x0000 0000 | 0x0000 0040 | 0x4003 0040
EFUSE | RW | 32 | 0x0000 0000 | 0x0000 1000 | 0x4003 1000
EFUSEADDR | RW | 32 | 0x0000 0000 | 0x0000 1004 | 0x4003 1004
DATAUPPER | RW | 32 | 0x0000 0000 | 0x0000 1008 | 0x4003 1008
DATALOWER | RW | 32 | 0x0000 0000 | 0x0000 100C | 0x4003 100C
EFUSECFG | RW | 32 | 0x0000 0001 | 0x0000 1010 | 0x4003 1010
EFUSESTAT | RO | 32 | 0x0000 0001 | 0x0000 1014 | 0x4003 1014
ACC | RO | 32 | 0x0000 0000 | 0x0000 1018 | 0x4003 1018
BOUNDARY | RW | 32 | 0x0000 0000 | 0x0000 101C | 0x4003 101C
EFUSEFLAG | RO | 32 | 0x0000 0000 | 0x0000 1020 | 0x4003 1020
EFUSEKEY | RW | 32 | 0x0000 0000 | 0x0000 1024 | 0x4003 1024
EFUSERELEASE | RO | 32 | 0x0000 0000 | 0x0000 1028 | 0x4003 1028
EFUSEPINS | RO | 32 | 0x0000 0000 | 0x0000 102C | 0x4003 102C
EFUSECRA | RW | 32 | 0x0000 0000 | 0x0000 1030 | 0x4003 1030
EFUSEREAD | RW | 32 | 0x0000 0000 | 0x0000 1034 | 0x4003 1034
EFUSEPROGRAM | RW | 32 | 0x0000 0000 | 0x0000 1038 | 0x4003 1038
EFUSEERROR | RW | 32 | 0x0000 0000 | 0x0000 103C | 0x4003 103C
SINGLEBIT | RO | 32 | 0x0000 0000 | 0x0000 1040 | 0x4003 1040
TWOBIT | RO | 32 | 0x0000 0000 | 0x0000 1044 | 0x4003 1044
SELFTESTCYC | RW | 32 | 0x0000 0000 | 0x0000 1048 | 0x4003 1048
SELFTESTSIGN | RW | 32 | 0x0000 0000 | 0x0000 104C | 0x4003 104C
FRDCTL | RW | 32 | 0x0000 0200 | 0x0000 2000 | 0x4003 2000
FSPRD | RW | 32 | 0x0000 0000 | 0x0000 2004 | 0x4003 2004
FEDACCTL1 | RW | 32 | 0x0000 0000 | 0x0000 2008 | 0x4003 2008
FEDACSTAT | RW | 32 | 0x0000 0000 | 0x0000 201C | 0x4003 201C
FBPROT | RW | 32 | 0x0000 0000 | 0x0000 2030 | 0x4003 2030
FBSE | RW | 32 | 0x0000 0000 | 0x0000 2034 | 0x4003 2034
FBBUSY | RO | 32 | 0x0000 00FE | 0x0000 2038 | 0x4003 2038
FBAC | RW | 32 | 0x0000 000F | 0x0000 203C | 0x4003 203C
FBFALLBACK | RW | 32 | 0x0505 FFFF | 0x0000 2040 | 0x4003 2040
FBPRDY | RO | 32 | 0x00FF 00FE | 0x0000 2044 | 0x4003 2044
FPAC1 | RW | 32 | 0x0208 2081 | 0x0000 2048 | 0x4003 2048
FPAC2 | RW | 32 | 0x0000 0000 | 0x0000 204C | 0x4003 204C
FMAC | RW | 32 | 0x0000 0000 | 0x0000 2050 | 0x4003 2050
FMSTAT | RO | 32 | 0x0000 0000 | 0x0000 2054 | 0x4003 2054
FLOCK | RW | 32 | 0x0000 55AA | 0x0000 2064 | 0x4003 2064
FVREADCT | RW | 32 | 0x0000 0008 | 0x0000 2080 | 0x4003 2080
FVHVCT1 | RW | 32 | 0x0084 0088 | 0x0000 2084 | 0x4003 2084
FVHVCT2 | RW | 32 | 0x00A2 0000 | 0x0000 2088 | 0x4003 2088
FVHVCT3 | RW | 32 | 0x000F 0000 | 0x0000 208C | 0x4003 208C
FVNVCT | RW | 32 | 0x0000 0800 | 0x0000 2090 | 0x4003 2090
FVSLP | RW | 32 | 0x0000 8000 | 0x0000 2094 | 0x4003 2094
FVWLCT | RW | 32 | 0x0000 0008 | 0x0000 2098 | 0x4003 2098
FEFUSECTL | RW | 32 | 0x0701 010A | 0x0000 209C | 0x4003 209C
FEFUSESTAT | RW | 32 | 0x0000 0000 | 0x0000 20A0 | 0x4003 20A0
FEFUSEDATA | RW | 32 | 0x0000 0000 | 0x0000 20A4 | 0x4003 20A4
FSEQPMP | RW | 32 | 0x8508 0000 | 0x0000 20A8 | 0x4003 20A8
FBSTROBES | RW | 32 | 0x0000 0104 | 0x0000 2100 | 0x4003 2100
FPSTROBES | RW | 32 | 0x0000 0103 | 0x0000 2104 | 0x4003 2104
FBMODE | RW | 32 | 0x0000 0000 | 0x0000 2108 | 0x4003 2108
FTCR | RW | 32 | 0x0000 0000 | 0x0000 210C | 0x4003 210C
FADDR | RW | 32 | 0x0000 0000 | 0x0000 2110 | 0x4003 2110
FTCTL | RW | 32 | 0x0000 0000 | 0x0000 211C | 0x4003 211C
FWPWRITE0 | RW | 32 | 0xFFFF FFFF | 0x0000 2120 | 0x4003 2120
FWPWRITE1 | RW | 32 | 0xFFFF FFFF | 0x0000 2124 | 0x4003 2124
FWPWRITE2 | RW | 32 | 0xFFFF FFFF | 0x0000 2128 | 0x4003 2128
FWPWRITE3 | RW | 32 | 0xFFFF FFFF | 0x0000 212C | 0x4003 212C
FWPWRITE4 | RW | 32 | 0xFFFF FFFF | 0x0000 2130 | 0x4003 2130
FWPWRITE5 | RW | 32 | 0xFFFF FFFF | 0x0000 2134 | 0x4003 2134
FWPWRITE6 | RW | 32 | 0xFFFF FFFF | 0x0000 2138 | 0x4003 2138
FWPWRITE7 | RW | 32 | 0xFFFF FFFF | 0x0000 213C | 0x4003 213C
FWPWRITE_ECC | RW | 32 | 0xFFFF FFFF | 0x0000 2140 | 0x4003 2140
FSWSTAT | RO | 32 | 0x0000 0001 | 0x0000 2144 | 0x4003 2144
FSM_GLBCTL | RO | 32 | 0x0000 0001 | 0x0000 2200 | 0x4003 2200
FSM_STATE | RO | 32 | 0x0000 0C00 | 0x0000 2204 | 0x4003 2204
FSM_STAT | RO | 32 | 0x0000 0004 | 0x0000 2208 | 0x4003 2208
FSM_CMD | RW | 32 | 0x0000 0000 | 0x0000 220C | 0x4003 220C
FSM_PE_OSU | RW | 32 | 0x0000 0000 | 0x0000 2210 | 0x4003 2210
FSM_VSTAT | RW | 32 | 0x0000 3000 | 0x0000 2214 | 0x4003 2214
FSM_PE_VSU | RW | 32 | 0x0000 0000 | 0x0000 2218 | 0x4003 2218
FSM_CMP_VSU | RW | 32 | 0x0000 0000 | 0x0000 221C | 0x4003 221C
FSM_EX_VAL | RW | 32 | 0x0000 0301 | 0x0000 2220 | 0x4003 2220
FSM_RD_H | RW | 32 | 0x0000 005A | 0x0000 2224 | 0x4003 2224
FSM_P_OH | RW | 32 | 0x0000 0100 | 0x0000 2228 | 0x4003 2228
FSM_ERA_OH | RW | 32 | 0x0000 0001 | 0x0000 222C | 0x4003 222C
FSM_SAV_PPUL | RO | 32 | 0x0000 0000 | 0x0000 2230 | 0x4003 2230
FSM_PE_VH | RW | 32 | 0x0000 0100 | 0x0000 2234 | 0x4003 2234
FSM_PRG_PW | RW | 32 | 0x0000 0000 | 0x0000 2240 | 0x4003 2240
FSM_ERA_PW | RW | 32 | 0x0000 0000 | 0x0000 2244 | 0x4003 2244
FSM_SAV_ERA_PUL | RO | 32 | 0x0000 0000 | 0x0000 2254 | 0x4003 2254
FSM_TIMER | RO | 32 | 0x0000 0000 | 0x0000 2258 | 0x4003 2258
FSM_MODE | RO | 32 | 0x0000 0000 | 0x0000 225C | 0x4003 225C
FSM_PGM | RO | 32 | 0x0000 0000 | 0x0000 2260 | 0x4003 2260
FSM_ERA | RO | 32 | 0x0000 0000 | 0x0000 2264 | 0x4003 2264
FSM_PRG_PUL | RW | 32 | 0x0004 0032 | 0x0000 2268 | 0x4003 2268
FSM_ERA_PUL | RW | 32 | 0x0004 0BB8 | 0x0000 226C | 0x4003 226C
FSM_STEP_SIZE | RW | 32 | 0x0000 0000 | 0x0000 2270 | 0x4003 2270
FSM_PUL_CNTR | RO | 32 | 0x0000 0000 | 0x0000 2274 | 0x4003 2274
FSM_EC_STEP_HEIGHT | RW | 32 | 0x0000 0000 | 0x0000 2278 | 0x4003 2278
FSM_ST_MACHINE | RW | 32 | 0x0080 0500 | 0x0000 227C | 0x4003 227C
FSM_FLES | RW | 32 | 0x0000 0000 | 0x0000 2280 | 0x4003 2280
FSM_WR_ENA | RW | 32 | 0x0000 0002 | 0x0000 2288 | 0x4003 2288
FSM_ACC_PP | RO | 32 | 0x0000 0000 | 0x0000 228C | 0x4003 228C
FSM_ACC_EP | RO | 32 | 0x0000 0000 | 0x0000 2290 | 0x4003 2290
FSM_ADDR | RO | 32 | 0x0000 0000 | 0x0000 22A0 | 0x4003 22A0
FSM_SECTOR | RW | 32 | 0xFFFF 0000 | 0x0000 22A4 | 0x4003 22A4
FMC_REV_ID | RO | 32 | 0x0000 0000 | 0x0000 22A8 | 0x4003 22A8
FSM_ERR_ADDR | RO | 32 | 0x0000 0000 | 0x0000 22AC | 0x4003 22AC
FSM_PGM_MAXPUL | RO | 32 | 0x0000 0000 | 0x0000 22B0 | 0x4003 22B0
FSM_EXECUTE | RW | 32 | 0x000A 000A | 0x0000 22B4 | 0x4003 22B4
FSM_SECTOR1 | RW | 32 | 0xFFFF FFFF | 0x0000 22C0 | 0x4003 22C0
FSM_SECTOR2 | RW | 32 | 0x0000 0000 | 0x0000 22C4 | 0x4003 22C4
FSM_BSLE0 | RW | 32 | 0x0000 0000 | 0x0000 22E0 | 0x4003 22E0
FSM_BSLE1 | RW | 32 | 0x0000 0000 | 0x0000 22E4 | 0x4003 22E4
FSM_BSLP0 | RW | 32 | 0x0000 0000 | 0x0000 22F0 | 0x4003 22F0
FSM_BSLP1 | RW | 32 | 0x0000 0000 | 0x0000 22F4 | 0x4003 22F4
FCFG_BANK | RO | 32 | 0x0000 0401 | 0x0000 2400 | 0x4003 2400
FCFG_WRAPPER | RO | 32 | 0x5000 9007 | 0x0000 2404 | 0x4003 2404
FCFG_BNK_TYPE | RO | 32 | 0x0000 0003 | 0x0000 2408 | 0x4003 2408
FCFG_B0_START | RO | 32 | 0x0200 0000 | 0x0000 2410 | 0x4003 2410
FCFG_B1_START | RO | 32 | 0x0000 0000 | 0x0000 2414 | 0x4003 2414
FCFG_B2_START | RO | 32 | 0x0000 0000 | 0x0000 2418 | 0x4003 2418
FCFG_B3_START | RO | 32 | 0x0000 0000 | 0x0000 241C | 0x4003 241C
FCFG_B4_START | RO | 32 | 0x0000 0000 | 0x0000 2420 | 0x4003 2420
FCFG_B5_START | RO | 32 | 0x0000 0000 | 0x0000 2424 | 0x4003 2424
FCFG_B6_START | RO | 32 | 0x0000 0000 | 0x0000 2428 | 0x4003 2428
FCFG_B7_START | RO | 32 | 0x0000 0000 | 0x0000 242C | 0x4003 242C
FCFG_B0_SSIZE0 | RO | 32 | 0x0020 0004 | 0x0000 2430 | 0x4003 2430

### TOP:FLASH Register Descriptions

### TOP:FLASH:STAT

Address offset | 0x0000 001C
Physical address | 0x4003 001C | Instance | FLASH
Description | FMC and Efuse Status
Type | RO

Bits | Field Name | Description | Type | Reset
31:16 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0000
15 | EFUSE_BLANK | Efuse scanning detected if fuse ROM is blank: 0 : Not blank 1 : Blank | RO | 0
14 | EFUSE_TIMEOUT | Efuse scanning resulted in timeout error. 0 : No Timeout error 1 : Timeout Error | RO | 0
13 | EFUSE_CRC_ERROR | Efuse scanning resulted in scan chain CRC error. 0 : No CRC error 1 : CRC Error | RO | 0
12:8 | EFUSE_ERRCODE | Same as EFUSEERROR.CODE | RO | 0x00
7:3 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x00
2 | SAMHOLD_DIS | Status indicator of flash sample and hold sequencing logic. This bit will go to 1 some delay after CFG.DIS_IDLE is set to 1. 0: Not disabled 1: Sample and hold disabled and stable | RO | 0
1 | BUSY | Fast version of the FMC FMSTAT.BUSY bit. This flag is valid immediately after the operation setting it (FMSTAT.BUSY is delayed some cycles) 0 : Not busy 1 : Busy | RO | 0
0 | POWER_MODE | Power state of the flash sub-system. 0 : Active 1 : Low power | RO | 0

### TOP:FLASH:CFG

Address offset | 0x0000 0024
Physical address | 0x4003 0024 | Instance | FLASH
Description | Internal Register. Customers can control this through TI provided API
Type | RW

Bits | Field Name | Description | Type | Reset
31 | Reserved | Internal field controlled by TI provided startup code | RW | 0
30:9 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x00 0000
8 | STANDBY_MODE_SEL | Internal field controlled by TI provided startup code | RW | 0
7:6 | STANDBY_PW_SEL | Internal field controlled by TI provided startup code | RW | 0x0
5 | DIS_EFUSECLK | Internal field controlled by TI provided startup code | RW | 0
4 | DIS_READACCESS | Internal field controlled by TI provided startup code | RW | 0
3 | ENABLE_SWINTF | Internal field controlled by TI provided startup code | RW | 0
2 | Reserved | Internal field controlled by TI provided startup code | RW | 0
1 | DIS_STANDBY | Internal field controlled by TI provided startup code | RW | 0
0 | DIS_IDLE | Internal field controlled by TI provided startup code | RW | 0

### TOP:FLASH:SYSCODE_START

Address offset | 0x0000 0028
Physical address | 0x4003 0028 | Instance | FLASH
Description | Internal Register. Customers can control this through TI provided API
Type | RW

Bits | Field Name | Description | Type | Reset
31:5 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x000 0000
4:0 | SYSCODE_START | Internal | RW | 0x00

### TOP:FLASH:FLASH_SIZE

Address offset | 0x0000 002C
Physical address | 0x4003 002C | Instance | FLASH
Description | Internal Register. Customers can control this through TI provided API
Type | RW

Bits | Field Name | Description | Type | Reset
31:8 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x00 0000
7:0 | SECTORS | Internal field controlled by TI provided startup code | RW | 0x00

### TOP:FLASH:FWLOCK

Address offset | 0x0000 003C
Physical address | 0x4003 003C | Instance | FLASH
Description | Internal Register. Customers can control this through TI provided API
Type | RW

Bits | Field Name | Description | Type | Reset
31:3 | Reserved | Internal field controlled by TI provided startup code | RO | 0x0000 0000
2:0 | FWLOCK | Internal field controlled by TI provided startup code | RW | 0x0

### TOP:FLASH:FWFLAG

Address offset | 0x0000 0040
Physical address | 0x4003 0040 | Instance | FLASH
Description | Internal Register. Customers can control this through TI provided API
Type | RW

Bits | Field Name | Description | Type | Reset
31:3 | Reserved | Internal field controlled by TI provided startup code | RO | 0x0000 0000
2:0 | FWFLAG | Internal field controlled by TI provided startup code | RW | 0x0

### TOP:FLASH:EFUSE

Address offset | 0x0000 1000
Physical address | 0x4003 1000 | Instance | FLASH
Description | Internal Register. Customers can control this through TI provided API
Type | RW

Bits | Field Name | Description | Type | Reset
31:29 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0
28:24 | INSTRUCTION | Internal | RW | 0x00
23:16 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x00
15:0 | DUMPWORD | Internal | RW | 0x0000

### TOP:FLASH:EFUSEADDR

Address offset | 0x0000 1004
Physical address | 0x4003 1004 | Instance | FLASH
Description | Internal Register. Customers can control this through TI provided API
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0000
15:11 | BLOCK | Internal | RW | 0x00
10:0 | ROW | Internal | RW | 0x000

### TOP:FLASH:DATAUPPER

Address offset | 0x0000 1008
Physical address | 0x4003 1008 | Instance | FLASH
Description | Internal Register. Customers can control this through TI provided API
Type | RW

Bits | Field Name | Description | Type | Reset
31:8 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x00 0000
7:3 | SPARE | Internal | RW | 0x00
2 | P | Internal | RW | 0
1 | R | Internal | RW | 0
0 | EEN | Internal | RW | 0

### TOP:FLASH:DATALOWER

Address offset | 0x0000 100C
Physical address | 0x4003 100C | Instance | FLASH
Description | Internal Register. Customers can control this through TI provided API
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | DATA | Internal | RW | 0x0000 0000

### TOP:FLASH:EFUSECFG

Address offset | 0x0000 1010
Physical address | 0x4003 1010 | Instance | FLASH
Description | Internal Register. Customers can control this through TI provided API
Type | RW

Bits | Field Name | Description | Type | Reset
31:14 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0 0000
13:12 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0
11:9 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0
8 | IDLEGATING | Internal | RW | 0
7 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0
6 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0
5 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0
4:3 | SLAVEPOWER | Internal | RW | 0x0
2 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0
1 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0
0 | GATING | Internal | RW | 1

### TOP:FLASH:EFUSESTAT

Address offset | 0x0000 1014
Physical address | 0x4003 1014 | Instance | FLASH
Description | Internal Register. Customers can control this through TI provided API
Type | RO

Bits | Field Name | Description | Type | Reset
31:1 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0000 0000
0 | RESETDONE | Internal | RO | 1

### TOP:FLASH:ACC

Address offset | 0x0000 1018
Physical address | 0x4003 1018 | Instance | FLASH
Description | Internal Register. Customers can control this through TI provided API
Type | RO

Bits | Field Name | Description | Type | Reset
31:24 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x00
23:0 | ACCUMULATOR | Internal | RO | 0x00 0000

### TOP:FLASH:BOUNDARY

Address offset | 0x0000 101C
Physical address | 0x4003 101C | Instance | FLASH
Description | Internal Register. Customers can control this through TI provided API
Type | RW

Bits | Field Name | Description | Type | Reset
31:24 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x00
23 | DISROW0 | Internal | RW | 0
22 | SPARE | Internal | RW | 0
21 | EFC_SELF_TEST_ERROR | Internal | RW | 0
20 | EFC_INSTRUCTION_INFO | Internal | RW | 0
19 | EFC_INSTRUCTION_ERROR | Internal | RW | 0
18 | EFC_AUTOLOAD_ERROR | Internal | RW | 0
17:14 | OUTPUTENABLE | Internal | RW | 0x0
13 | YS_ECC_SELF_TEST_EN | Internal | RW | 0
12 | SYS_ECC_OVERRIDE_EN | Internal | RW | 0
11 | EFC_FDI | Internal | RW | 0
10 | SYS_DIEID_AUTOLOAD_EN | Internal | RW | 0
9:8 | SYS_REPAIR_EN | Internal | RW | 0x0
7:4 | SYS_WS_READ_STATES | Internal | RW | 0x0
3:0 | INPUTENABLE | Internal | RW | 0x0

### TOP:FLASH:EFUSEFLAG

Address offset | 0x0000 1020
Physical address | 0x4003 1020 | Instance | FLASH
Description | Internal Register. Customers can control this through TI provided API
Type | RO

Bits | Field Name | Description | Type | Reset
31:1 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0000 0000
0 | KEY | Internal | RO | 0

### TOP:FLASH:EFUSEKEY

Address offset | 0x0000 1024
Physical address | 0x4003 1024 | Instance | FLASH
Description | Internal Register. Customers can control this through TI provided API
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | CODE | Internal | RW | 0x0000 0000

### TOP:FLASH:EFUSERELEASE

Address offset | 0x0000 1028
Physical address | 0x4003 1028 | Instance | FLASH
Description | Internal Register. Customers can control this through TI provided API
Type | RO

Bits | Field Name | Description | Type | Reset
31:25 | ODPYEAR | Internal | RO | 0x00
24:21 | ODPMONTH | Internal | RO | 0x0
20:16 | ODPDAY | Internal | RO | 0x00
15:9 | EFUSEYEAR | Internal | RO | 0x00
8:5 | EFUSEMONTH | Internal | RO | 0x0
4:0 | EFUSEDAY | Internal | RO | 0x00

### TOP:FLASH:EFUSEPINS

Address offset | 0x0000 102C
Physical address | 0x4003 102C | Instance | FLASH
Description | Internal Register. Customers can control this through TI provided API
Type | RO

Bits | Field Name | Description | Type | Reset
31:16 | RESERVED16 | Internal | RO | 0x0000
15 | EFC_SELF_TEST_DONE | Internal | RO | 0
14 | EFC_SELF_TEST_ERROR | Internal | RO | 0
13 | SYS_ECC_SELF_TEST_EN | Internal | RO | 0
12 | EFC_INSTRUCTION_INFO | Internal | RO | 0
11 | EFC_INSTRUCTION_ERROR | Internal | RO | 0
10 | EFC_AUTOLOAD_ERROR | Internal | RO | 0
9 | SYS_ECC_OVERRIDE_EN | Internal | RO | 0
8 | EFC_READY | Internal | RO | 0
7 | EFC_FCLRZ | Internal | RO | 0
6 | SYS_DIEID_AUTOLOAD_EN | Internal | RO | 0
5:4 | SYS_REPAIR_EN | Internal | RO | 0x0
3:0 | SYS_WS_READ_STATES | Internal | RO | 0x0

### TOP:FLASH:EFUSECRA

Address offset | 0x0000 1030
Physical address | 0x4003 1030 | Instance | FLASH
Description | Internal Register. Customers can control this through TI provided API
Type | RW

Bits | Field Name | Description | Type | Reset
31:6 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x000 0000
5:0 | DATA | Internal | RW | 0x00

### TOP:FLASH:EFUSEREAD

Address offset | 0x0000 1034
Physical address | 0x4003 1034 | Instance | FLASH
Description | Internal Register. Customers can control this through TI provided API
Type | RW

Bits | Field Name | Description | Type | Reset
31:10 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x00 0000
9:8 | DATABIT | Internal | RW | 0x0
7:4 | READCLOCK | Internal | RW | 0x0
3 | DEBUG | Internal | RW | 0
2 | SPARE | Internal | RW | 0
1:0 | MARGIN | Internal | RW | 0x0

### TOP:FLASH:EFUSEPROGRAM

Address offset | 0x0000 1038
Physical address | 0x4003 1038 | Instance | FLASH
Description | Internal Register. Customers can control this through TI provided API
Type | RW

Bits | Field Name | Description | Type | Reset
31 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0
30 | COMPAREDISABLE | Internal | RW | 0
29:14 | CLOCKSTALL | Internal | RW | 0x0000
13 | VPPTOVDD | Internal | RW | 0
12:9 | ITERATIONS | Internal | RW | 0x0
8:0 | WRITECLOCK | Internal | RW | 0x000

### TOP:FLASH:EFUSEERROR

Address offset | 0x0000 103C
Physical address | 0x4003 103C | Instance | FLASH
Description | Internal Register. Customers can control this through TI provided API
Type | RW

Bits | Field Name | Description | Type | Reset
31:6 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x000 0000
5 | DONE | Internal | RW | 0
4:0 | CODE | Internal | RW | 0x00

### TOP:FLASH:SINGLEBIT

Address offset | 0x0000 1040
Physical address | 0x4003 1040 | Instance | FLASH
Description | Internal Register. Customers can control this through TI provided API
Type | RO

Bits | Field Name | Description | Type | Reset
31:1 | FROMN | Internal | RO | 0x0000 0000
0 | FROM0 | Internal | RO | 0

### TOP:FLASH:TWOBIT

Address offset | 0x0000 1044
Physical address | 0x4003 1044 | Instance | FLASH
Description | Internal Register. Customers can control this through TI provided API
Type | RO

Bits | Field Name | Description | Type | Reset
31:1 | FROMN | Internal | RO | 0x0000 0000
0 | FROM0 | Internal | RO | 0

### TOP:FLASH:SELFTESTCYC

Address offset | 0x0000 1048
Physical address | 0x4003 1048 | Instance | FLASH
Description | Internal Register. Customers can control this through TI provided API
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | CYCLES | Internal | RW | 0x0000 0000

### TOP:FLASH:SELFTESTSIGN

Address offset | 0x0000 104C
Physical address | 0x4003 104C | Instance | FLASH
Description | Internal Register. Customers can control this through TI provided API
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | SIGNATURE | Internal | RW | 0x0000 0000

### TOP:FLASH:FRDCTL

Address offset | 0x0000 2000
Physical address | 0x4003 2000 | Instance | FLASH
Description | Internal Register. Customers can control this through TI provided API
Type | RW

Bits | Field Name | Description | Type | Reset
31:28 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0
27:24 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0
23:17 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x00
16 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0
15:12 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0
11:8 | RWAIT | Internal field controlled by TI provided startup code | RW | 0x2
7:5 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0
4 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0
3:1 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0
0 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0

### TOP:FLASH:FSPRD

Address offset | 0x0000 2004
Physical address | 0x4003 2004 | Instance | FLASH
Description | Internal Register. Customers can control this through TI provided API
Type | RW

Bits | Field Name | Description | Type | Reset
31:28 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0
27:24 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0
23:17 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x00
16 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0
15:8 | RMBSEM | Internal | RW | 0x00
7:2 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x00
1 | RM1 | Internal | RW | 0
0 | RM0 | Internal | RW | 0

### TOP:FLASH:FEDACCTL1

Address offset | 0x0000 2008
Physical address | 0x4003 2008 | Instance | FLASH
Description | Internal Register. Customers can control this through TI provided API
Type | RW

Bits | Field Name | Description | Type | Reset
31:25 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x00
24 | SUSP_IGNR | Internal | RW | 0
23:20 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0
19:16 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0
15:11 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x00
10 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0
9 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0
8 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0
7:6 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0
5 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0
4 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0
3:0 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0

### TOP:FLASH:FEDACSTAT

Address offset | 0x0000 201C
Physical address | 0x4003 201C | Instance | FLASH
Description | Internal Register. Customers can control this through TI provided API
Type | RW

Bits | Field Name | Description | Type | Reset
31:26 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x00
25 | RVF_INT | Internal | RW | 0
24 | FSM_DONE | Internal | RW | 0
23 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0
22 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0
21 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0
20 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0
19 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0
18 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0
17 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0
16 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0
15:14 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0
13 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0
12 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0
11 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0
10 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0
9 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0
8 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0
7 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0
6 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0
5 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0
4 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0
3 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0
2 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0
1 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0
0 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0

### TOP:FLASH:FBPROT

Address offset | 0x0000 2030
Physical address | 0x4003 2030 | Instance | FLASH
Description | Internal Register. Customers can control this through TI provided API
Type | RW

Bits | Field Name | Description | Type | Reset
31:1 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0000 0000
0 | PROTL1DIS | Internal | RW | 0

### TOP:FLASH:FBSE

Address offset | 0x0000 2034
Physical address | 0x4003 2034 | Instance | FLASH
Description | Internal Register. Customers can control this through TI provided API
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0000
15:0 | BSE | Internal | RW | 0x0000

### TOP:FLASH:FBBUSY

Address offset | 0x0000 2038
Physical address | 0x4003 2038 | Instance | FLASH
Description | Internal Register. Customers can control this through TI provided API
Type | RO

Bits | Field Name | Description | Type | Reset
31:8 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x00 0000
7:0 | BUSY | Internal | RO | 0xFE

### TOP:FLASH:FBAC

Address offset | 0x0000 203C
Physical address | 0x4003 203C | Instance | FLASH
Description | Internal Register. Customers can control this through TI provided API
Type | RW

Bits | Field Name | Description | Type | Reset
31:24 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x00
23:17 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x00
16 | OTPPROTDIS | Internal | RW | 0
15:8 | BAGP | Internal | RW | 0x00
7:0 | VREADS | Internal | RW | 0x0F

### TOP:FLASH:FBFALLBACK

Address offset | 0x0000 2040
Physical address | 0x4003 2040 | Instance | FLASH
Description | Internal Register. Customers can control this through TI provided API
Type | RW

Bits | Field Name | Description | Type | Reset
31:28 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0
27:24 | FSM_PWRSAV | Internal | RW | 0x5
23:20 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0
19:16 | REG_PWRSAV | Internal | RW | 0x5
15:14 | BANKPWR7 | Internal | RW | 0x3
13:12 | BANKPWR6 | Internal | RW | 0x3
11:10 | BANKPWR5 | Internal | RW | 0x3
9:8 | BANKPWR4 | Internal | RW | 0x3
7:6 | BANKPWR3 | Internal | RW | 0x3
5:4 | BANKPWR2 | Internal | RW | 0x3
3:2 | BANKPWR1 | Internal | RW | 0x3
1:0 | BANKPWR0 | Internal | RW | 0x3

### TOP:FLASH:FBPRDY

Address offset | 0x0000 2044
Physical address | 0x4003 2044 | Instance | FLASH
Description | Internal Register. Customers can control this through TI provided API
Type | RO

Bits | Field Name | Description | Type | Reset
31:24 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x00
23:17 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x7F
16 | BANKBUSY | Internal | RO | 1
15 | PUMPRDY | Internal | RO | 0
14:8 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x00
7:1 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x7F
0 | BANKRDY | Internal | RO | 0

### TOP:FLASH:FPAC1

Address offset | 0x0000 2048
Physical address | 0x4003 2048 | Instance | FLASH
Description | Internal Register. Customers can control this through TI provided API
Type | RW

Bits | Field Name | Description | Type | Reset
31:28 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0
27:16 | PSLEEPTDIS | Internal | RW | 0x208
15:4 | PUMPRESET_PW | Internal | RW | 0x208
3:2 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0
1:0 | PUMPPWR | Internal | RW | 0x1

### TOP:FLASH:FPAC2

Address offset | 0x0000 204C
Physical address | 0x4003 204C | Instance | FLASH
Description | Internal Register. Customers can control this through TI provided API
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0000
15:0 | PAGP | Internal | RW | 0x0000

### TOP:FLASH:FMAC

Address offset | 0x0000 2050
Physical address | 0x4003 2050 | Instance | FLASH
Description | Internal Register. Customers can control this through TI provided API
Type | RW

Bits | Field Name | Description | Type | Reset
31:3 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0000 0000
2:0 | BANK | Internal | RW | 0x0

### TOP:FLASH:FMSTAT

Address offset | 0x0000 2054
Physical address | 0x4003 2054 | Instance | FLASH
Description | Internal Register. Customers can control this through TI provided API
Type | RO

Bits | Field Name | Description | Type | Reset
31:18 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0000
17 | RVSUSP | Internal | RO | 0
16 | RDVER | Internal | RO | 0
15 | RVF | Internal | RO | 0
14 | ILA | Internal | RO | 0
13 | DBF | Internal | RO | 0
12 | PGV | Internal | RO | 0
11 | PCV | Internal | RO | 0
10 | EV | Internal | RO | 0
9 | CV | Internal | RO | 0
8 | BUSY | Internal | RO | 0
7 | ERS | Internal | RO | 0
6 | PGM | Internal | RO | 0
5 | INVDAT | Internal | RO | 0
4 | CSTAT | Internal | RO | 0
3 | VOLSTAT | Internal | RO | 0
2 | ESUSP | Internal | RO | 0
1 | PSUSP | Internal | RO | 0
0 | SLOCK | Internal | RO | 0

### TOP:FLASH:FLOCK

Address offset | 0x0000 2064
Physical address | 0x4003 2064 | Instance | FLASH
Description | Internal Register. Customers can control this through TI provided API
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0000
15:0 | ENCOM | Internal | RW | 0x55AA

### TOP:FLASH:FVREADCT

Address offset | 0x0000 2080
Physical address | 0x4003 2080 | Instance | FLASH
Description | Internal Register. Customers can control this through TI provided API
Type | RW

Bits | Field Name | Description | Type | Reset
31:4 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x000 0000
3:0 | VREADCT | Internal field controlled by TI provided startup code | RW | 0x8

### TOP:FLASH:FVHVCT1

Address offset | 0x0000 2084
Physical address | 0x4003 2084 | Instance | FLASH
Description | Internal Register. Customers can control this through TI provided API
Type | RW

Bits | Field Name | Description | Type | Reset
31:24 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x00
23:20 | TRIM13_E | Internal field controlled by TI provided startup code | RW | 0x8
19:16 | VHVCT_E | Internal field controlled by TI provided startup code | RW | 0x4
15:8 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x00
7:4 | TRIM13_PV | Internal field controlled by TI provided startup code | RW | 0x8
3:0 | VHVCT_PV | Internal field controlled by TI provided startup code | RW | 0x8

### TOP:FLASH:FVHVCT2

Address offset | 0x0000 2088
Physical address | 0x4003 2088 | Instance | FLASH
Description | Internal Register. Customers can control this through TI provided API
Type | RW

Bits | Field Name | Description | Type | Reset
31:24 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x00
23:20 | TRIM13_P | Internal field controlled by TI provided startup code | RW | 0xA
19:16 | VHVCT_P | Internal field controlled by TI provided startup code | RW | 0x2
15:0 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0000

### TOP:FLASH:FVHVCT3

Address offset | 0x0000 208C
Physical address | 0x4003 208C | Instance | FLASH
Description | Internal Register. Customers can control this through TI provided API
Type | RW

Bits | Field Name | Description | Type | Reset
31:20 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x000
19:16 | WCT | Internal | RW | 0xF
15:4 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x000
3:0 | VHVCT_READ | Internal | RW | 0x0

### TOP:FLASH:FVNVCT

Address offset | 0x0000 2090
Physical address | 0x4003 2090 | Instance | FLASH
Description | Internal Register. Customers can control this through TI provided API
Type | RW

Bits | Field Name | Description | Type | Reset
31:13 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0 0000
12:8 | VCG2P5CT | Internal field controlled by TI provided startup code | RW | 0x08
7:5 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0
4:0 | VIN_CT | Internal | RW | 0x00

### TOP:FLASH:FVSLP

Address offset | 0x0000 2094
Physical address | 0x4003 2094 | Instance | FLASH
Description | Internal Register. Customers can control this through TI provided API
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0000
15:12 | VSL_P | Internal field controlled by TI provided startup code | RW | 0x8
11:0 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x000

### TOP:FLASH:FVWLCT

Address offset | 0x0000 2098
Physical address | 0x4003 2098 | Instance | FLASH
Description | Internal Register. Customers can control this through TI provided API
Type | RW

Bits | Field Name | Description | Type | Reset
31:5 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x000 0000
4:0 | VWLCT_P | Internal field controlled by TI provided startup code | RW | 0x08

### TOP:FLASH:FEFUSECTL

Address offset | 0x0000 209C
Physical address | 0x4003 209C | Instance | FLASH
Description | Internal Register. Customers can control this through TI provided API
Type | RW

Bits | Field Name | Description | Type | Reset
31:27 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x00
26:24 | CHAIN_SEL | Internal | RW | 0x7
23:18 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x00
17 | WRITE_EN | Internal | RW | 0
16 | BP_SEL | Internal | RW | 1
15:9 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x00
8 | EF_CLRZ | Internal | RW | 1
7:5 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0
4 | EF_TEST | Internal | RW | 0
3:0 | EFUSE_EN | Internal | RW | 0xA

### TOP:FLASH:FEFUSESTAT

Address offset | 0x0000 20A0
Physical address | 0x4003 20A0 | Instance | FLASH
Description | Internal Register. Customers can control this through TI provided API
Type | RW

Bits | Field Name | Description | Type | Reset
31:1 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0000 0000
0 | SHIFT_DONE | Internal | RW | 0

### TOP:FLASH:FEFUSEDATA

Address offset | 0x0000 20A4
Physical address | 0x4003 20A4 | Instance | FLASH
Description | Internal Register. Customers can control this through TI provided API
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | FEFUSEDATA | Internal | RW | 0x0000 0000

### TOP:FLASH:FSEQPMP

Address offset | 0x0000 20A8
Physical address | 0x4003 20A8 | Instance | FLASH
Description | Internal Register. Customers can control this through TI provided API
Type | RW

Bits | Field Name | Description | Type | Reset
31:28 | RESERVED28 | Internal | RW | 0x8
27:24 | TRIM_3P4 | Internal field controlled by TI provided startup code | RW | 0x5
23:22 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0
21:20 | TRIM_1P7 | Internal field controlled by TI provided startup code | RW | 0x0
19:16 | TRIM_0P8 | Internal field controlled by TI provided startup code | RW | 0x8
15 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0
14:12 | VIN_AT_X | Internal | RW | 0x0
11:9 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0
8 | VIN_BY_PASS | Internal field controlled by TI provided startup code | RW | 0
7:0 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text) | RW | 0x00

### TOP:FLASH:FBSTROBES

Address offset | 0x0000 2100
Physical address | 0x4003 2100 | Instance | FLASH
Description | Internal Register. Customers can control this through TI provided API
Type | RW

Bits | Field Name | Description | Type | Reset
31:25 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x00
24 | ECBIT | Internal | RW | 0
23:19 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x00
18 | RWAIT2_FLCLK | Internal | RW | 0
17 | RWAIT_FLCLK | Internal | RW | 0
16 | FLCLKEN | Internal | RW | 0
15:9 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x00
8 | CTRLENZ | Internal | RW | 1
7 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0
6 | NOCOLRED | Internal | RW | 0
5 | PRECOL | Internal | RW | 0
4 | TI_OTP | Internal | RW | 0
3 | OTP | Internal | RW | 0
2 | TEZ | Internal | RW | 1
1:0 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0

### TOP:FLASH:FPSTROBES

Address offset | 0x0000 2104
Physical address | 0x4003 2104 | Instance | FLASH
Description | Internal Register. Customers can control this through TI provided API
Type | RW

Bits | Field Name | Description | Type | Reset
31:9 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x00 0000
8 | EXECUTEZ | Internal | RW | 1
7:2 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x00
1 | V3PWRDNZ | Internal | RW | 1
0 | V5PWRDNZ | Internal | RW | 1

### TOP:FLASH:FBMODE

Address offset | 0x0000 2108
Physical address | 0x4003 2108 | Instance | FLASH
Description | Internal Register. Customers can control this through TI provided API
Type | RW

Bits | Field Name | Description | Type | Reset
31:3 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0000 0000
2:0 | MODE | Internal | RW | 0x0

### TOP:FLASH:FTCR

Address offset | 0x0000 210C
Physical address | 0x4003 210C | Instance | FLASH
Description | Internal Register. Customers can control this through TI provided API
Type | RW

Bits | Field Name | Description | Type | Reset
31:7 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x000 0000
6:0 | TCR | Internal | RW | 0x00

### TOP:FLASH:FADDR

Address offset | 0x0000 2110
Physical address | 0x4003 2110 | Instance | FLASH
Description | Internal Register. Customers can control this through TI provided API
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | FADDR | Internal | RW | 0x0000 0000

### TOP:FLASH:FTCTL

Address offset | 0x0000 211C
Physical address | 0x4003 211C | Instance | FLASH
Description | Internal Register. Customers can control this through TI provided API
Type | RW

Bits | Field Name | Description | Type | Reset
31:25 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x00
24 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0
23:17 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x00
16 | WDATA_BLK_CLR | Internal | RW | 0
15:2 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0000
1 | TEST_EN | Internal | RW | 0
0 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0

### TOP:FLASH:FWPWRITE0

Address offset | 0x0000 2120
Physical address | 0x4003 2120 | Instance | FLASH
Description | Internal Register. Customers can control this through TI provided API
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | FWPWRITE0 | Internal | RW | 0xFFFF FFFF

### TOP:FLASH:FWPWRITE1

Address offset | 0x0000 2124
Physical address | 0x4003 2124 | Instance | FLASH
Description | Internal Register. Customers can control this through TI provided API
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | FWPWRITE1 | Internal | RW | 0xFFFF FFFF

### TOP:FLASH:FWPWRITE2

Address offset | 0x0000 2128
Physical address | 0x4003 2128 | Instance | FLASH
Description | Internal Register. Customers can control this through TI provided API
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | FWPWRITE2 | Internal | RW | 0xFFFF FFFF

### TOP:FLASH:FWPWRITE3

Address offset | 0x0000 212C
Physical address | 0x4003 212C | Instance | FLASH
Description | Internal Register. Customers can control this through TI provided API
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | FWPWRITE3 | Internal | RW | 0xFFFF FFFF

### TOP:FLASH:FWPWRITE4

Address offset | 0x0000 2130
Physical address | 0x4003 2130 | Instance | FLASH
Description | Internal Register. Customers can control this through TI provided API
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | FWPWRITE4 | Internal | RW | 0xFFFF FFFF

### TOP:FLASH:FWPWRITE5

Address offset | 0x0000 2134
Physical address | 0x4003 2134 | Instance | FLASH
Description | Internal Register. Customers can control this through TI provided API
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | FWPWRITE5 | Internal | RW | 0xFFFF FFFF

### TOP:FLASH:FWPWRITE6

Address offset | 0x0000 2138
Physical address | 0x4003 2138 | Instance | FLASH
Description | Internal Register. Customers can control this through TI provided API
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | FWPWRITE6 | Internal | RW | 0xFFFF FFFF

### TOP:FLASH:FWPWRITE7

Address offset | 0x0000 213C
Physical address | 0x4003 213C | Instance | FLASH
Description | Internal Register. Customers can control this through TI provided API
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | FWPWRITE7 | Internal | RW | 0xFFFF FFFF

### TOP:FLASH:FWPWRITE_ECC

Address offset | 0x0000 2140
Physical address | 0x4003 2140 | Instance | FLASH
Description | Internal Register. Customers can control this through TI provided API
Type | RW

Bits | Field Name | Description | Type | Reset
31:24 | ECCBYTES07_00 | Internal | RW | 0xFF
23:16 | ECCBYTES15_08 | Internal | RW | 0xFF
15:8 | ECCBYTES23_16 | Internal | RW | 0xFF
7:0 | ECCBYTES31_24 | Internal | RW | 0xFF

### TOP:FLASH:FSWSTAT

Address offset | 0x0000 2144
Physical address | 0x4003 2144 | Instance | FLASH
Description | Internal Register. Customers can control this through TI provided API
Type | RO

Bits | Field Name | Description | Type | Reset
31:1 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0000 0000
0 | SAFELV | Internal | RO | 1

### TOP:FLASH:FSM_GLBCTL

Address offset | 0x0000 2200
Physical address | 0x4003 2200 | Instance | FLASH
Description | Internal Register. Customers can control this through TI provided API
Type | RO

Bits | Field Name | Description | Type | Reset
31:1 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0000 0000
0 | CLKSEL | Internal | RO | 1

### TOP:FLASH:FSM_STATE

Address offset | 0x0000 2204
Physical address | 0x4003 2204 | Instance | FLASH
Description | Internal Register. Customers can control this through TI provided API
Type | RO

Bits | Field Name | Description | Type | Reset
31:12 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0 0000
11 | CTRLENZ | Internal | RO | 1
10 | EXECUTEZ | Internal | RO | 1
9 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0
8 | FSM_ACT | Internal | RO | 0
7 | TIOTP_ACT | Internal | RO | 0
6 | OTP_ACT | Internal | RO | 0
5:0 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x00

### TOP:FLASH:FSM_STAT

Address offset | 0x0000 2208
Physical address | 0x4003 2208 | Instance | FLASH
Description | Internal Register. Customers can control this through TI provided API
Type | RO

Bits | Field Name | Description | Type | Reset
31:3 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0000 0000
2 | NON_OP | Internal | RO | 1
1 | OVR_PUL_CNT | Internal | RO | 0
0 | INV_DAT | Internal | RO | 0

### TOP:FLASH:FSM_CMD

Address offset | 0x0000 220C
Physical address | 0x4003 220C | Instance | FLASH
Description | Internal Register. Customers can control this through TI provided API
Type | RW

Bits | Field Name | Description | Type | Reset
31:6 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x000 0000
5:0 | FSMCMD | Internal | RW | 0x00

### TOP:FLASH:FSM_PE_OSU

Address offset | 0x0000 2210
Physical address | 0x4003 2210 | Instance | FLASH
Description | Internal Register. Customers can control this through TI provided API
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0000
15:8 | PGM_OSU | Internal field controlled by TI provided startup code | RW | 0x00
7:0 | ERA_OSU | Internal field controlled by TI provided startup code | RW | 0x00

### TOP:FLASH:FSM_VSTAT

Address offset | 0x0000 2214
Physical address | 0x4003 2214 | Instance | FLASH
Description | Internal Register. Customers can control this through TI provided API
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0000
15:12 | VSTAT_CNT | Internal field controlled by TI provided startup code | RW | 0x3
11:0 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x000

### TOP:FLASH:FSM_PE_VSU

Address offset | 0x0000 2218
Physical address | 0x4003 2218 | Instance | FLASH
Description | Internal Register. Customers can control this through TI provided API
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0000
15:8 | PGM_VSU | Internal field controlled by TI provided startup code | RW | 0x00
7:0 | ERA_VSU | Internal field controlled by TI provided startup code | RW | 0x00

### TOP:FLASH:FSM_CMP_VSU

Address offset | 0x0000 221C
Physical address | 0x4003 221C | Instance | FLASH
Description | Internal Register. Customers can control this through TI provided API
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0000
15:12 | ADD_EXZ | Internal field controlled by TI provided startup code | RW | 0x0
11:0 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x000

### TOP:FLASH:FSM_EX_VAL

Address offset | 0x0000 2220
Physical address | 0x4003 2220 | Instance | FLASH
Description | Internal Register. Customers can control this through TI provided API
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0000
15:8 | REP_VSU | Internal field controlled by TI provided startup code | RW | 0x03
7:0 | EXE_VALD | Internal field controlled by TI provided startup code | RW | 0x01

### TOP:FLASH:FSM_RD_H

Address offset | 0x0000 2224
Physical address | 0x4003 2224 | Instance | FLASH
Description | Internal Register. Customers can control this through TI provided API
Type | RW

Bits | Field Name | Description | Type | Reset
31:8 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x00 0000
7:0 | RD_H | Internal field controlled by TI provided startup code | RW | 0x5A

### TOP:FLASH:FSM_P_OH

Address offset | 0x0000 2228
Physical address | 0x4003 2228 | Instance | FLASH
Description | Internal Register. Customers can control this through TI provided API
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0000
15:8 | PGM_OH | Internal field controlled by TI provided startup code | RW | 0x01
7:0 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x00

### TOP:FLASH:FSM_ERA_OH

Address offset | 0x0000 222C
Physical address | 0x4003 222C | Instance | FLASH
Description | Internal Register. Customers can control this through TI provided API
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0000
15:0 | ERA_OH | Internal field controlled by TI provided startup code | RW | 0x0001

### TOP:FLASH:FSM_SAV_PPUL

Address offset | 0x0000 2230
Physical address | 0x4003 2230 | Instance | FLASH
Description | Internal Register. Customers can control this through TI provided API
Type | RO

Bits | Field Name | Description | Type | Reset
31:12 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0 0000
11:0 | SAV_P_PUL | Internal | RO | 0x000

### TOP:FLASH:FSM_PE_VH

Address offset | 0x0000 2234
Physical address | 0x4003 2234 | Instance | FLASH
Description | Internal Register. Customers can control this through TI provided API
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0000
15:8 | PGM_VH | Internal field controlled by TI provided startup code | RW | 0x01
7:0 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x00

### TOP:FLASH:FSM_PRG_PW

Address offset | 0x0000 2240
Physical address | 0x4003 2240 | Instance | FLASH
Description | Internal Register. Customers can control this through TI provided API
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0000
15:0 | PROG_PUL_WIDTH | Internal field controlled by TI provided startup code | RW | 0x0000

### TOP:FLASH:FSM_ERA_PW

Address offset | 0x0000 2244
Physical address | 0x4003 2244 | Instance | FLASH
Description | Internal Register. Customers can control this through TI provided API
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | FSM_ERA_PW | Internal field controlled by TI provided startup code | RW | 0x0000 0000

### TOP:FLASH:FSM_SAV_ERA_PUL

Address offset | 0x0000 2254
Physical address | 0x4003 2254 | Instance | FLASH
Description | Internal Register. Customers can control this through TI provided API
Type | RO

Bits | Field Name | Description | Type | Reset
31:12 | RESERVED12 | Internal | RO | 0x0 0000
11:0 | SAV_ERA_PUL | Internal | RO | 0x000

### TOP:FLASH:FSM_TIMER

Address offset | 0x0000 2258
Physical address | 0x4003 2258 | Instance | FLASH
Description | Internal Register. Customers can control this through TI provided API
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | FSM_TIMER | Internal | RO | 0x0000 0000

### TOP:FLASH:FSM_MODE

Address offset | 0x0000 225C
Physical address | 0x4003 225C | Instance | FLASH
Description | Internal Register. Customers can control this through TI provided API
Type | RO

Bits | Field Name | Description | Type | Reset
31:20 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x000
19:18 | RDV_SUBMODE | Internal | RO | 0x0
17:16 | PGM_SUBMODE | Internal | RO | 0x0
15:14 | ERA_SUBMODE | Internal | RO | 0x0
13:12 | SUBMODE | Internal | RO | 0x0
11:9 | SAV_PGM_CMD | Internal | RO | 0x0
8:6 | SAV_ERA_MODE | Internal | RO | 0x0
5:3 | MODE | Internal | RO | 0x0
2:0 | CMD | Internal | RO | 0x0

### TOP:FLASH:FSM_PGM

Address offset | 0x0000 2260
Physical address | 0x4003 2260 | Instance | FLASH
Description | Internal Register. Customers can control this through TI provided API
Type | RO

Bits | Field Name | Description | Type | Reset
31:26 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x00
25:23 | PGM_BANK | Internal | RO | 0x0
22:0 | PGM_ADDR | Internal | RO | 0x00 0000

### TOP:FLASH:FSM_ERA

Address offset | 0x0000 2264
Physical address | 0x4003 2264 | Instance | FLASH
Description | Internal Register. Customers can control this through TI provided API
Type | RO

Bits | Field Name | Description | Type | Reset
31:26 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x00
25:23 | ERA_BANK | Internal | RO | 0x0
22:0 | ERA_ADDR | Internal | RO | 0x00 0000

### TOP:FLASH:FSM_PRG_PUL

Address offset | 0x0000 2268
Physical address | 0x4003 2268 | Instance | FLASH
Description | Internal Register. Customers can control this through TI provided API
Type | RW

Bits | Field Name | Description | Type | Reset
31:20 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x000
19:16 | BEG_EC_LEVEL | Internal field controlled by TI provided startup code | RW | 0x4
15:12 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0
11:0 | MAX_PRG_PUL | Internal field controlled by TI provided startup code | RW | 0x032

### TOP:FLASH:FSM_ERA_PUL

Address offset | 0x0000 226C
Physical address | 0x4003 226C | Instance | FLASH
Description | Internal Register. Customers can control this through TI provided API
Type | RW

Bits | Field Name | Description | Type | Reset
31:20 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x000
19:16 | MAX_EC_LEVEL | Internal field controlled by TI provided startup code | RW | 0x4
15:12 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0
11:0 | MAX_ERA_PUL | Internal field controlled by TI provided startup code | RW | 0xBB8

### TOP:FLASH:FSM_STEP_SIZE

Address offset | 0x0000 2270
Physical address | 0x4003 2270 | Instance | FLASH
Description | Internal Register. Customers can control this through TI provided API
Type | RW

Bits | Field Name | Description | Type | Reset
31:25 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x00
24:16 | EC_STEP_SIZE | Internal field controlled by TI provided startup code | RW | 0x000
15:0 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0000

### TOP:FLASH:FSM_PUL_CNTR

Address offset | 0x0000 2274
Physical address | 0x4003 2274 | Instance | FLASH
Description | Internal Register. Customers can control this through TI provided API
Type | RO

Bits | Field Name | Description | Type | Reset
31:25 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x00
24:16 | CUR_EC_LEVEL | Internal | RO | 0x000
15:12 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0
11:0 | PUL_CNTR | Internal | RO | 0x000

### TOP:FLASH:FSM_EC_STEP_HEIGHT

Address offset | 0x0000 2278
Physical address | 0x4003 2278 | Instance | FLASH
Description | Internal Register. Customers can control this through TI provided API
Type | RW

Bits | Field Name | Description | Type | Reset
31:4 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x000 0000
3:0 | EC_STEP_HEIGHT | Internal field controlled by TI provided startup code | RW | 0x0

### TOP:FLASH:FSM_ST_MACHINE

Address offset | 0x0000 227C
Physical address | 0x4003 227C | Instance | FLASH
Description | Internal Register. Customers can control this through TI provided API
Type | RW

Bits | Field Name | Description | Type | Reset
31:24 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x00
23 | DO_PRECOND | Internal field controlled by TI provided startup code | RW | 1
22 | FSM_INT_EN | Internal | RW | 0
21 | ALL_BANKS | Internal | RW | 0
20 | CMPV_ALLOWED | Internal | RW | 0
19 | RANDOM | Internal | RW | 0
18 | RV_SEC_EN | Internal | RW | 0
17 | RV_RES | Internal | RW | 0
16 | RV_INT_EN | Internal | RW | 0
15 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0
14 | ONE_TIME_GOOD | Internal field controlled by TI provided startup code | RW | 0
13 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0
12 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0
11 | DO_REDU_COL | Internal | RW | 0
10:7 | DBG_SHORT_ROW | Internal | RW | 0xA
6 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0
5 | PGM_SEC_COF_EN | Internal | RW | 0
4 | PREC_STOP_EN | Internal | RW | 0
3 | DIS_TST_EN | Internal | RW | 0
2 | CMD_EN | Internal | RW | 0
1 | INV_DATA | Internal | RW | 0
0 | OVERRIDE | Internal | RW | 0

### TOP:FLASH:FSM_FLES

Address offset | 0x0000 2280
Physical address | 0x4003 2280 | Instance | FLASH
Description | Internal Register. Customers can control this through TI provided API
Type | RW

Bits | Field Name | Description | Type | Reset
31:12 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0 0000
11:8 | BLK_TIOTP | Internal | RW | 0x0
7:0 | BLK_OTP | Internal | RW | 0x00

### TOP:FLASH:FSM_WR_ENA

Address offset | 0x0000 2288
Physical address | 0x4003 2288 | Instance | FLASH
Description | Internal Register. Customers can control this through TI provided API
Type | RW

Bits | Field Name | Description | Type | Reset
31:3 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0000 0000
2:0 | WR_ENA | Internal | RW | 0x2

### TOP:FLASH:FSM_ACC_PP

Address offset | 0x0000 228C
Physical address | 0x4003 228C | Instance | FLASH
Description | Internal Register. Customers can control this through TI provided API
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | FSM_ACC_PP | Internal | RO | 0x0000 0000

### TOP:FLASH:FSM_ACC_EP

Address offset | 0x0000 2290
Physical address | 0x4003 2290 | Instance | FLASH
Description | Internal Register. Customers can control this through TI provided API
Type | RO

Bits | Field Name | Description | Type | Reset
31:16 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0000
15:0 | ACC_EP | Internal | RO | 0x0000

### TOP:FLASH:FSM_ADDR

Address offset | 0x0000 22A0
Physical address | 0x4003 22A0 | Instance | FLASH
Description | Internal Register. Customers can control this through TI provided API
Type | RO

Bits | Field Name | Description | Type | Reset
31 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0
30:28 | BANK | Internal | RO | 0x0
27:0 | CUR_ADDR | Internal | RO | 0x000 0000

### TOP:FLASH:FSM_SECTOR

Address offset | 0x0000 22A4
Physical address | 0x4003 22A4 | Instance | FLASH
Description | Internal Register. Customers can control this through TI provided API
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | SECT_ERASED | Internal | RW | 0xFFFF
15:8 | FSM_SECTOR_EXTENSION | Internal | RO | 0x00
7:4 | SECTOR | Internal | RO | 0x0
3:0 | SEC_OUT | Internal | RO | 0x0

### TOP:FLASH:FMC_REV_ID

Address offset | 0x0000 22A8
Physical address | 0x4003 22A8 | Instance | FLASH
Description | Internal Register. Customers can control this through TI provided API
Type | RO

Bits | Field Name | Description | Type | Reset
31:12 | MOD_VERSION | Internal | RO | 0x0 0000
11:0 | CONFIG_CRC | Internal | RO | 0x000

### TOP:FLASH:FSM_ERR_ADDR

Address offset | 0x0000 22AC
Physical address | 0x4003 22AC | Instance | FLASH
Description | Internal Register. Customers can control this through TI provided API
Type | RO

Bits | Field Name | Description | Type | Reset
31:8 | FSM_ERR_ADDR | Internal | RO | 0x00 0000
7:4 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0
3:0 | FSM_ERR_BANK | Internal | RO | 0x0

### TOP:FLASH:FSM_PGM_MAXPUL

Address offset | 0x0000 22B0
Physical address | 0x4003 22B0 | Instance | FLASH
Description | Internal Register. Customers can control this through TI provided API
Type | RO

Bits | Field Name | Description | Type | Reset
31:12 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0 0000
11:0 | FSM_PGM_MAXPUL | Internal | RO | 0x000

### TOP:FLASH:FSM_EXECUTE

Address offset | 0x0000 22B4
Physical address | 0x4003 22B4 | Instance | FLASH
Description | Internal Register. Customers can control this through TI provided API
Type | RW

Bits | Field Name | Description | Type | Reset
31:20 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x000
19:16 | SUSPEND_NOW | Internal | RW | 0xA
15:5 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x000
4:0 | FSMEXECUTE | Internal | RW | 0x0A

### TOP:FLASH:FSM_SECTOR1

Address offset | 0x0000 22C0
Physical address | 0x4003 22C0 | Instance | FLASH
Description | Internal Register. Customers can control this through TI provided API
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | FSM_SECTOR1 | Internal | RW | 0xFFFF FFFF

### TOP:FLASH:FSM_SECTOR2

Address offset | 0x0000 22C4
Physical address | 0x4003 22C4 | Instance | FLASH
Description | Internal Register. Customers can control this through TI provided API
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | FSM_SECTOR2 | Internal | RW | 0x0000 0000

### TOP:FLASH:FSM_BSLE0

Address offset | 0x0000 22E0
Physical address | 0x4003 22E0 | Instance | FLASH
Description | Internal Register. Customers can control this through TI provided API
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | FSM_BSLE0 | Internal field controlled by TI provided startup code | RW | 0x0000 0000

### TOP:FLASH:FSM_BSLE1

Address offset | 0x0000 22E4
Physical address | 0x4003 22E4 | Instance | FLASH
Description | Internal Register. Customers can control this through TI provided API
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | FSM_BSL1 | Internal field controlled by TI provided startup code | RW | 0x0000 0000

### TOP:FLASH:FSM_BSLP0

Address offset | 0x0000 22F0
Physical address | 0x4003 22F0 | Instance | FLASH
Description | Internal Register. Customers can control this through TI provided API
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | FSM_BSLP0 | Internal field controlled by TI provided startup code | RW | 0x0000 0000

### TOP:FLASH:FSM_BSLP1

Address offset | 0x0000 22F4
Physical address | 0x4003 22F4 | Instance | FLASH
Description | Internal Register. Customers can control this through TI provided API
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | FSM_BSL1 | Internal field controlled by TI provided startup code | RW | 0x0000 0000

### TOP:FLASH:FCFG_BANK

Address offset | 0x0000 2400
Physical address | 0x4003 2400 | Instance | FLASH
Description | Internal Register. Customers can control this through TI provided API
Type | RO

Bits | Field Name | Description | Type | Reset
31:20 | EE_BANK_WIDTH | Internal | RO | 0x000
19:16 | EE_NUM_BANK | Internal | RO | 0x0
15:4 | MAIN_BANK_WIDTH | Internal | RO | 0x040
3:0 | MAIN_NUM_BANK | Internal | RO | 0x1

### TOP:FLASH:FCFG_WRAPPER

Address offset | 0x0000 2404
Physical address | 0x4003 2404 | Instance | FLASH
Description | Internal Register. Customers can control this through TI provided API
Type | RO

Bits | Field Name | Description | Type | Reset
31:24 | FAMILY_TYPE | Internal | RO | 0x50
23:21 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0
20 | MEM_MAP | Internal | RO | 0
19:16 | CPU2 | Internal | RO | 0x0
15:12 | EE_IN_MAIN | Internal | RO | 0x9
11 | ROM | Internal | RO | 0
10 | IFLUSH | Internal | RO | 0
9 | SIL3 | Internal | RO | 0
8 | ECCA | Internal | RO | 0
7:6 | AUTO_SUSP | Internal | RO | 0x0
5:4 | UERR | Internal | RO | 0x0
3:0 | CPU_TYPE1 | Internal | RO | 0x7

### TOP:FLASH:FCFG_BNK_TYPE

Address offset | 0x0000 2408
Physical address | 0x4003 2408 | Instance | FLASH
Description | Internal Register. Customers can control this through TI provided API
Type | RO

Bits | Field Name | Description | Type | Reset
31:28 | B7_TYPE | Internal | RO | 0x0
27:24 | B6_TYPE | Internal | RO | 0x0
23:20 | B5_TYPE | Internal | RO | 0x0
19:16 | B4_TYPE | Internal | RO | 0x0
15:12 | B3_TYPE | Internal | RO | 0x0
11:8 | B2_TYPE | Internal | RO | 0x0
7:4 | B1_TYPE | Internal | RO | 0x0
3:0 | B0_TYPE | Internal | RO | 0x3

### TOP:FLASH:FCFG_B0_START

Address offset | 0x0000 2410
Physical address | 0x4003 2410 | Instance | FLASH
Description | Internal Register. Customers can control this through TI provided API
Type | RO

Bits | Field Name | Description | Type | Reset
31:28 | B0_MAX_SECTOR | Internal | RO | 0x0
27:24 | B0_MUX_FACTOR | Internal | RO | 0x2
23:0 | B0_START_ADDR | Internal | RO | 0x00 0000

### TOP:FLASH:FCFG_B1_START

Address offset | 0x0000 2414
Physical address | 0x4003 2414 | Instance | FLASH
Description | Internal Register. Customers can control this through TI provided API
Type | RO

Bits | Field Name | Description | Type | Reset
31:28 | B1_MAX_SECTOR | Internal | RO | 0x0
27:24 | B1_MUX_FACTOR | Internal | RO | 0x0
23:0 | B1_START_ADDR | Internal | RO | 0x00 0000

### TOP:FLASH:FCFG_B2_START

Address offset | 0x0000 2418
Physical address | 0x4003 2418 | Instance | FLASH
Description | Internal Register. Customers can control this through TI provided API
Type | RO

Bits | Field Name | Description | Type | Reset
31:28 | B2_MAX_SECTOR | Internal | RO | 0x0
27:24 | B2_MUX_FACTOR | Internal | RO | 0x0
23:0 | B2_START_ADDR | Internal | RO | 0x00 0000

### TOP:FLASH:FCFG_B3_START

Address offset | 0x0000 241C
Physical address | 0x4003 241C | Instance | FLASH
Description | Internal Register. Customers can control this through TI provided API
Type | RO

Bits | Field Name | Description | Type | Reset
31:28 | B3_MAX_SECTOR | Internal | RO | 0x0
27:24 | B3_MUX_FACTOR | Internal | RO | 0x0
23:0 | B3_START_ADDR | Internal | RO | 0x00 0000

### TOP:FLASH:FCFG_B4_START

Address offset | 0x0000 2420
Physical address | 0x4003 2420 | Instance | FLASH
Description | Internal Register. Customers can control this through TI provided API
Type | RO

Bits | Field Name | Description | Type | Reset
31:28 | B4_MAX_SECTOR | Internal | RO | 0x0
27:24 | B4_MUX_FACTOR | Internal | RO | 0x0
23:0 | B4_START_ADDR | Internal | RO | 0x00 0000

### TOP:FLASH:FCFG_B5_START

Address offset | 0x0000 2424
Physical address | 0x4003 2424 | Instance | FLASH
Description | Internal Register. Customers can control this through TI provided API
Type | RO

Bits | Field Name | Description | Type | Reset
31:28 | B5_MAX_SECTOR | Internal | RO | 0x0
27:24 | B5_MUX_FACTOR | Internal | RO | 0x0
23:0 | B5_START_ADDR | Internal | RO | 0x00 0000

### TOP:FLASH:FCFG_B6_START

Address offset | 0x0000 2428
Physical address | 0x4003 2428 | Instance | FLASH
Description | Internal Register. Customers can control this through TI provided API
Type | RO

Bits | Field Name | Description | Type | Reset
31:28 | B6_MAX_SECTOR | Internal | RO | 0x0
27:24 | B6_MUX_FACTOR | Internal | RO | 0x0
23:0 | B6_START_ADDR | Internal | RO | 0x00 0000

### TOP:FLASH:FCFG_B7_START

Address offset | 0x0000 242C
Physical address | 0x4003 242C | Instance | FLASH
Description | Internal Register. Customers can control this through TI provided API
Type | RO

Bits | Field Name | Description | Type | Reset
31:28 | B7_MAX_SECTOR | Internal | RO | 0x0
27:24 | B7_MUX_FACTOR | Internal | RO | 0x0
23:0 | B7_START_ADDR | Internal | RO | 0x00 0000

### TOP:FLASH:FCFG_B0_SSIZE0

Address offset | 0x0000 2430
Physical address | 0x4003 2430 | Instance | FLASH
Description | Internal Register. Customers can control this through TI provided API
Type | RO

Bits | Field Name | Description | Type | Reset
31:28 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0
27:16 | B0_NUM_SECTORS | Internal | RO | 0x020
15:4 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x000
3:0 | B0_SECT_SIZE | Internal | RO | 0x4