## ADI_1_SYNTH

Instance: ADI_1_SYNTH
Component: ADI_1_SYNTH
Base address: 0x10000000

ADI for synthesizer modules (analog part).
Registers Fields should be considered static unless otherwise noted (as dynamic)

### TOP:ADI_1_SYNTH Register Summary

Register Name | Type | Register Width (Bits) | Register Reset | Address Offset | Physical Address
VCOLDOCTL0 | RW | 8 | 0x0000 0000 | 0x0000 0000 | 0x1000 0000
VCOLDOCTL1 |  | 8 | 0x0000 0000 | 0x0000 0001 | 0x1000 0001
VCOLDOCFG |  | 8 | 0x0000 0000 | 0x0000 0002 | 0x1000 0002
SLDOCTL0 | RW | 8 | 0x0000 0000 | 0x0000 0003 | 0x1000 0003
SLDOCTL1 | RW | 8 | 0x0000 0000 | 0x0000 0004 | 0x1000 0004
SYNTHCTLINIT | RW | 8 | 0x0000 0000 | 0x0000 0008 | 0x1000 0008
ATESTCTL0 | RW | 8 | 0x0000 0000 | 0x0000 0009 | 0x1000 0009
ATESTCTL1 | RW | 8 | 0x0000 0000 | 0x0000 000A | 0x1000 000A
STAT | RO | 8 | 0x0000 0000 | 0x0000 000F | 0x1000 000F

### TOP:ADI_1_SYNTH Register Descriptions

### TOP:ADI_1_SYNTH:VCOLDOCTL0

Address offset | 0x0000 0000
Physical address | 0x1000 0000 | Instance | ADI_1_SYNTH
Description | LDOVCO Control
Type | RW

Bits | Field Name | Description | Type | Reset
7:5 | RESERVED5 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RW | 0x0
4 | ATEST_V_EN | Enables regulated output voltage to ATEST. 0: Disabled 1: Enabled | RW | 0
3 | BYPASS_REG_EN | Bypass LDO and short VDDR and LDO output. 0: Disabled 1: Enabled | RW | 0
2 | RDY_EN | Enable LDO ready Signal generation circuit. EN must also be set. When circuit is enabled, it will set STAT.LDOVCO_RDY when VCOLDO is ready. 0: Disable 1: Enable | RW | 0
1 | BIAS_DIS | Disable dummy bias current. 0: Dummy bias current on (Default) 1: Dummy bias current off | RW | 0
0 | EN | Enable regulator for supplying VCO, VCO Divider 0: Disabled 1: Enabled | RW | 0

### TOP:ADI_1_SYNTH:VCOLDOCTL1

Address offset | 0x0000 0001
Physical address | 0x1000 0001 | Instance | ADI_1_SYNTH
Description | Low DropOut Regulator for Voltage Controlled Oscillator Control 1 This register contains output trim and ATEST enable
Type |

Bits | Field Name | Description | Type | Reset
7 | RESERVED7 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RW | 0
6 | ATEST_I_EN | Enable test current (2.5% of pass device current) to ATEST. 0: Disabled 1: Enabled | RW | 0
5:0 | TRIM_OUT | Trim LDO's output voltage linearly with a signed 2's complement number. Step size is approximately 5 mV. 0x20: -32 : 1.238V (Minimum Voltage) ... 0x2F: -1 : 1.389V 0x00: +0 : 1.400V (Default) 0x01: +1 : 1.404V ... 0x1F:+31 : 1.549V (Maximum Voltage) VCOLDOCTL0.ATEST_V_EN required to monitor voltage. | RW | 0x00

### TOP:ADI_1_SYNTH:VCOLDOCFG

Address offset | 0x0000 0002
Physical address | 0x1000 0002 | Instance | ADI_1_SYNTH
Description | Low DropOut Regulator for Voltage Controlled Oscillator Configuration This register is used to trim the compensation components.
Type |

Bits | Field Name | Description | Type | Reset
7 | RESERVED7 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RW | 0
6 | DIV_BIAS_DIS | Disable RF divider dummy bias current. 0: Dummy bias current on (Default) 1: Dummy bias current off | RW | 0
5:3 | COMP_RES | Trim compensation resistor in series with Miller cap in nonlinear steps. Default should be 0x3. Unsigned number. 0x0: 1066 ohms (Minimum Resistance) 0x1: 1230 ohms 0x2: 1454 ohms 0x3: 1777 ohms (Default) 0x4: 2285 ohms 0x5: 3200 ohms 0x6: 5333 ohms 0x7: 16000 ohms (Maximum Resistance) | RW | 0x0
2:0 | COMP_CAP | Trim compensation Miller cap in linear steps of 0.5 pF. Default should be 0x4. Unsigned. Tradeoff stability for speed. 0x0: 3.5 pF (Maximum Capacitance) 0x1: 3.0 pF ... 0x4: 1.5pF (Default) ... 0x6: 0.5 pF 0x7: Open Circuit / No Capacitance / No Compensation (regardless of COMP_RES setting) | RW | 0x0

### TOP:ADI_1_SYNTH:SLDOCTL0

Address offset | 0x0000 0003
Physical address | 0x1000 0003 | Instance | ADI_1_SYNTH
Description | Synthesizer Low DropOut Regultaror Control 0
Type | RW

Bits | Field Name | Description | Type | Reset
7 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text) | RW | 0
6 | COMP_CAP | Enable compensation cap 0: Disable compensation (default) 1: Enable compensation (1pF Miller cap around pass device) | RW | 0
5 | ATEST_I_EN | Enable test current (2% of pass device current) to ATEST. 0: Disabled 1: Enabled | RW | 0
4 | ATEST_V_EN | Enables regulated output voltage to ATEST. 0: Disabled 1: Enabled | RW | 0
3 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text) | RW | 0
2 | RDY_EN | Enable LDO ready Signal generation circuit. EN must also be set. When circuit is enabled, it will set STAT.SLDO_RDY when SLDO is ready. 0: Disable 1: Enable | RW | 0
1 | BIAS_DIS | Disable dummy bias current. 0: Dummy bias current on (Default) 1: Dummy bias current off | RW | 0
0 | EN | Enable regulator for supplying RF synthesizer core, TDC and clock retimer 0: Disabled 1: Enabled | RW | 0

### TOP:ADI_1_SYNTH:SLDOCTL1

Address offset | 0x0000 0004
Physical address | 0x1000 0004 | Instance | ADI_1_SYNTH
Description | Synthesizer Low DropOut Regulator Control 1 This register trims the SLDO output
Type | RW

Bits | Field Name | Description | Type | Reset
7:6 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text) | RW | 0x0
5:0 | TRIM_OUT | Trim LDO's output voltage linearly with a signed 2's complement number. Step size is approximately 5 mV. 0x20: -32 : 1.11 (Minimum Voltage) ... 0x00: +0 : 1.26V (Default) ... 0x1F:+31 : 1.41V (Maximum Voltage) SLDOCTL0.ATEST_V_EN required to monitor voltage. | RW | 0x00

### TOP:ADI_1_SYNTH:SYNTHCTLINIT

Address offset | 0x0000 0008
Physical address | 0x1000 0008 | Instance | ADI_1_SYNTH
Description | Synthesizer Control of Initialisation Clock and reset to synth
Type | RW

Bits | Field Name | Description | Type | Reset
7:2 | RESERVED2 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |  | 0x00
1 | CLK_EN | Enable for clock from XOSC to synthesizer |  | 0
0 | DDI_RESET_N | Reset digital core of synthesizer DDI 0: Reset DDI 1: No action |  | 0

### TOP:ADI_1_SYNTH:ATESTCTL0

Address offset | 0x0000 0009
Physical address | 0x1000 0009 | Instance | ADI_1_SYNTH
Description | Analog Test Control 0
Type | RW

Bits | Field Name | Description | Type | Reset
7:0 | TESTSEL | Control muxing of analog test signals from RF_TOP. Used in conjunction with ATESTCTL1.TESTSEL.
Value | ENUM name | Description
0x00 | NC | No signal connected to ATEST0/1
0x01 | RXOUTIP_A0 | RX_OUTIP to ATEST0
0x02 | RXOUTQP_A0 | RX_OUTQP to ATEST0
0x04 | PEAKDETP_A0 | PEADET_P to ATEST0
0x08 | IFADCP_A0 | IFADC_P to ATEST0
0x10 | LDOV_A0 | LDO_V to ATEST0
0x20 | RXOUTIN_A1 | RX_OUTIN to ATEST1
0x40 | RXOUTQN_A1 | RXOUTQN to ATEST1
0x80 | PEAKDETN_A1 | PEAKDET_N to ATEST1
|  | 0x00

### TOP:ADI_1_SYNTH:ATESTCTL1

Address offset | 0x0000 000A
Physical address | 0x1000 000A | Instance | ADI_1_SYNTH
Description | Analog Test Control 1
Type | RW

Bits | Field Name | Description | Type | Reset
7:2 | RESEREVED2 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |  | 0x00
1:0 | TESTSEL | Control muxing of analog test signals from RF_TOP. Used in conjunction with ATESTCTL0.TESTSEL.
Value | ENUM name | Description
0x0 | NC | No signal connected to ATEST0/1
0x1 | IFADCTESTN_A1 | IFADC_TEST_N to ATEST1
0x2 | LDOITEST_A1 | LDO_ITEST to ATEST1
|  | 0x0

### TOP:ADI_1_SYNTH:STAT

Address offset | 0x0000 000F
Physical address | 0x1000 000F | Instance | ADI_1_SYNTH
Description | Status
Type | RO

Bits | Field Name | Description | Type | Reset
7:3 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x00
2 | SYNTH_TUNE_ACK | Acknowledgement from digital part of frequency synthesizer that the current calibration step has completed. 0: The calibration phase set by DLO_DTX:SYNTHREG00.SYNTH_TUNE_PHASE has not finished 1: The calibration phase set by DLO_DTX:SYNTHREG00.SYNTH_TUNE_PHASE has finished | RO | 0
1 | SLDO_RDY | Status of SLDO Latched once high and can only be reset by toggling SLDOCTL0.RDY_EN. 0: Output is less than 90% of target value 1: Output is greater than 90% of target value. | RO | 0
0 | LDOVCO_RDY | Status of LDOVCO. Latched once high and can only be reset by toggling VCOLDOCTL0.RDY_EN. 0: Output is less than 90% of target value 1: Output is greater than 90% of target value. | RO | 0