## CRYPTO

Instance: CRYPTO
Component: CRYPTO
Base address: 0x40024000

Crypto core with DMA capability and local key storage

### TOP:CRYPTO Register Summary

Register Name | Type | Register Width (Bits) | Register Reset | Address Offset | Physical Address
DMACH0CTL | RW | 32 | 0x0000 0000 | 0x0000 0000 | 0x4002 4000
DMACH0EXTADDR | RW | 32 | 0x0000 0000 | 0x0000 0004 | 0x4002 4004
DMACH0LEN | RW | 32 | 0x0000 0000 | 0x0000 000C | 0x4002 400C
DMASTAT | RO | 32 | 0x0000 0000 | 0x0000 0018 | 0x4002 4018
DMASWRESET | WO | 32 | 0x0000 0000 | 0x0000 001C | 0x4002 401C
DMACH1CTL | RW | 32 | 0x0000 0000 | 0x0000 0020 | 0x4002 4020
DMACH1EXTADDR | RW | 32 | 0x0000 0000 | 0x0000 0024 | 0x4002 4024
DMACH1LEN | RW | 32 | 0x0000 0000 | 0x0000 002C | 0x4002 402C
DMABUSCFG | RW | 32 | 0x0000 2400 | 0x0000 0078 | 0x4002 4078
DMAPORTERR | RO | 32 | 0x0000 0000 | 0x0000 007C | 0x4002 407C
DMAHWVER | RO | 32 | 0x0101 2ED1 | 0x0000 00FC | 0x4002 40FC
KEYWRITEAREA | RW | 32 | 0x0000 0000 | 0x0000 0400 | 0x4002 4400
KEYWRITTENAREA | RW | 32 | 0x0000 0000 | 0x0000 0404 | 0x4002 4404
KEYSIZE | RW | 32 | 0x0000 0001 | 0x0000 0408 | 0x4002 4408
KEYREADAREA | RW | 32 | 0x0000 0008 | 0x0000 040C | 0x4002 440C
AESKEY2__0-AESKEY2__3 | WO | 32 | 0x0000 0000 | 0x0000 0500-0x0000 050C | 0x4002 4500- 0x4002 450C
AESKEY3__0-AESKEY3__3 | WO | 32 | 0x0000 0000 | 0x0000 0510-0x0000 051C | 0x4002 4510- 0x4002 451C
AESIV__0-AESIV__3 | RW | 32 | 0x0000 0000 | 0x0000 0540-0x0000 054C | 0x4002 4540- 0x4002 454C
AESCTL | RW | 32 | 0x8000 0000 | 0x0000 0550 | 0x4002 4550
AESDATALEN0 | WO | 32 | 0x0000 0000 | 0x0000 0554 | 0x4002 4554
AESDATALEN1 | WO | 32 | 0x0000 0000 | 0x0000 0558 | 0x4002 4558
AESAUTHLEN | WO | 32 | 0x0000 0000 | 0x0000 055C | 0x4002 455C
AESDATAIN0 | WO | 32 | 0x0000 0000 | 0x0000 0560 | 0x4002 4560
AESDATAOUT0 | RO | 32 | 0x0000 0000 | 0x0000 0560 | 0x4002 4560
AESDATAIN1 | WO | 32 | 0x0000 0000 | 0x0000 0564 | 0x4002 4564
AESDATAOUT1 | RO | 32 | 0x0000 0000 | 0x0000 0564 | 0x4002 4564
AESDATAIN2 | WO | 32 | 0x0000 0000 | 0x0000 0568 | 0x4002 4568
AESDATAOUT2 | RO | 32 | 0x0000 0000 | 0x0000 0568 | 0x4002 4568
AESDATAIN3 | WO | 32 | 0x0000 0000 | 0x0000 056C | 0x4002 456C
AESDATAOUT3 | RO | 32 | 0x0000 0000 | 0x0000 056C | 0x4002 456C
AESTAGOUT__0-AESTAGOUT__3 | RO | 32 | 0x0000 0000 | 0x0000 0570-0x0000 057C | 0x4002 4570- 0x4002 457C
ALGSEL | RW | 32 | 0x0000 0000 | 0x0000 0700 | 0x4002 4700
DMAPROTCTL | RW | 32 | 0x0000 0000 | 0x0000 0704 | 0x4002 4704
SWRESET | RW | 32 | 0x0000 0000 | 0x0000 0740 | 0x4002 4740
IRQTYPE | RW | 32 | 0x0000 0000 | 0x0000 0780 | 0x4002 4780
IRQEN | RW | 32 | 0x0000 0000 | 0x0000 0784 | 0x4002 4784
IRQCLR | WO | 32 | 0x0000 0000 | 0x0000 0788 | 0x4002 4788
IRQSET | WO | 32 | 0x0000 0000 | 0x0000 078C | 0x4002 478C
IRQSTAT | RO | 32 | 0x0000 0000 | 0x0000 0790 | 0x4002 4790
HWVER | RO | 32 | 0x9111 8778 | 0x0000 07FC | 0x4002 47FC

### TOP:CRYPTO Register Descriptions

### TOP:CRYPTO:DMACH0CTL

Address offset | 0x0000 0000
Physical address | 0x4002 4000 | Instance | CRYPTO
Description | DMA Channel 0 Control
Type | RW

Bits | Field Name | Description | Type | Reset
31:2 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text) | RW | 0x0000 0000
1 | PRIO | Channel priority: A channel with high priority will be served before a channel with low priority in cases with simultaneous access requests. If both channels have the same priority access of the channels to the external port is arbitrated using a Round Robin scheme.
Value | ENUM name | Description
0 | LOW | Priority low
1 | HIGH | Priority high
| RW | 0
0 | EN | DMA Channel 0 Control
Value | ENUM name | Description
0 | DIS | Channel disabled
1 | EN | Channel enabled
| RW | 0

### TOP:CRYPTO:DMACH0EXTADDR

Address offset | 0x0000 0004
Physical address | 0x4002 4004 | Instance | CRYPTO
Description | DMA Channel 0 External Address
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | ADDR | Channel external address value. Holds the last updated external address after being sent to the master interface. | RW | 0x0000 0000

### TOP:CRYPTO:DMACH0LEN

Address offset | 0x0000 000C
Physical address | 0x4002 400C | Instance | CRYPTO
Description | DMA Channel 0 Length
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text) | RW | 0x0000
15:0 | LEN | DMA transfer length in bytes. During configuration, this register contains the DMA transfer length in bytes. During operation, it contains the last updated value of the DMA transfer length after being sent to the master interface. Note: Writing a non-zero value to this register field starts the transfer if the channel is enabled by setting DMACH0CTL.EN. | RW | 0x0000

### TOP:CRYPTO:DMASTAT

Address offset | 0x0000 0018
Physical address | 0x4002 4018 | Instance | CRYPTO
Description | DMA Controller Status
Type | RO

Bits | Field Name | Description | Type | Reset
31:18 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0000
17 | PORT_ERR | Reflects possible transfer errors on the AHB port. | RO | 0
16:2 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0000
1 | CH1_ACTIVE | This register field indicates if DMA channel 1 is active or not. 0: Not active 1: Active | RO | 0
0 | CH0_ACTIVE | This register field indicates if DMA channel 0 is active or not. 0: Not active 1: Active | RO | 0

### TOP:CRYPTO:DMASWRESET

Address offset | 0x0000 001C
Physical address | 0x4002 401C | Instance | CRYPTO
Description | DMA Controller Software Reset
Type | WO

Bits | Field Name | Description | Type | Reset
31:1 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(WO std text) | WO | 0x0000 0000
0 | RESET | Software reset enable 0: Disable 1: Enable (self-cleared to zero). Note: Completion of the software reset must be checked in DMASTAT.CH0_ACTIVE and DMASTAT.CH1_ACTIVE. | WO | 0

### TOP:CRYPTO:DMACH1CTL

Address offset | 0x0000 0020
Physical address | 0x4002 4020 | Instance | CRYPTO
Description | DMA Channel 1 Control
Type | RW

Bits | Field Name | Description | Type | Reset
31:2 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text) | RW | 0x0000 0000
1 | PRIO | Channel priority: A channel with high priority will be served before a channel with low priority in cases with simultaneous access requests. If both channels have the same priority access of the channels to the external port is arbitrated using a Round Robin scheme.
Value | ENUM name | Description
0 | LOW | Priority low
1 | HIGH | Priority high
| RW | 0
0 | EN | Channel enable: Note: Disabling an active channel will interrupt the DMA operation. The ongoing block transfer will be completed, but no new transfers will be requested.
Value | ENUM name | Description
0 | DIS | Channel disabled
1 | EN | Channel enabled
| RW | 0

### TOP:CRYPTO:DMACH1EXTADDR

Address offset | 0x0000 0024
Physical address | 0x4002 4024 | Instance | CRYPTO
Description | DMA Channel 1 External Address
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | ADDR | Channel external address value. Holds the last updated external address after being sent to the master interface. | RW | 0x0000 0000

### TOP:CRYPTO:DMACH1LEN

Address offset | 0x0000 002C
Physical address | 0x4002 402C | Instance | CRYPTO
Description | DMA Channel 1 Length
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text) | RW | 0x0000
15:0 | LEN | DMA transfer length in bytes. During configuration, this register contains the DMA transfer length in bytes. During operation, it contains the last updated value of the DMA transfer length after being sent to the master interface. Note: Writing a non-zero value to this register field starts the transfer if the channel is enabled by setting DMACH1CTL.EN. | RW | 0x0000

### TOP:CRYPTO:DMABUSCFG

Address offset | 0x0000 0078
Physical address | 0x4002 4078 | Instance | CRYPTO
Description | DMA Controller Master Configuration
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text) | RW | 0x0000
15:12 | AHB_MST1_BURST_SIZE | Maximum burst size that can be performed on the AHB bus
Value | ENUM name | Description
0x2 | 4_BYTE | 4 bytes
0x3 | 8_BYTE | 8 bytes
0x4 | 16_BYTE | 16 bytes
0x5 | 32_BYTE | 32 bytes
0x6 | 64_BYTE | 64 bytes
| RW | 0x2
11 | AHB_MST1_IDLE_EN | Idle transfer insertion between consecutive burst transfers on AHB
Value | ENUM name | Description
0 | NO_IDLE | Do not insert idle transfers.
1 | IDLE | Idle transfer insertion enabled
| RW | 0
10 | AHB_MST1_INCR_EN | Burst length type of AHB transfer
Value | ENUM name | Description
0 | UNSPECIFIED | Unspecified length burst transfers
1 | SPECIFIED | Fixed length bursts or single transfers
| RW | 1
9 | AHB_MST1_LOCK_EN | Locked transform on AHB
Value | ENUM name | Description
0 | NOT_LOCKED | Transfers are not locked
1 | LOCKED | Transfers are locked
| RW | 0
8 | AHB_MST1_BIGEND | Endianess for the AHB master
Value | ENUM name | Description
0 | LITTLE_ENDIAN | Little Endian
1 | BIG_ENDIAN | Big Endian
| RW | 0
7:0 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text) | RW | 0x00

### TOP:CRYPTO:DMAPORTERR

Address offset | 0x0000 007C
Physical address | 0x4002 407C | Instance | CRYPTO
Description | DMA Controller Port Error
Type | RO

Bits | Field Name | Description | Type | Reset
31:13 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0 0000
12 | AHB_ERR | A 1 indicates that the Crypto peripheral has detected an AHB bus error | RO | 0
11:10 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0
9 | LAST_CH | Indicates which channel was serviced last (channel 0 or channel 1) by the AHB master port. | RO | 0
8:0 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x000

### TOP:CRYPTO:DMAHWVER

Address offset | 0x0000 00FC
Physical address | 0x4002 40FC | Instance | CRYPTO
Description | DMA Controller Version
Type | RO

Bits | Field Name | Description | Type | Reset
31:28 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0
27:24 | HW_MAJOR_VER | Major version number | RO | 0x1
23:20 | HW_MINOR_VER | Minor version number | RO | 0x0
19:16 | HW_PATCH_LVL | Patch level. | RO | 0x1
15:8 | VER_NUM_COMPL | Bit-by-bit complement of the VER_NUM field bits. | RO | 0x2E
7:0 | VER_NUM | Version number of the DMA Controller (209) | RO | 0xD1

### TOP:CRYPTO:KEYWRITEAREA

Address offset | 0x0000 0400
Physical address | 0x4002 4400 | Instance | CRYPTO
Description | Key Write Area
Type | RW

Bits | Field Name | Description | Type | Reset
31:8 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text) | RW | 0x00 0000
7 | RAM_AREA7 | Represents an area of 128 bits. Select the key store RAM area(s) where the key(s) needs to be written. Writing to multiple RAM locations is only possible when the selected RAM areas are sequential.
Value | ENUM name | Description
0 | NOT_SEL | This RAM area is not selected to be written
1 | SEL | This RAM area is selected to be written
| RW | 0
6 | RAM_AREA6 | Represents an area of 128 bits. Select the key store RAM area(s) where the key(s) needs to be written. Writing to multiple RAM locations is only possible when the selected RAM areas are sequential.
Value | ENUM name | Description
0 | NOT_SEL | This RAM area is not selected to be written
1 | SEL | This RAM area is selected to be written
| RW | 0
5 | RAM_AREA5 | Represents an area of 128 bits. Select the key store RAM area(s) where the key(s) needs to be written. Writing to multiple RAM locations is only possible when the selected RAM areas are sequential.
Value | ENUM name | Description
0 | NOT_SEL | This RAM area is not selected to be written
1 | SEL | This RAM area is selected to be written
| RW | 0
4 | RAM_AREA4 | Represents an area of 128 bits. Select the key store RAM area(s) where the key(s) needs to be written. Writing to multiple RAM locations is only possible when the selected RAM areas are sequential.
Value | ENUM name | Description
0 | NOT_SEL | This RAM area is not selected to be written
1 | SEL | This RAM area is selected to be written
| RW | 0
3 | RAM_AREA3 | Represents an area of 128 bits. Select the key store RAM area(s) where the key(s) needs to be written. Writing to multiple RAM locations is only possible when the selected RAM areas are sequential.
Value | ENUM name | Description
0 | NOT_SEL | This RAM area is not selected to be written
1 | SEL | This RAM area is selected to be written
| RW | 0
2 | RAM_AREA2 | Represents an area of 128 bits. Select the key store RAM area(s) where the key(s) needs to be written. Writing to multiple RAM locations is only possible when the selected RAM areas are sequential.
Value | ENUM name | Description
0 | NOT_SEL | This RAM area is not selected to be written
1 | SEL | This RAM area is selected to be written
| RW | 0
1 | RAM_AREA1 | Represents an area of 128 bits. Select the key store RAM area(s) where the key(s) needs to be written. Writing to multiple RAM locations is only possible when the selected RAM areas are sequential.
Value | ENUM name | Description
0 | NOT_SEL | This RAM area is not selected to be written
1 | SEL | This RAM area is selected to be written
| RW | 0
0 | RAM_AREA0 | Represents an area of 128 bits. Select the key store RAM area(s) where the key(s) needs to be written. Writing to multiple RAM locations is only possible when the selected RAM areas are sequential.
Value | ENUM name | Description
0 | NOT_SEL | This RAM area is not selected to be written
1 | SEL | This RAM area is selected to be written
| RW | 0

### TOP:CRYPTO:KEYWRITTENAREA

Address offset | 0x0000 0404
Physical address | 0x4002 4404 | Instance | CRYPTO
Description | Key Written Area Status This register shows which areas of the key store RAM contain valid written keys. When a new key needs to be written to the key store, on a location that is already occupied by a valid key, this key area must be cleared first. This can be done by writing this register before the new key is written to the key store memory. Attempting to write to a key area that already contains a valid key is not allowed and will result in an error.
Type | RW

Bits | Field Name | Description | Type | Reset
31:8 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text) | RW | 0x00 0000
7 | RAM_AREA_WRITTEN7 | On read this bit returns the key area written status. This bit can be reset by writing a 1. Note: This register will be reset on a soft reset initiated by writing to DMASWRESET.RESET. After a soft reset, all keys must be rewritten to the key store memory.
Value | ENUM name | Description
0 | NOT_WRITTEN | This RAM area is not written with valid key information
1 | WRITTEN | This RAM area is written with valid key information
| RW | 0
6 | RAM_AREA_WRITTEN6 | On read this bit returns the key area written status. This bit can be reset by writing a 1. Note: This register will be reset on a soft reset initiated by writing to DMASWRESET.RESET. After a soft reset, all keys must be rewritten to the key store memory.
Value | ENUM name | Description
0 | NOT_WRITTEN | This RAM area is not written with valid key information
1 | WRITTEN | This RAM area is written with valid key information
| RW | 0
5 | RAM_AREA_WRITTEN5 | On read this bit returns the key area written status. This bit can be reset by writing a 1. Note: This register will be reset on a soft reset initiated by writing to DMASWRESET.RESET. After a soft reset, all keys must be rewritten to the key store memory.
Value | ENUM name | Description
0 | NOT_WRITTEN | This RAM area is not written with valid key information
1 | WRITTEN | This RAM area is written with valid key information
| RW | 0
4 | RAM_AREA_WRITTEN4 | On read this bit returns the key area written status. This bit can be reset by writing a 1. Note: This register will be reset on a soft reset initiated by writing to DMASWRESET.RESET. After a soft reset, all keys must be rewritten to the key store memory.
Value | ENUM name | Description
0 | NOT_WRITTEN | This RAM area is not written with valid key information
1 | WRITTEN | This RAM area is written with valid key information
| RW | 0
3 | RAM_AREA_WRITTEN3 | On read this bit returns the key area written status. This bit can be reset by writing a 1. Note: This register will be reset on a soft reset initiated by writing to DMASWRESET.RESET. After a soft reset, all keys must be rewritten to the key store memory.
Value | ENUM name | Description
0 | NOT_WRITTEN | This RAM area is not written with valid key information
1 | WRITTEN | This RAM area is written with valid key information
| RW | 0
2 | RAM_AREA_WRITTEN2 | On read this bit returns the key area written status. This bit can be reset by writing a 1. Note: This register will be reset on a soft reset initiated by writing to DMASWRESET.RESET. After a soft reset, all keys must be rewritten to the key store memory.
Value | ENUM name | Description
0 | NOT_WRITTEN | This RAM area is not written with valid key information
1 | WRITTEN | This RAM area is written with valid key information
| RW | 0
1 | RAM_AREA_WRITTEN1 | On read this bit returns the key area written status. This bit can be reset by writing a 1. Note: This register will be reset on a soft reset initiated by writing to DMASWRESET.RESET. After a soft reset, all keys must be rewritten to the key store memory.
Value | ENUM name | Description
0 | NOT_WRITTEN | This RAM area is not written with valid key information
1 | WRITTEN | This RAM area is written with valid key information
| RW | 0
0 | RAM_AREA_WRITTEN0 | On read this bit returns the key area written status. This bit can be reset by writing a 1. Note: This register will be reset on a soft reset initiated by writing to DMASWRESET.RESET. After a soft reset, all keys must be rewritten to the key store memory.
Value | ENUM name | Description
0 | NOT_WRITTEN | This RAM area is not written with valid key information
1 | WRITTEN | This RAM area is written with valid key information
| RW | 0

### TOP:CRYPTO:KEYSIZE

Address offset | 0x0000 0408
Physical address | 0x4002 4408 | Instance | CRYPTO
Description | Key Size This register defines the size of the keys that are written with DMA.
Type | RW

Bits | Field Name | Description | Type | Reset
31:2 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text) | RW | 0x0000 0000
1:0 | SIZE | Key size When writing to this register, KEYWRITTENAREA will be reset. Note: For the Crypto peripheral this field is fixed to 128 bits. For software compatibility KEYWRITTENAREA will be reset when writing to this register.
Value | ENUM name | Description
0x1 | 128_BIT | 128 bits
0x2 | 192_BIT | Not supported
0x3 | 256_BIT | Not supported
| RW | 0x1

### TOP:CRYPTO:KEYREADAREA

Address offset | 0x0000 040C
Physical address | 0x4002 440C | Instance | CRYPTO
Description | Key Read Area
Type | RW

Bits | Field Name | Description | Type | Reset
31 | BUSY | Key store operation busy status flag (read only) 0: operation is completed. 1: operation is not completed and the key store is busy. | RO | 0
30:4 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text) | RW | 0x000 0000
3:0 | RAM_AREA | Selects the area of the key store RAM from where the key needs to be read that will be written to the AES engine. Only RAM areas that contain valid written keys can be selected.
Value | ENUM name | Description
0x0 | RAM_AREA0 | RAM Area 0
0x1 | RAM_AREA1 | RAM Area 1
0x2 | RAM_AREA2 | RAM Area 2
0x3 | RAM_AREA3 | RAM Area 3
0x4 | RAM_AREA4 | RAM Area 4
0x5 | RAM_AREA5 | RAM Area 5
0x6 | RAM_AREA6 | RAM Area 6
0x7 | RAM_AREA7 | RAM Area 7
0x8 | NO_RAM | No RAM
| RW | 0x8

### TOP:CRYPTO:AESKEY2__0-AESKEY2__3

Address offset | 0x0000 0500-0x0000 050C
Physical address | 0x4002 4500- 0x4002 450C | Instance | CRYPTO
Description | Clear AES_KEY2/GHASH Key
Type | WO

Bits | Field Name | Description | Type | Reset
31:0 | KEY2 | AESKEY2.* bits 31+x:0+x or AES_GHASH_H.* bits 31+x:0+x, where x = 0, 32, 64, 96 ordered from the LSW entry of this 4-deep register array. The interpretation of this field depends on the crypto operation mode. | WO | 0x0000 0000

### TOP:CRYPTO:AESKEY3__0-AESKEY3__3

Address offset | 0x0000 0510-0x0000 051C
Physical address | 0x4002 4510- 0x4002 451C | Instance | CRYPTO
Description | Clear AES_KEY3
Type | WO

Bits | Field Name | Description | Type | Reset
31:0 | KEY3 | AESKEY3.* bits 31+x:0+x or AESKEY2.* bits 159+x:128+x, where x = 0, 32, 64, 96 ordered from the LSW entry of this 4-deep register arrary. The interpretation of this field depends on the crypto operation mode. | WO | 0x0000 0000

### TOP:CRYPTO:AESIV__0-AESIV__3

Address offset | 0x0000 0540-0x0000 054C
Physical address | 0x4002 4540- 0x4002 454C | Instance | CRYPTO
Description | AES Initialization Vector
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | IV | The interpretation of this field depends on the crypto operation mode. | RW | 0x0000 0000

### TOP:CRYPTO:AESCTL

Address offset | 0x0000 0550
Physical address | 0x4002 4550 | Instance | CRYPTO
Description | AES Input/Output Buffer Control
Type | RW

Bits | Field Name | Description | Type | Reset
31 | CONTEXT_RDY | If 1, this status bit indicates that the context data registers can be overwritten and the Host is permitted to write the next context. Writing a context means writing either a mode, the crypto length or AESDATALEN1.LEN_MSW, AESDATALEN0.LEN_LSW length registers | RO | 1
30 | SAVED_CONTEXT_RDY | If read as 1, this status bit indicates that an AES authentication TAG and/or IV block(s) is/are available for the Host to retrieve. This bit is only asserted if SAVE_CONTEXT is set to 1. The bit is mutually exclusive with CONTEXT_RDY. Writing 1 clears the bit to zero, indicating the Crypto peripheral can start its next operation. This bit is also cleared when the 4th word of the output TAG and/or IV is read. Note: All other mode bit writes will be ignored when this mode bit is written with 1. Note: This bit is controlled automatically by the Crypto peripheral for TAG read DMA operations. For typical use, this bit does NOT need to be written, but is used for status reading only. In this case, this status bit is automatically maintained by the Crypto peripheral. | RW | 0
29 | SAVE_CONTEXT | IV must be read before the AES engine can start a new operation. | RW | 0
28:25 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text) | RW | 0x0
24:22 | CCM_M | Defines M that indicates the length of the authentication field for CCM operations; the authentication field length equals two times the value of CCM_M plus one. Note: The Crypto peripheral always returns a 128-bit authentication field, of which the M least significant bytes are valid. All values are supported. | RW | 0x0
21:19 | CCM_L | Defines L that indicates the width of the length field for CCM operations; the length field in bytes equals the value of CMM_L plus one. All values are supported. | RW | 0x0
18 | CCM | AES-CCM mode enable. AES-CCM is a combined mode, using AES for both authentication and encryption. Note: Selecting AES-CCM mode requires writing of AESDATALEN1.LEN_MSW and AESDATALEN0.LEN_LSW after all other registers. Note: The CTR mode bit in this register must also be set to 1 to enable AES-CTR; selecting other AES modes than CTR mode is invalid. | RW | 0
17:16 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text) | RW | 0x0
15 | CBC_MAC | MAC mode enable. The DIR bit must be set to 1 for this mode. Selecting this mode requires writing the AESDATALEN1.LEN_MSW and AESDATALEN0.LEN_LSW registers after all other registers. | RW | 0
14:9 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text) | RW | 0x00
8:7 | CTR_WIDTH | Specifies the counter width for AES-CTR mode
Value | ENUM name | Description
0x0 | 32_BIT | 32 bits
0x1 | 64_BIT | 64 bits
0x2 | 96_BIT | 96 bits
0x3 | 128_BIT | 128 bits
| RW | 0x0
6 | CTR | AES-CTR mode enable This bit must also be set for CCM, when encryption/decryption is required. | RW | 0
5 | CBC | CBC mode enable | RW | 0
4:3 | KEY_SIZE | This field specifies the key size. The key size is automatically configured when a new key is loaded via the key store module. 00 = N/A - reserved 01 = 128 bits 10 = N/A - reserved 11 = N/A - reserved For the Crypto peripheral this field is fixed to 128 bits. | RO | 0x0
2 | DIR | Direction. 0 : Decrypt operation is performed. 1 : Encrypt operation is performed. This bit must be written with a 1 when CBC-MAC is selected. | RW | 0
1 | INPUT_RDY | If read as 1, this status bit indicates that the 16-byte AES input buffer is empty. The Host is permitted to write the next block of data. Writing a 0 clears the bit to zero and indicates that the AES engine can use the provided input data block. Writing a 1 to this bit will be ignored. Note: For DMA operations, this bit is automatically controlled by the Crypto peripheral. After reset, this bit is 0. After writing a context (note 1), this bit will become 1. For typical use, this bit does NOT need to be written, but is used for status reading only. In this case, this status bit is automatically maintained by the Crypto peripheral. | RW | 0
0 | OUTPUT_RDY | If read as 1, this status bit indicates that an AES output block is available to be retrieved by the Host. Writing a 0 clears the bit to zero and indicates that output data is read by the Host. The AES engine can provide a next output data block. Writing a 1 to this bit will be ignored. Note: For DMA operations, this bit is automatically controlled by the Crypto peripheral. For typical use, this bit does NOT need to be written, but is used for status reading only. In this case, this status bit is automatically maintained by the Crypto peripheral. | RW | 0

### TOP:CRYPTO:AESDATALEN0

Address offset | 0x0000 0554
Physical address | 0x4002 4554 | Instance | CRYPTO
Description | Crypto Data Length LSW
Type | WO

Bits | Field Name | Description | Type | Reset
31:0 | LEN_LSW | Used to write the Length values to the Crypto peripheral. This register contains bits [31:0] of the combined data length. | WO | 0x0000 0000

### TOP:CRYPTO:AESDATALEN1

Address offset | 0x0000 0558
Physical address | 0x4002 4558 | Instance | CRYPTO
Description | Crypto Data Length MSW
Type | WO

Bits | Field Name | Description | Type | Reset
31:29 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(WO std text) | WO | 0x0
28:0 | LEN_MSW | Bits [60:32] of the combined data length. Bits [60:0] of the crypto length registers AESDATALEN1 and AESDATALEN0 store the cryptographic data length in bytes for all modes. Once processing with this context is started, this length decrements to zero. Data lengths up to (2^61 - 1) bytes are allowed. For GCM, any value up to 2^36 - 32 bytes can be used. This is because a 32-bit counter mode is used; the maximum number of 128-bit blocks is 2^32 - 2, resulting in a maximum number of bytes of 2^36 - 32. Writing to this register triggers the engine to start using this context. This is valid for all modes except GCM and CCM. Note: For the combined modes (GCM and CCM), this length does not include the authentication only data; the authentication length is specified in the AESAUTHLEN.LEN. All modes must have a length > 0. For the combined modes, it is allowed to have one of the lengths equal to zero. For the basic encryption modes (ECB/CBC/CTR) it is allowed to program zero to the length field; in that case the length is assumed infinite. All data must be byte (8-bit) aligned for stream cipher modes; bit aligned data streams are not supported by the Crypto peripheral. For block cipher modes, the data length must be programmed in multiples of the block cipher size, 16 bytes. | WO | 0x0000 0000

### TOP:CRYPTO:AESAUTHLEN

Address offset | 0x0000 055C
Physical address | 0x4002 455C | Instance | CRYPTO
Description | AES Authentication Length
Type | WO

Bits | Field Name | Description | Type | Reset
31:0 | LEN | Authentication data length in bytes for combined mode, CCM only. Supported AAD-lengths for CCM are from 0 to (216 - 28) bytes. Once processing with this context is started, this length decrements to zero. Writing this register triggers the engine to start using this context for CCM. | WO | 0x0000 0000

### TOP:CRYPTO:AESDATAIN0

Address offset | 0x0000 0560
Physical address | 0x4002 4560 | Instance | CRYPTO
Description | AES Data Input/Output 0
Type | WO

Bits | Field Name | Description | Type | Reset
31:0 | DATA | Data registers for input block data to the Crypto peripheral. These bits = AES Input Data[31:0] of [127:0] For normal operations, this register is not used, since data input and output is transferred from and to the AES engine via DMA. For a Host write operation, these registers must be written with the 128-bit input block for the next AES operation. Writing at a word-aligned offset within this address range will store the word (4 bytes) of data into the corresponding position of 4-word deep (16 bytes = 128-bit AES block) data input buffer. This buffer is used for the next AES operation. If the last data block is not completely filled with valid data (see notes below), it is allowed to write only the words with valid data. Next AES operation is triggered by writing to AESCTL.INPUT_RDY. Note: AES typically operates on 128 bits block multiple input data. The CTR, GCM and CCM modes form an exception. The last block of a CTR-mode message may contain less than 128 bits (refer to [NIST 800-38A]): 0 < n <= 128 bits. For GCM/CCM, the last block of both AAD and message data may contain less than 128 bits (refer to [NIST 800-38D]). The Crypto peripheral automatically pads or masks misaligned ending data blocks with zeroes for GCM, CCM and CBC-MAC. For CTR mode, the remaining data in an unaligned data block is ignored. | WO | 0x0000 0000

### TOP:CRYPTO:AESDATAOUT0

Address offset | 0x0000 0560
Physical address | 0x4002 4560 | Instance | CRYPTO
Description | Data Input/Output
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | DATA | Data register 0 for output block data from the Crypto peripheral. These bits = AES Output Data[31:0] of {127:0] For normal operations, this register is not used, since data input and output is transferred from and to the AES engine via DMA. For a Host read operation, these registers contain the 128-bit output block from the latest AES operation. Reading from a word-aligned offset within this address range will read one word (4 bytes) of data out the 4-word deep (16 bytes = 128-bits AES block) data output buffer. The words (4 words, one full block) should be read before the core will move the next block to the data output buffer. To empty the data output buffer, AESCTL.OUTPUT_RDY must be written. For the modes with authentication (CBC-MAC, GCM and CCM), the invalid (message) bytes/words can be written with any data. Note: The AAD / authentication only data is not copied to the output buffer but only used for authentication. | RO | 0x0000 0000

### TOP:CRYPTO:AESDATAIN1

Address offset | 0x0000 0564
Physical address | 0x4002 4564 | Instance | CRYPTO
Description | AES Data Input/Output 1
Type | WO

Bits | Field Name | Description | Type | Reset
31:0 | DATA | Data registers for input block data to the Crypto peripheral. These bits = AES Input Data[63:32] of [127:0] For normal operations, this register is not used, since data input and output is transferred from and to the AES engine via DMA. For a Host write operation, these registers must be written with the 128-bit input block for the next AES operation. Writing at a word-aligned offset within this address range will store the word (4 bytes) of data into the corresponding position of 4-word deep (16 bytes = 128-bit AES block) data input buffer. This buffer is used for the next AES operation. If the last data block is not completely filled with valid data (see notes below), it is allowed to write only the words with valid data. Next AES operation is triggered by writing to AESCTL.INPUT_RDY. Note: AES typically operates on 128 bits block multiple input data. The CTR, GCM and CCM modes form an exception. The last block of a CTR-mode message may contain less than 128 bits (refer to [NIST 800-38A]): 0 < n <= 128 bits. For GCM/CCM, the last block of both AAD and message data may contain less than 128 bits (refer to [NIST 800-38D]). The Crypto peripheral automatically pads or masks misaligned ending data blocks with zeroes for GCM, CCM and CBC-MAC. For CTR mode, the remaining data in an unaligned data block is ignored. | WO | 0x0000 0000

### TOP:CRYPTO:AESDATAOUT1

Address offset | 0x0000 0564
Physical address | 0x4002 4564 | Instance | CRYPTO
Description | AES Data Input/Output 3
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | DATA | Data registers for output block data from the Crypto peripheral. These bits = AES Output Data[63:32] of [127:0] For normal operations, this register is not used, since data input and output is transferred from and to the AES engine via DMA. For a Host read operation, these registers contain the 128-bit output block from the latest AES operation. Reading from a word-aligned offset within this address range will read one word (4 bytes) of data out the 4-word deep (16 bytes = 128-bits AES block) data output buffer. The words (4 words, one full block) should be read before the core will move the next block to the data output buffer. To empty the data output buffer, AESCTL.OUTPUT_RDY must be written. For the modes with authentication (CBC-MAC, GCM and CCM), the invalid (message) bytes/words can be written with any data. Note: The AAD / authentication only data is not copied to the output buffer but only used for authentication. | RO | 0x0000 0000

### TOP:CRYPTO:AESDATAIN2

Address offset | 0x0000 0568
Physical address | 0x4002 4568 | Instance | CRYPTO
Description | AES Data Input/Output 2
Type | WO

Bits | Field Name | Description | Type | Reset
31:0 | DATA | Data registers for input block data to the Crypto peripheral. These bits = AES Input Data[95:64] of [127:0] For normal operations, this register is not used, since data input and output is transferred from and to the AES engine via DMA. For a Host write operation, these registers must be written with the 128-bit input block for the next AES operation. Writing at a word-aligned offset within this address range will store the word (4 bytes) of data into the corresponding position of 4-word deep (16 bytes = 128-bit AES block) data input buffer. This buffer is used for the next AES operation. If the last data block is not completely filled with valid data (see notes below), it is allowed to write only the words with valid data. Next AES operation is triggered by writing to AESCTL.INPUT_RDY. Note: AES typically operates on 128 bits block multiple input data. The CTR, GCM and CCM modes form an exception. The last block of a CTR-mode message may contain less than 128 bits (refer to [NIST 800-38A]): 0 < n <= 128 bits. For GCM/CCM, the last block of both AAD and message data may contain less than 128 bits (refer to [NIST 800-38D]). The Crypto peripheral automatically pads or masks misaligned ending data blocks with zeroes for GCM, CCM and CBC-MAC. For CTR mode, the remaining data in an unaligned data block is ignored. | WO | 0x0000 0000

### TOP:CRYPTO:AESDATAOUT2

Address offset | 0x0000 0568
Physical address | 0x4002 4568 | Instance | CRYPTO
Description | AES Data Input/Output 2
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | DATA | Data registers for output block data from the Crypto peripheral. These bits = AES Output Data[95:64] of [127:0] For normal operations, this register is not used, since data input and output is transferred from and to the AES engine via DMA. For a Host read operation, these registers contain the 128-bit output block from the latest AES operation. Reading from a word-aligned offset within this address range will read one word (4 bytes) of data out the 4-word deep (16 bytes = 128-bits AES block) data output buffer. The words (4 words, one full block) should be read before the core will move the next block to the data output buffer. To empty the data output buffer, AESCTL.OUTPUT_RDY must be written. For the modes with authentication (CBC-MAC, GCM and CCM), the invalid (message) bytes/words can be written with any data. Note: The AAD / authentication only data is not copied to the output buffer but only used for authentication. | RO | 0x0000 0000

### TOP:CRYPTO:AESDATAIN3

Address offset | 0x0000 056C
Physical address | 0x4002 456C | Instance | CRYPTO
Description | Data Input/Output
Type | WO

Bits | Field Name | Description | Type | Reset
31:0 | DATA | Data registers for input block data to the Crypto peripheral. These bits = AES Input Data[127:96] of [127:0] For normal operations, this register is not used, since data input and output is transferred from and to the AES engine via DMA. For a Host write operation, these registers must be written with the 128-bit input block for the next AES operation. Writing at a word-aligned offset within this address range will store the word (4 bytes) of data into the corresponding position of 4-word deep (16 bytes = 128-bit AES block) data input buffer. This buffer is used for the next AES operation. If the last data block is not completely filled with valid data (see notes below), it is allowed to write only the words with valid data. Next AES operation is triggered by writing to AESCTL.INPUT_RDY. Note: AES typically operates on 128 bits block multiple input data. The CTR, GCM and CCM modes form an exception. The last block of a CTR-mode message may contain less than 128 bits (refer to [NIST 800-38A]): 0 < n <= 128 bits. For GCM/CCM, the last block of both AAD and message data may contain less than 128 bits (refer to [NIST 800-38D]). The Crypto peripheral automatically pads or masks misaligned ending data blocks with zeroes for GCM, CCM and CBC-MAC. For CTR mode, the remaining data in an unaligned data block is ignored. | WO | 0x0000 0000

### TOP:CRYPTO:AESDATAOUT3

Address offset | 0x0000 056C
Physical address | 0x4002 456C | Instance | CRYPTO
Description | AES Data Input/Output 3
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | DATA | Data registers for output block data from the Crypto peripheral. These bits = AES Output Data[127:96] of [127:0] For normal operations, this register is not used, since data input and output is transferred from and to the AES engine via DMA. For a Host read operation, these registers contain the 128-bit output block from the latest AES operation. Reading from a word-aligned offset within this address range will read one word (4 bytes) of data out the 4-word deep (16 bytes = 128-bits AES block) data output buffer. The words (4 words, one full block) should be read before the core will move the next block to the data output buffer. To empty the data output buffer, AESCTL.OUTPUT_RDY must be written. For the modes with authentication (CBC-MAC, GCM and CCM), the invalid (message) bytes/words can be written with any data. Note: The AAD / authentication only data is not copied to the output buffer but only used for authentication. | RO | 0x0000 0000

### TOP:CRYPTO:AESTAGOUT__0-AESTAGOUT__3

Address offset | 0x0000 0570-0x0000 057C
Physical address | 0x4002 4570- 0x4002 457C | Instance | CRYPTO
Description | AES Tag Output
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | TAG | This register contains the authentication TAG for the combined and authentication-only modes. | RO | 0x0000 0000

### TOP:CRYPTO:ALGSEL

Address offset | 0x0000 0700
Physical address | 0x4002 4700 | Instance | CRYPTO
Description | Master Algorithm Select This register configures the internal destination of the DMA controller.
Type | RW

Bits | Field Name | Description | Type | Reset
31 | TAG | If this bit is cleared to 0, the DMA operation involves only data. If this bit is set, the DMA operation includes a TAG (Authentication Result / Digest). | RW | 0
30:2 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text) | RW | 0x0000 0000
1 | AES | If set to 1, the AES data is loaded via DMA Both Read and Write maximum transfer size to DMA engine is set to 16 bytes | RW | 0
0 | KEY_STORE | If set to 1, selects the Key Store to be loaded via DMA. The maximum transfer size to DMA engine is set to 32 bytes (however transfers of 16, 24 and 32 bytes are allowed) | RW | 0

### TOP:CRYPTO:DMAPROTCTL

Address offset | 0x0000 0704
Physical address | 0x4002 4704 | Instance | CRYPTO
Description | Master Protection Control
Type | RW

Bits | Field Name | Description | Type | Reset
31:1 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text) | RW | 0x0000 0000
0 | EN | Select AHB transfer protection control for DMA transfers using the key store area as destination. 0 : transfers use 'USER' type access. 1 : transfers use 'PRIVILEGED' type access. | RW | 0

### TOP:CRYPTO:SWRESET

Address offset | 0x0000 0740
Physical address | 0x4002 4740 | Instance | CRYPTO
Description | Software Reset
Type | RW

Bits | Field Name | Description | Type | Reset
31:1 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text) | RW | 0x0000 0000
0 | RESET | If this bit is set to 1, the following modules are reset: - Master control internal state is reset. That includes interrupt, error status register and result available interrupt generation FSM. - Key store module state is reset. That includes clearing the Written Area flags; therefore the keys must be reloaded to the key store module. Writing 0 has no effect. The bit is self cleared after executing the reset. | RW | 0

### TOP:CRYPTO:IRQTYPE

Address offset | 0x0000 0780
Physical address | 0x4002 4780 | Instance | CRYPTO
Description | Interrupt Configuration
Type | RW

Bits | Field Name | Description | Type | Reset
31:1 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text) | RW | 0x0000 0000
0 | IEN | Interrupt enable. This bit must be set to 1 to enable interrupts from the Crypto peripheral. 0 : All interrupts are disabled enabled. 1 : All interrupts are enabled. | RW | 0

### TOP:CRYPTO:IRQEN

Address offset | 0x0000 0784
Physical address | 0x4002 4784 | Instance | CRYPTO
Description | Interrupt Enable
Type | RW

Bits | Field Name | Description | Type | Reset
31:2 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text) | RW | 0x0000 0000
1 | DMA_IN_DONE | This bit enables IRQSTAT.DMA_IN_DONE as source for IRQ. | RW | 0
0 | RESULT_AVAIL | This bit enables IRQSTAT.RESULT_AVAIL as source for IRQ. | RW | 0

### TOP:CRYPTO:IRQCLR

Address offset | 0x0000 0788
Physical address | 0x4002 4788 | Instance | CRYPTO
Description | Interrupt Clear
Type | WO

Bits | Field Name | Description | Type | Reset
31 | DMA_BUS_ERR | If 1 is written to this bit, IRQSTAT.DMA_BUS_ERR is cleared. | WO | 0
30 | KEY_ST_WR_ERR | If 1 is written to this bit, IRQSTAT.KEY_ST_WR_ERR is cleared. | WO | 0
29 | KEY_ST_RD_ERR | If 1 is written to this bit, IRQSTAT.KEY_ST_RD_ERR is cleared. | WO | 0
28:2 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(WO std text) | WO | 0x000 0000
1 | DMA_IN_DONE | If 1 is written to this bit, IRQSTAT.DMA_IN_DONE is cleared. | WO | 0
0 | RESULT_AVAIL | If 1 is written to this bit, IRQSTAT.RESULT_AVAIL is cleared. | WO | 0

### TOP:CRYPTO:IRQSET

Address offset | 0x0000 078C
Physical address | 0x4002 478C | Instance | CRYPTO
Description | Interrupt Set
Type | WO

Bits | Field Name | Description | Type | Reset
31:2 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(WO std text) | WO | 0x0000 0000
1 | DMA_IN_DONE | If 1 is written to this bit, IRQSTAT.DMA_IN_DONE is set. Writing 0 has no effect. | WO | 0
0 | RESULT_AVAIL | If 1 is written to this bit, IRQSTAT.RESULT_AVAIL is set. Writing 0 has no effect. | WO | 0

### TOP:CRYPTO:IRQSTAT

Address offset | 0x0000 0790
Physical address | 0x4002 4790 | Instance | CRYPTO
Description | Interrupt Status
Type | RO

Bits | Field Name | Description | Type | Reset
31 | DMA_BUS_ERR | This bit is set when a DMA bus error is detected during a DMA operation. The value of this register is held until it is cleared via IRQCLR.DMA_BUS_ERR Note: This error is asserted if an error is detected on the AHB master interface during a DMA operation. Note: This is not an interrupt source. | RO | 0
30 | KEY_ST_WR_ERR | This bit is set when a write error is detected during the DMA write operation to the key store memory. The value of this register is held until it is cleared via IRQCLR.KEY_ST_WR_ERR Note: This error is asserted if a DMA operation does not cover a full key area or more areas are written than expected. Note: This is not an interrupt source. | RO | 0
29 | KEY_ST_RD_ERR | This bit will be set when a read error is detected during the read of a key from the key store, while copying it to the AES engine. The value of this register is held until it is cleared via IRQCLR.KEY_ST_RD_ERR. Note: This error is asserted if a key location is selected in the key store that is not available. Note: This is not an interrupt source. | RO | 0
28:2 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x000 0000
1 | DMA_IN_DONE | This bit returns the status of DMA data in done interrupt. | RO | 0
0 | RESULT_AVAIL | This bit is set high when the Crypto peripheral has a result available. | RO | 0

### TOP:CRYPTO:HWVER

Address offset | 0x0000 07FC
Physical address | 0x4002 47FC | Instance | CRYPTO
Description | CTRL Module Version
Type | RO

Bits | Field Name | Description | Type | Reset
31:28 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x9
27:24 | HW_MAJOR_VER | Major version number | RO | 0x1
23:20 | HW_MINOR_VER | Minor version number | RO | 0x1
19:16 | HW_PATCH_LVL | Patch level, starts at 0 at first delivery of this version. | RO | 0x1
15:8 | VER_NUM_COMPL | These bits simply contain the complement of VER_NUM (0x87), used by a driver to ascertain that the Crypto peripheral register is indeed read. | RO | 0x87
7:0 | VER_NUM | The version number for the Crypto peripheral, this field contains the value 120 (decimal) or 0x78. | RO | 0x78