## AON_RTC

Instance: AON_RTC
Component: AON_RTC
Base address: 0x40092000

This component control the Real Time Clock residing in AON
Note: This module is only supporting 32 bit ReadWrite access.

### TOP:AON_RTC Register Summary

Register Name | Type | Register Width (Bits) | Register Reset | Address Offset | Physical Address
CTL | RW | 32 | 0x0000 0000 | 0x0000 0000 | 0x4009 2000
EVFLAGS | RW | 32 | 0x0000 0000 | 0x0000 0004 | 0x4009 2004
SEC | RW | 32 | 0x0000 0000 | 0x0000 0008 | 0x4009 2008
SUBSEC | RW | 32 | 0x0000 0000 | 0x0000 000C | 0x4009 200C
SUBSECINC | RO | 32 | 0x0080 0000 | 0x0000 0010 | 0x4009 2010
CHCTL | RW | 32 | 0x0000 0000 | 0x0000 0014 | 0x4009 2014
CH0CMP | RW | 32 | 0x0000 0000 | 0x0000 0018 | 0x4009 2018
CH1CMP | RW | 32 | 0x0000 0000 | 0x0000 001C | 0x4009 201C
CH2CMP | RW | 32 | 0x0000 0000 | 0x0000 0020 | 0x4009 2020
CH2CMPINC | RW | 32 | 0x0000 0000 | 0x0000 0024 | 0x4009 2024
CH1CAPT | RO | 32 | 0x0000 0000 | 0x0000 0028 | 0x4009 2028
SYNC | RW | 32 | 0x0000 0000 | 0x0000 002C | 0x4009 202C

### TOP:AON_RTC Register Descriptions

### TOP:AON_RTC:CTL

Address offset | 0x0000 0000
Physical address | 0x4009 2000 | Instance | AON_RTC
Description | RTC Control Register This register contains various bitfields for configuration of RTC
Type | RW

Bits | Field Name | Description | Type | Reset
31:19 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0000
18:16 | COMB_EV_MASK | Eventmask selecting which delayed events that form the combined event. Enumeration values can be combined with a logical or.
Value | ENUM name | Description
0x0 | NONE | No event is selected for combined event.
0x1 | CH0 | Use Channel 0 delayed event in combined event
0x2 | CH1 | Use Channel 1 delayed event in combined event
0x4 | CH2 | Use Channel 2 delayed event in combined event
| RW | 0x0
15:12 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0
11:8 | EV_DELAY | Number of SCLK_LF clock cycles waited before generating delayed events. (Common setting for all RTC cannels) the delayed event is delayed
Value | ENUM name | Description
0x0 | D0 | No delay on delayed event
0x1 | D1 | Delay by 1 clock cycles
0x2 | D2 | Delay by 2 clock cycles
0x3 | D4 | Delay by 4 clock cycles
0x4 | D8 | Delay by 8 clock cycles
0x5 | D16 | Delay by 16 clock cycles
0x6 | D32 | Delay by 32 clock cycles
0x7 | D48 | Delay by 48 clock cycles
0x8 | D64 | Delay by 64 clock cycles
0x9 | D80 | Delay by 80 clock cycles
0xA | D96 | Delay by 96 clock cycles
0xB | D112 | Delay by 112 clock cycles
0xC | D128 | Delay by 128 clock cycles
0xD | D144 | Delay by 144 clock cycles
| RW | 0x0
7 | RESET | RTC Counter reset. Writing 1 to this bit will reset the RTC counter. This bit is cleared when reset takes effect | WO | 0
6:3 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0
2 | RTC_4KHZ_EN | RTC_4KHZ is a 4 KHz reference output, tapped from [SUBSEC:VALUE] bit 19 which is used by AUX timer. 0: RTC_4KHZ signal is forced to 0 1: RTC_4KHZ is enabled ( provied that RTC is enabled EN) | RW | 0
1 | RTC_UPD_EN | RTC_UPD is a 16 KHz signal used to sync up the radio timer. The 16 Khz is SCLK_LF divided by 2 0: RTC_UPD signal is forced to 0 1: RTC_UPD signal is toggling @16 kHz | RW | 0
0 | EN | Enable RTC counter 0: Halted (frozen) 1: Running | RW | 0

### TOP:AON_RTC:EVFLAGS

Address offset | 0x0000 0004
Physical address | 0x4009 2004 | Instance | AON_RTC
Description | RTC Status Register This register contains event flags from the 3 RTC channels.. Each flag will be cleared when writing a '1' to the corresponding bitfield.
Type | RW

Bits | Field Name | Description | Type | Reset
31:17 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0000
16 | CH2 | Channel 2 event flag, set when CHCTL.CH2_EN = 1 and the RTC value matches or passes the CH2CMP value. An event will be scheduled to occur as soon as possible when writing to CH2CMP provided that the channel is enabled and the new value matches any time between next RTC value and 1 second in the past Writing 1 clears this flag. Note that a new event can not occur on this channel in first 2 SCLK_LF cycles after a clearance. AUX_SCE can read the flag through AUX_WUC:WUEVFLAGS.AON_RTC and clear it using AUX_WUC:WUEVCLR.AON_RTC. | RW | 0
15:9 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x00
8 | CH1 | Channel 1 event flag, set when CHCTL.CH1_EN = 1 and one of the following: - CHCTL.CH1_CAPT_EN = 0 and the RTC value matches or passes the CH1CMP value. - CHCTL.CH1_CAPT_EN = 1 and capture occurs. An event will be scheduled to occur as soon as possible when writing to CH1CMP provided that the channel is enabled, in compare mode and the new value matches any time between next RTC value and 1 second in the past. Writing 1 clears this flag. Note that a new event can not occur on this channel in first 2 SCLK_LF cycles after a clearance. | RW | 0
7:1 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x00
0 | CH0 | Channel 0 event flag, set when CHCTL.CH0_EN = 1 and the RTC value matches or passes the CH0CMP value. An event will be scheduled to occur as soon as possible when writing to CH0CMP provided that the channels is enabled and the new value matches any time between next RTC value and 1 second in the past. Writing 1 clears this flag. Note that a new event can not occur on this channel in first 2 SCLK_LF cycles after a clearance. | RW | 0

### TOP:AON_RTC:SEC

Address offset | 0x0000 0008
Physical address | 0x4009 2008 | Instance | AON_RTC
Description | Second Counter Value, Integer Part
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | VALUE | Unsigned integer representing Real Time Clock in seconds. When reading this register the content of SUBSEC.VALUE is simultaneously latched. A consistent reading of the combined Real Time Clock can be obtained by first reading this register, then reading SUBSEC register. | RW | 0x0000 0000

### TOP:AON_RTC:SUBSEC

Address offset | 0x0000 000C
Physical address | 0x4009 200C | Instance | AON_RTC
Description | Second Counter Value, Fractional Part
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | VALUE | Unsigned integer representing Real Time Clock in fractions of a second (VALUE/2^32 seconds) at the time when SEC register was read. Examples : - 0x0000_0000 = 0.0 sec - 0x4000_0000 = 0.25 sec - 0x8000_0000 = 0.5 sec - 0xC000_0000 = 0.75 sec | RW | 0x0000 0000

### TOP:AON_RTC:SUBSECINC

Address offset | 0x0000 0010
Physical address | 0x4009 2010 | Instance | AON_RTC
Description | Subseconds Increment Register Value added to SUBSEC.VALUE on every **SCLK_LF **clock cycle.
Type | RO

Bits | Field Name | Description | Type | Reset
31:24 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x00
23:0 | VALUEINC | This value compensates for a SCLK_LF clock which has an offset from 32768 Hz. The compensation value can be found as 2^38 / freq, where freq is SCLK_LF clock frequency in Hertz This value is added to SUBSEC.VALUE on every cycle, and carry of this is added to SEC.VALUE. To perform the addition, bits [23:6] are aligned with SUBSEC.VALUE bits [17:0]. The remaining bits [5:0] are accumulated in a hidden 6-bit register that generates a carry into the above mentioned addition on overflow. The default value corresponds to incrementing by precisely 1/32768 of a second. NOTE: This register is read only. Modification of the register value must be done using registers AUX_WUC:RTCSUBSECINC1 , AUX_WUC:RTCSUBSECINC0 and AUX_WUC:RTCSUBSECINCCTL | RO | 0x80 0000

### TOP:AON_RTC:CHCTL

Address offset | 0x0000 0014
Physical address | 0x4009 2014 | Instance | AON_RTC
Description | Channel Configuration Register
Type | RW

Bits | Field Name | Description | Type | Reset
31:19 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0000
18 | CH2_CONT_EN | Set to enable continuous opereation of Channel 2 | RW | 0
17 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0
16 | CH2_EN | RTC Channel 2 Enable 0: Disable RTC Channel 2 1: Enable RTC Channel 2 | RW | 0
15:10 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x00
9 | CH1_CAPT_EN | Set Channel 1 mode 0: Compare mode (default) 1: Capture mode | RW | 0
8 | CH1_EN | RTC Channel 1 Enable 0: Disable RTC Channel 1 1: Enable RTC Channel 1 | RW | 0
7:1 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x00
0 | CH0_EN | RTC Channel 0 Enable 0: Disable RTC Channel 0 1: Enable RTC Channel 0 | RW | 0

### TOP:AON_RTC:CH0CMP

Address offset | 0x0000 0018
Physical address | 0x4009 2018 | Instance | AON_RTC
Description | Channel 0 Compare Value
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | VALUE | RTC Channel 0 compare value. Bit 31 to 16 represents seconds and bits 15 to 0 represents subseconds of the compare value. The compare value is compared against SEC.VALUE (15:0) and SUBSEC.VALUE (31:16) values of the Real Time Clock register. A Cannel 0 event is generated when {SEC.VALUE(15:0),SUBSEC.VALUE (31:16)} is reaching or exciting the compare value. Writing to this register can trigger an immediate*) event in case the new compare value matches a Real Time Clock value from 1 second in the past up till current Real Time Clock value. Example: To generate a compare 5.5 seconds RTC start,- set this value = 0x0005_8000 *) It can take up to 2 SCLK_LF clock cycles before event occurs due to synchronization. | RW | 0x0000 0000

### TOP:AON_RTC:CH1CMP

Address offset | 0x0000 001C
Physical address | 0x4009 201C | Instance | AON_RTC
Description | Channel 1 Compare Value
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | VALUE | RTC Channel 1 compare value. Bit 31 to 16 represents seconds and bits 15 to 0 represents subseconds of the compare value. The compare value is compared against SEC.VALUE (15:0) and SUBSEC.VALUE (31:16) values of the Real Time Clock register. A Cannel 0 event is generated when {SEC.VALUE(15:0),SUBSEC.VALUE (31:16)} is reaching or exciting the compare value. Writing to this register can trigger an immediate*) event in case the new compare value matches a Real Time Clock value from 1 second in the past up till current Real Time Clock value. Example: To generate a compare 5.5 seconds RTC start,- set this value = 0x0005_8000 *) It can take up to 2 SCLK_LF clock cycles before event occurs due to synchronization. | RW | 0x0000 0000

### TOP:AON_RTC:CH2CMP

Address offset | 0x0000 0020
Physical address | 0x4009 2020 | Instance | AON_RTC
Description | Channel 2 Compare Value
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | VALUE | RTC Channel 2 compare value. Bit 31 to 16 represents seconds and bits 15 to 0 represents subseconds of the compare value. The compare value is compared against SEC.VALUE (15:0) and SUBSEC.VALUE (31:16) values of the Real Time Clock register. A Cannel 0 event is generated when {SEC.VALUE(15:0),SUBSEC.VALUE (31:16)} is reaching or exciting the compare value. Writing to this register can trigger an immediate*) event in case the new compare value matches a Real Time Clock value from 1 second in the past up till current Real Time Clock value. Example: To generate a compare 5.5 seconds RTC start,- set this value = 0x0005_8000 *) It can take up to 2 SCLK_LF clock cycles before event occurs due to synchronization. | RW | 0x0000 0000

### TOP:AON_RTC:CH2CMPINC

Address offset | 0x0000 0024
Physical address | 0x4009 2024 | Instance | AON_RTC
Description | Channel 2 Compare Value Auto-increment This register is primarily used to generate periodical wake-up for the AUX_SCE module, through the [AUX_EVCTL.EVSTAT0.AON_RTC] event.
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | VALUE | If CHCTL.CH2_CONT_EN is set, this value is added to CH2CMP.VALUE on every channel 2 compare event. | RW | 0x0000 0000

### TOP:AON_RTC:CH1CAPT

Address offset | 0x0000 0028
Physical address | 0x4009 2028 | Instance | AON_RTC
Description | Channel 1 Capture Value If CHCTL.CH1_EN = 1and CHCTL.CH1_CAPT_EN = 1, capture occurs on each rising edge of the event selected in AON_EVENT:RTCSEL.
Type | RO

Bits | Field Name | Description | Type | Reset
31:16 | SEC | Value of SEC.VALUE bits 15:0 at capture time. | RO | 0x0000
15:0 | SUBSEC | Value of SUBSEC.VALUE bits 31:16 at capture time. | RO | 0x0000

### TOP:AON_RTC:SYNC

Address offset | 0x0000 002C
Physical address | 0x4009 202C | Instance | AON_RTC
Description | AON Synchronization Register This register is used for synchronizing between MCU and entire AON domain.
Type | RW

Bits | Field Name | Description | Type | Reset
31:1 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0000 0000
0 | WBUSY | This register will always return 0,- however it will not return the value until there are no outstanding write requests between MCU and AON Note: Writing to this register prior to reading will force a wait until next SCLK_LF edge. This is recommended for syncing read registers from AON when waking up from sleep Failure to do so may result in reading AON values from prior to going to sleep | RW | 0