## ADI_0_RF

Instance: ADI_0_RF
Component: ADI_0_RF
Base address: 0x0

ADI for LNA, IFAMP, PA, IFADC modules.
Registers Fields should be considered static unless otherwise noted (as dynamic)

### TOP:ADI_0_RF Register Summary

Register Name | Type | Register Width (Bits) | Register Reset | Address Offset | Physical Address
LNACTL0 | RW | 8 | 0x0000 0000 | 0x0000 0000 | 0x0000 0000
LNACTL1 | RW | 8 | 0x0000 0000 | 0x0000 0001 | 0x0000 0001
LNACTL2 | RW | 8 | 0x0000 0000 | 0x0000 0002 | 0x0000 0002
IFAMPCTL0 | RW | 8 | 0x0000 0000 | 0x0000 0003 | 0x0000 0003
IFAMPCTL1 | RW | 8 | 0x0000 0000 | 0x0000 0004 | 0x0000 0004
IFAMPCTL2 | RW | 8 | 0x0000 0000 | 0x0000 0005 | 0x0000 0005
PACTL0 | RW | 8 | 0x0000 0000 | 0x0000 0006 | 0x0000 0006
PACTL1 | RW | 8 | 0x0000 0000 | 0x0000 0007 | 0x0000 0007
PACTL2 | RW | 8 | 0x0000 0000 | 0x0000 0008 | 0x0000 0008
RFLDO0 | RW | 8 | 0x0000 0000 | 0x0000 0009 | 0x0000 0009
RFLDO1 | RW | 8 | 0x0000 0000 | 0x0000 000A | 0x0000 000A
RFLDO2 | RW | 8 | 0x0000 0000 | 0x0000 000B | 0x0000 000B
IFADCCTL0 | RW | 8 | 0x0000 0000 | 0x0000 000C | 0x0000 000C
IFADCLFCFG0 | RW | 8 | 0x0000 0000 | 0x0000 000D | 0x0000 000D
IFADCLFCFG1 | RW | 8 | 0x0000 0000 | 0x0000 000E | 0x0000 000E
IFADCDAC | RW | 8 | 0x0000 0000 | 0x0000 000F | 0x0000 000F
IFADCQUANT0 | RW | 8 | 0x0000 0000 | 0x0000 0010 | 0x0000 0010
IFADCCTL1 | RW | 8 | 0x0000 0000 | 0x0000 0012 | 0x0000 0012
IFADCCTL2 | RW | 8 | 0x0000 0000 | 0x0000 0013 | 0x0000 0013
IFALDO1 | RW | 8 | 0x0000 0000 | 0x0000 0018 | 0x0000 0018
IFALDO2 | RW | 8 | 0x0000 0000 | 0x0000 0019 | 0x0000 0019
IFALDO3 | RW | 8 | 0x0000 0000 | 0x0000 001A | 0x0000 001A
IFDLDO1 | RW | 8 | 0x0000 0000 | 0x0000 001B | 0x0000 001B
IFDLDO2 | RW | 8 | 0x0000 0000 | 0x0000 001C | 0x0000 001C
IFDLDO3 | RW | 8 | 0x0000 0000 | 0x0000 001D | 0x0000 001D
IFAMPCTL3 | RW | 8 | 0x0000 0000 | 0x0000 001E | 0x0000 001E
STAT | RO | 8 | 0x0000 0000 | 0x0000 001F | 0x0000 001F

### TOP:ADI_0_RF Register Descriptions

### TOP:ADI_0_RF:LNACTL0

Address offset | 0x0000 0000
Physical address | 0x0000 0000 | Instance | ADI_0_RF
Description | LNA and Antenna Diversity Control
Type | RW

Bits | Field Name | Description | Type | Reset
7:4 | MIX_AD | Antenna diversity control in mixers. Other bit combinations than the enumerated ones are illegal.
Value | ENUM name | Description
0x0 | MIX_DIFF_MODE | Differential mode.
0x5 | MIX_SE_RFP | I-channel and Q-channel mixers are single balanced and connected to RFP LNA.
0xA | MIX_SE_RFN | I-channel and Q-channel mixers are single balanced and connected to RFN LNA.
| RW | 0x0
3:2 | LNA_AD | Antenna diversity control. Other bit combinations than the enumerated ones are not allowed.
Value | ENUM name | Description
0x0 | LNA_DIFF_MODE | LNA is in differential mode and utilizes RFP and RFN.
0x1 | LNA_SE_RFP | LNA is single ended and connected to RFP.
0x2 | LNA_SE_RFN | LNA is single ended and connected to RFN.
| RW | 0x0
1 | BIAS_DIS | Disable dummy bias current. 0: Dummy bias current on (Default) 1: Dummy bias current off | RW | 0
0 | EN | LNA enable signal.
Value | ENUM name | Description
0 | DIS | Disable
1 | EN | Enable
| RW | 0

### TOP:ADI_0_RF:LNACTL1

Address offset | 0x0000 0001
Physical address | 0x0000 0001 | Instance | ADI_0_RF
Description | LNA Gain and Input Device Control
Type | RW

Bits | Field Name | Description | Type | Reset
7:6 | RESERVED6 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RW | 0x0
5:4 | DEV_CTL | LNA input device control. 00: Half of input devices on with capacitor cross coupling. Default setting in differential mode. See LNACTL0.LNA_AD. 01: All devices on with capacitor cross coupling to half the devices. 10: All devices on, no cross coupling. Default setting in single ended mode. 11: 1/4 of input devices on, no cross coupling, gain is reduced by 3dB compared to '00' setting. Part of AGC when using differential mode. | RW | 0x0
3:0 | GAIN | LNA gain control. Thermometer encoded. All other values are not supported.
Value | ENUM name | Description
0x0 | MAX_MINUS_12 | LNA gain set to -12 dB
0x1 | MAX_MINUS_9 | LNA gain set to -9 dB
0x3 | MAX_MINUS_6 | LNA gain set to -6 dB
0x7 | MAX_MINUS_3 | LNA gain set to -3 dB
0xF | MAX | LNA gain set to 0 dB
| RW | 0x0

### TOP:ADI_0_RF:LNACTL2

Address offset | 0x0000 0002
Physical address | 0x0000 0002 | Instance | ADI_0_RF
Description | LNA Bias and RXTX Pin Control
Type | RW

Bits | Field Name | Description | Type | Reset
7:6 | RXTX_PIN | Control of RXTX pin. TheRXTXpin is used when LNA uses external bias. See LNACTL2.EXT_BIAS. 00: RXTXpin = 0 (RX) 01: RXTXpin = high impedance (TX) 10: RXTXpin = 0 11: RXTXpin = 1 | RW | 0x0
5 | RESERVED5 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RW | 0
4 | EXT_BIAS | LNA bias method 0: LNA is biased with internal resistors. 1: LNA is biased externally through balun. | RW | 0
3:0 | IB | LNA bias current control. Linear steps. Will be trimmed in production test. 0x0: Minimum 0xF: Maximum | RW | 0x0

### TOP:ADI_0_RF:IFAMPCTL0

Address offset | 0x0000 0003
Physical address | 0x0000 0003 | Instance | ADI_0_RF
Description | IFAMP Control
Type | RW

Bits | Field Name | Description | Type | Reset
7:3 | TRIM | Trim bits for IFAMP gain. The trim circuit consist of a binary weighted resistor ladder which gives a non-linear gain versus bit value curve. 0x00: Max gain (default setting) 0x1F: Min gain | RW | 0x00
2 | BIAS_DIS | Disable dummy bias current. 0: Dummy bias current on (Default) 1: Dummy bias current off | RW | 0
1 | EN_Q | Q-channel IFAMP enable signal
Value | ENUM name | Description
0 | DIS | Disable
1 | EN | Enable
| RW | 0
0 | EN_I | I-channel IFAMP enable signal
Value | ENUM name | Description
0 | DIS | Disable
1 | EN | Enable
| RW | 0

### TOP:ADI_0_RF:IFAMPCTL1

Address offset | 0x0000 0004
Physical address | 0x0000 0004 | Instance | ADI_0_RF
Description | IFAMP Gain Control
Type | RW

Bits | Field Name | Description | Type | Reset
7:6 | RESERVED6 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RW | 0x0
5:0 | GAIN | IFAMP gain control. Thermometer encoded. 0x00: Min gain (Max - 18.0dB) 0x01: Max gain - 15.0dB 0x03: Max gain - 12.0dB 0x07: Max gain - 9.0dB 0x0F: Max gain - 6.0dB 0x1F: Max gain - 3.0dB 0x3F: Max gain All other values are not supported.
Value | ENUM name | Description
0x00 | MAX_MINUS_18 | IFAMP gain set to maximum -18 dB
0x01 | MAX_MINUS_15 | IFAMP gain set to maximum -15 dB
0x03 | MAX_MINUS_12 | IFAMP gain set to maximum -12 dB
0x07 | MAX_MINUS_9 | IFAMP gain set to maximum -9 dB
0x0F | MAX_MINUS_6 | IFAMP gain set to maximum -6 dB
0x1F | MAX_MINUS_3 | IFAMP gain set to maximum -3 dB
0x3F | MAX | IFAMP gain set to maximum
| RW | 0x00

### TOP:ADI_0_RF:IFAMPCTL2

Address offset | 0x0000 0005
Physical address | 0x0000 0005 | Instance | ADI_0_RF
Description | IFAMP Output Attenuation Control
Type | RW

Bits | Field Name | Description | Type | Reset
7:3 | RESERVED3 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RW | 0x00
2:0 | ATTN | IFAMP output attenuation control in 3 dB steps
Value | ENUM name | Description
0x0 | MIN | 0 dB
0x1 | MINUS_3 | -3 dB
0x2 | MINUS_6 | -6 dB
0x3 | MINUS_9 | -9 dB
0x4 | MINUS_12 | -12 dB
0x5 | MINUS_15 | -15 dB
0x6 | MINUS_18 | -18 dB
0x7 | MINUS_21 | -21 dB
|  | 0x0

### TOP:ADI_0_RF:PACTL0

Address offset | 0x0000 0006
Physical address | 0x0000 0006 | Instance | ADI_0_RF
Description | PA Control
Type | RW

Bits | Field Name | Description | Type | Reset
7:3 | TRIM | Trim of bias current to get constant output power over process and temperature. Will be trimmed in production test. 0x00: Minimum 0x1F: Maximum | RW | 0x00
2 | PEAKDET_EN | PA peakdetect circuit enable signal.
Value | ENUM name | Description
0 | DIS | Disable
1 | EN | Enable
| RW | 0
1 | BIAS_DIS | Disable dummy bias current. 0: Dummy bias current on (Default) 1: Dummy bias current off | RW | 0
0 | EN | PA enable signal.
Value | ENUM name | Description
0 | DIS | Disable
1 | EN | Enable
| RW | 0

### TOP:ADI_0_RF:PACTL1

Address offset | 0x0000 0007
Physical address | 0x0000 0007 | Instance | ADI_0_RF
Description | PA Gain and Power Control
Type | RW

Bits | Field Name | Description | Type | Reset
7:6 | GAIN | Gain control in PA 1st stage. x0: Max gain 01: Lower gain 11: Min gain | RW | 0x0
5:0 | IB | PA output power control 0x00: Min output power 0x3F: Max output power | RW | 0x00

### TOP:ADI_0_RF:PACTL2

Address offset | 0x0000 0008
Physical address | 0x0000 0008 | Instance | ADI_0_RF
Description | PA Antenna Diversity Control Control of antenna diversity and RXTXpin.
Type | RW

Bits | Field Name | Description | Type | Reset
7:5 | RXTX | Control of RFP and RFN when used to control external range extender device. (ie. If RFP is used as a single ended RF input, RFN is available to be used as a control output) 0x0: Default 0x2: RFP is low 0x3: RFP is high (1.4V) 0x6: RFN is low 0x7: RFN is high (1.4V) Other bit combinations are not valid. | RW | 0x0
4:3 | CM | Debug / experimental registers. Do not use! | RW | 0x0
2:0 | AD | When PACTL0.EN = 1: 000, 100: PA is differential 001, 101: PA is single ended and connected to RFP. 010, 110: PA is single ended and connected to RFN. When PACTL0.EN = 0: 101: RFN PA NMOS is turned on giving bias to RFP LNA when configured in external bias mode. Same functionality as RXTXpin. 110: RFP PA NMOS is turned on giving bias to RFN LNA when configured in external bias mode. Same functionality as RXTXpin. Other bit combinations are not valid. | RW | 0x0

### TOP:ADI_0_RF:RFLDO0

Address offset | 0x0000 0009
Physical address | 0x0000 0009 | Instance | ADI_0_RF
Description | RFLDO Control This register controls the LDO that supplies LNA, PA and mixer modules.
Type | RW

Bits | Field Name | Description | Type | Reset
7:6 | RESERVED6 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RW | 0x0
5 | ATEST_I_EN | Enable test current (2% of pass device current) to ATEST. 0: Disabled 1: Enabled | RW | 0
4 | ATEST_V_EN | Enables regulated output voltage to ATEST. 0: Disabled 1: Enabled | RW | 0
3 | BYPASS_REG_EN | Bypass LDO and short VDDR to PA, LNA and Mixer. RFLDO0.EN must be 0b1 to use this mode. 0: Disabled 1: Enabled | RW | 0
2 | RDY_EN | Enables generation of the LDO ready signal. Read result from STAT.RF_LDO. RFLDO0.EN must be 0b1 in order to use this feature.
Value | ENUM name | Description
0 | DIS | Disable
1 | EN | Enable
| RW | 0
1 | BIAS_DIS | Disable dummy bias current. 0: Dummy bias current on (Default) 1: Dummy bias current off
Value | ENUM name | Description
0 | EN | Enable
1 | DIS | Disable
| RW | 0
0 | EN | Enable signal for RFLDO. Powers PA, LNA and Mixer
Value | ENUM name | Description
0 | DIS | Disable
1 | EN | Enable
| RW | 0

### TOP:ADI_0_RF:RFLDO1

Address offset | 0x0000 000A
Physical address | 0x0000 000A | Instance | ADI_0_RF
Description | RFLDO Output Trim
Type | RW

Bits | Field Name | Description | Type | Reset
7 | RESERVED7 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RW | 0
6:0 | TRIM_OUT | Trims output voltage in steps of approximately 5mV linear steps. The trim is unsigned and uncentered. 0x00: ~893 mV (Minimum Output Voltage) 0x01: ~897 mV ... 0x68: ~1.40 V (Target Value) 0x3F: ~1.52 V (Maximum Value) RFLDO0.ATEST_V_EN is needed for trimming. | RW | 0x00

### TOP:ADI_0_RF:RFLDO2

Address offset | 0x0000 000B
Physical address | 0x0000 000B | Instance | ADI_0_RF
Description | RFLDO Compensation Trim
Type | RW

Bits | Field Name | Description | Type | Reset
7:6 | RESERVED6 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RW | 0x0
5:3 | COMP_RES | Trim compensation resistor in series with Miller cap in nonlinear steps. Default should be 0x1. Unsigned number. 0x0: 1066 ohms (Minimum Resistance) 0x1: 1230 ohms (Default) 0x2: 1454 ohms 0x3: 1777 ohms 0x4: 2285 ohms 0x5: 3200 ohms 0x6: 5333 ohms 0x7: 16000 ohms (Maximum Resistance) | RW | 0x0
2:0 | COMP_CAP | Trim compensation Miller cap in linear steps of 0.5 pF. Default should be 0x6. Unsigned number. 0x0: 3.5 pF (Maximum Capacitance) 0x1: 3.0 pF ... 0x6: 0.5 pF (Default) 0x7: Open Circuit / No Capacitance / No Compensation (regardless of COMP_RES setting) | RW | 0x0

### TOP:ADI_0_RF:IFADCCTL0

Address offset | 0x0000 000C
Physical address | 0x0000 000C | Instance | ADI_0_RF
Description | Intermediate Frequency ADC Trim and Configuration This register contain some of the IFADC trim and configuration settings.
Type | RW

Bits | Field Name | Description | Type | Reset
7:4 | INT2ADJ | Adjust integrator 2 gain, given by gm/C. The list below indicates the resulting gm while C is fixed (~235fF). Note MSB signifies high power (1) vs. Low power (0) mode. 0x0: 27.8 uS 0x1: 26.0 uS 0x2: 24.0 uS 0x3: 22.7 uS 0x4: 21.2 uS 0x5: 20.1 uS 0x6: 18.9 uS 0x7: 18.1 uS 0x8: 32.0 uS 0x9: 29.6 uS 0xA: 27.1 uS 0xB: 25.4 uS 0xC: 23.6 uS 0xD: 22.3 uS (Default) 0xE: 20.8 uS 0xF: 19.8 uS | RW | 0x0
3:2 | AAFCAP | Adjust AAF damping Nominal fc (Mag = -3dB) 0: 6.49 MHz 1: 5.31 MHz 2: 4.49 MHz 3: 3.59 MHz (Default) | RW | 0x0
1 | BIAS_DIS | Disable dummy bias current. 0: Dummy bias current on (Default) 1: Dummy bias current off
Value | ENUM name | Description
0 | EN | Enable (default)
1 | DIS | Disable
| RW | 0
0 | Reserved |  | RW | 0

### TOP:ADI_0_RF:IFADCLFCFG0

Address offset | 0x0000 000D
Physical address | 0x0000 000D | Instance | ADI_0_RF
Description | Intermediate Frequency ADC Trim and Configuration This register contain some of the IFADC trim settings.
Type | RW

Bits | Field Name | Description | Type | Reset
7:4 | FF1ADJ | Adjust FF1 gain (transconductance/gm from first integrator into quantizer), note MSB signifies high power (1) vs. Low power (0) mode. 0x0: 23.8 uS - Default 0x1: 22.3 uS 0x2: 20.6 uS 0x3: 19.5 us 0x4: 18.1 uS 0x5: 17.2 uS 0x6: 16.2 uS 0x7: 15.5 uS 0x8: 27.2 uS 0x9: 25.2 uS 0xA: 23.1 uS 0xB: 21.6 uS 0xC: 20.0 uS 0xD: 18.9 uS 0xE: 17.7 uS 0xF: 16.8 uS | RW | 0x0
3:0 | INT3ADJ | Adjust integrator 3 gain, see IFADCCTL0.INT2ADJ for valid trim values Default value, 0x6 | RW | 0x0

### TOP:ADI_0_RF:IFADCLFCFG1

Address offset | 0x0000 000E
Physical address | 0x0000 000E | Instance | ADI_0_RF
Description | Intermediate Frequency ADC Trim and Configuration This register contain some of the IFADC trim settings.
Type | RW

Bits | Field Name | Description | Type | Reset
7:4 | FF3ADJ | Adjust FF3 gain (transconductance/gm from third integrator into quantizer). See IFADCLFCFG0.FF1ADJ for values. Default value is 0x4 | RW | 0x0
3:0 | FF2ADJ | Adjust FF2 gain (transconductance/gm from second integrator into quantizer). See IFADCLFCFG0.FF1ADJ for values. Default value is 0x3 | RW | 0x0

### TOP:ADI_0_RF:IFADCDAC

Address offset | 0x0000 000F
Physical address | 0x0000 000F | Instance | ADI_0_RF
Description | Intermediate Frequency ADC Ttrim and Configuration This register contain some of the IFADC trim and configuration settings.
Type | RW

Bits | Field Name | Description | Type | Reset
7 | MODE | Selects DAC return to zero mode
Value | ENUM name | Description
0 | NRTZ | NRTZ enabled. Default
1 | RTZ | RTZ enabled
| RW | 0
6:1 | TRIM | Trim feedback-DAC current in uA. Increasing this current will give a more aggressive noise shaping but it also reduce the gain into the IFADC. 0x00: 0.00 uA 0x01: 0.83 uA 0x02: 1.66 uA 0x03: 2.50 uA 0x04: 3.33 uA 0x05: 4.17 uA 0x06: 5.00 uA 0x07: 5.83 uA 0x08: 6.67 uA 0x09: 7.50 uA 0x0A: 8.33 uA 0x0B: 9.17 uA 0x0C: 10.00 uA 0x0D: 10.83 uA - Default 0x0E: 11.67 uA 0x0F: 12.50 uA 0x10: 13.33 uA 0x11: 14.17 uA 0x12: 15.00 uA 0x13: 15.83 uA 0x14: 16.67 uA 0x15: 17.50 uA 0x16: 18.33 uA 0x17: 19.17 uA 0x18: 20.00 uA 0x19: 20.83 uA 0x1A: 21.67 uA 0x1B: 22.50 uA 0x1C: 23.33 uA 0x1D: 24.17 uA 0x1E: 25.00 uA 0x1F: 25.83 uA Note that bit 6 is not used | RW | 0x00
0 | RESERVED0 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RW | 0

### TOP:ADI_0_RF:IFADCQUANT0

Address offset | 0x0000 0010
Physical address | 0x0000 0010 | Instance | ADI_0_RF
Description | IFADC Quantizer Trim and Control This register controls trim values and calibration of the IFADC quantizers.
Type | RW

Bits | Field Name | Description | Type | Reset
7:6 | Reserved | Internal | RW | 0x0
5:4 | Reserved | Internal | RW | 0x0
3 | AUTOCAL_EN | Quantizer auto calibrate enable. Before this sequence is initiated the IFADCs to be used must be enabled with IFADCCTL1.ADCIEN and/or IFADCCTL1.ADCQEN. Then reset digital sub-blocks with IFADCCTL2.RESETN before the auto calibrate is enabled. | RW | 0
2:0 | TH | Threshold adjust for quantizer. NOM is ~25mV. 0: Single threshold 1: NOM * 1/4 2: NOM * 2/4 3: NOM * 3/4 4: NOM 5: NOM * 5/4 - Default 6: NOM * 6/4 7: NOM * 7/4 | RW | 0x0

### TOP:ADI_0_RF:IFADCCTL1

Address offset | 0x0000 0012
Physical address | 0x0000 0012 | Instance | ADI_0_RF
Description | Intermediate Frequency ADC Trim and Configuration This register contain some of the IFADC trim and configuration settings.
Type | RW

Bits | Field Name | Description | Type | Reset
7:5 | DITHERTRIM | Adjust dither output current 0: 250.0 nA (Default) 1: 500.0 nA 2: 749.8 nA 3: 999.7 nA 4: 1249 nA 5: 1499 nA 6: 1749 nA 7: 1999 nA | RW | 0x0
4 | ADCIEN | Enable I-channel IFADC
Value | ENUM name | Description
0 | DIS | Disable
1 | EN | Enable
| RW | 0
3 | ADCQEN | Enable Q-channel IFADC
Value | ENUM name | Description
0 | DIS | Disable
1 | EN | Enable
| RW | 0
2:1 | DITHEREN | Dither algorithm select. This register is also used for integrity check of IFADC output test modes (IFADCCTL2.ADCLFSROUTEN=1). IFADC output bits in test mode is combined as following: IFADC output Q[1:0] = 10 (static) and IFADC output I[1:0] is configured according to the list below (the right side is the resulting IFADC output): 0: 00 1: PRBS2d 0 2: 0 PRBS2 3: PRBS2d PRBS2
Value | ENUM name | Description
0x0 | DIS | Disable dither (Default)
0x1 | ENS | Single pseudo random sequence, white dither
0x2 | ENSD | White noise dither, double power (same sequence on both outputs)
0x3 | ENG | Gaussian dither, two different pseudo random sequences combined
| RW | 0x0
0 | Reserved |  | RW | 0

### TOP:ADI_0_RF:IFADCCTL2

Address offset | 0x0000 0013
Physical address | 0x0000 0013 | Instance | ADI_0_RF
Description | Intermediate Frequency ADC Configuration This register contain some of the IFADC configuration settings.
Type | RW

Bits | Field Name | Description | Type | Reset
7 | RESETN | Reset all digital blocks (active low). Must be done after the IFADC has been enabled to reset digital sub-IP. First enable the IFADC withIFADCCTL1.ADCIEN and/or IFADCCTL1.ADCQEN. Then reset the device by pulling the signal low for at least one clock cycle, then back high.
Value | ENUM name | Description
0 | EN | Disable
1 | DIS | Enable (default)
| RW | 0
6 | CLKGENEN | Enable clock generator module
Value | ENUM name | Description
0 | DIS | Disable
1 | EN | Enable (default)
| RW | 0
5 | ADCDIGCLKEN | Enable clock output from IFADC to decimator
Value | ENUM name | Description
0 | DIS | Disable
1 | EN | Enable (default)
| RW | 0
4 | Reserved | Internal | RW | 0
3:2 | RESERVED2 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RW | 0x0
1 | INVCLKOUT | Control phase inversion of IFADC clock output
Value | ENUM name | Description
0 | DIS | Keep default IFADC output clock phase
1 | EN | Invert IFADC output clock phase (default)
| RW | 0
0 | Reserved |  | RW | 0

### TOP:ADI_0_RF:IFALDO1

Address offset | 0x0000 0018
Physical address | 0x0000 0018 | Instance | ADI_0_RF
Description | IFADC Analog Supply LDO
Type | RW

Bits | Field Name | Description | Type | Reset
7:5 | RESERVED5 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RW | 0x0
4 | ERR_AMP_ZERO_EN | Enables a zero in the LDO error amplifier's output to improve stability at the cost of bandwidth. 0: Disabled (Default) 1: Enabled
Value | ENUM name | Description
0 | DIS | Disable
1 | EN | Enable
| RW | 0
3 | BYPASS_REG_EN | Bypass LDO and short VDDR on LDO output to IFADC. 0: Disabled (Default) 1: Enabled (IFALDO1.EN must be enabled) | RW | 0
2 | RDY_EN | Enable LDO Ready Signal. Read result in STAT.IFLDOS_RDY. 0: Disable ready signal generation circuit 1: Enable ready signal generation circuit (IFALDO1.EN must be enabled) (Default)
Value | ENUM name | Description
0 | DIS | Disable
1 | EN | Enable
| RW | 0
1 | BIAS_DIS | Disable dummy bias current. 0: Dummy bias current on (Default) 1: Dummy bias current off
Value | ENUM name | Description
0 | EN | Enable
1 | DIS | Disable
| RW | 0
0 | EN | Enable IFADC's regulator for analog blocks.
Value | ENUM name | Description
0 | DIS | Disable
1 | EN | Enable (Default)
| RW | 0

### TOP:ADI_0_RF:IFALDO2

Address offset | 0x0000 0019
Physical address | 0x0000 0019 | Instance | ADI_0_RF
Description | IFADC Analog Supply LDO
Type | RW

Bits | Field Name | Description | Type | Reset
7:5 | COMP_CAP | Trim compensation Miller cap in linear steps of 0.5 pF. Default should be 0x6. Unsigned. Tradeoff stability for speed. 0x0: 3.5 pF (Maximum Capacitance) 0x1: 3.0 pF ... 0x6: 0.5 pF (Default) 0x7: Open Circuit / No Capacitance / No Compensation (regardless of IFALDO3.COMP_RES setting) | RW | 0x0
4:0 | TRIM_OUT | Trim LDO's output voltage linearly with a signed 2's complement number. Step size is approximately 8 mV. 0x10: -16 : 1.324V (Minimum Voltage) ... 0x1F: -1 : 1.395V 0x00: +0 : 1.403V (Default) 0x01: +1 : 1.407V ... 0x0F:+15 : 1.474V (Maximum Voltage) | RW | 0x00

### TOP:ADI_0_RF:IFALDO3

Address offset | 0x0000 001A
Physical address | 0x0000 001A | Instance | ADI_0_RF
Description | IFADC Analog Supply LDO
Type | RW

Bits | Field Name | Description | Type | Reset
7:5 | RESERVED5 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RW | 0x0
4 | ATEST_V_EN | Enables regulated output voltage to ATEST. Used to trim the LDO. 0: Disabled 1: Enabled | RW | 0
3 | ATEST_I_EN | Enable test current (8.33% or 1/12 of LDO load current) to ATEST. 0: Disabled 1: Enabled | RW | 0
2:0 | COMP_RES | Trim compensation resistor in series with Miller cap in nonlinear steps. Default should be 0x0. Unsigned number. 0x0: 1066 ohms (Minimum Resistance, Default) 0x1: 1230 ohms 0x2: 1454 ohms 0x3: 1777 ohms 0x4: 2285 ohms 0x5: 3200 ohms 0x6: 5333 ohms 0x7: 16000 ohms (Maximum Resistance) | RW | 0x0

### TOP:ADI_0_RF:IFDLDO1

Address offset | 0x0000 001B
Physical address | 0x0000 001B | Instance | ADI_0_RF
Description | IFADC Digital Supply LDO
Type | RW

Bits | Field Name | Description | Type | Reset
7:4 | RESERVED4 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RW | 0x0
3 | BYPASS_REG_EN | Bypass LDO and short VDDR to LDO's output to ADC. 0: Disabled (Default) 1: Enabled
Value | ENUM name | Description
0 | DIS | Disable
1 | EN | Enable
| RW | 0
2 | RDY_EN | Enable LDO Ready Signal. Read result in STAT.IFLDOS_RDY. 0: Disable ready signal generation circuit 1: Enable ready signal generation circuit (IFDIGLDO_EN must be enabled) (Default)
Value | ENUM name | Description
0 | DIS | Disable
1 | EN | Enable
| RW | 0
1 | BIAS_DIS | Disable dummy bias current. 0: Dummy bias current on (Default) 1: Dummy bias current off
Value | ENUM name | Description
0 | EN | Enable
1 | DIS | Disable
| RW | 0
0 | EN | Enable IFADC LDO for digital blocks.
Value | ENUM name | Description
0 | DIS | Disable
1 | EN | Enable
| RW | 0

### TOP:ADI_0_RF:IFDLDO2

Address offset | 0x0000 001C
Physical address | 0x0000 001C | Instance | ADI_0_RF
Description | IFADC Digital Supply LDO
Type | RW

Bits | Field Name | Description | Type | Reset
7:5 | COMP_CAP | Trim compensation Miller cap in linear steps of 0.5 pF. Default should be 0x6. Unsigned. 0x0: 3.5 pF (Maximum Capacitance) 0x1: 3.0 pF ... 0x6: 0.5 pF (Default) 0x7: Open Circuit / No Capacitance / No Compensation (regardless of IFDLDO3.COMP_RES setting) | RW | 0x0
4:0 | TRIM_OUT | Trim LDO's output voltage linearly with a signed 2's complement number. Step size is approximately 8 mV. 0x10: -16 : 1.128V (Minimum Voltage) ... 0x1F: -1 : 1.198V 0x00: +0 : 1.206V (Default) 0x01: +1 : 1.210V ... 0x0F:+15 : 1.277V (Maximum Voltage) | RW | 0x00

### TOP:ADI_0_RF:IFDLDO3

Address offset | 0x0000 001D
Physical address | 0x0000 001D | Instance | ADI_0_RF
Description | IFADC Digital **Supply LDO**
Type | RW

Bits | Field Name | Description | Type | Reset
7:5 | RESERVED5 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RW | 0x0
4 | ATEST_V_EN | Enables regulated output voltage to ATEST. Used to trim the LDO. 0: Disabled 1: Enabled
Value | ENUM name | Description
0 | DIS | Disable
1 | EN | Enable
| RW | 0
3 | ATEST_I_EN | Enable test current (10% of LDO load current) to ATEST. 0: Disabled 1: Enabled
Value | ENUM name | Description
0 | DIS | Disable
1 | EN | Enable
| RW | 0
2:0 | COMP_RES | Trim compensation resistor in series with Miller cap in nonlinear steps. Default should be 0x0. Unsigned number. 0x0: 1066 ohms (Minimum Resistance, Default) 0x1: 1230 ohms 0x2: 1454 ohms 0x3: 1777 ohms 0x4: 2285 ohms 0x5: 3200 ohms 0x6: 5333 ohms 0x7: 16000 ohms (Maximum Resistance) | RW | 0x0

### TOP:ADI_0_RF:IFAMPCTL3

Address offset | 0x0000 001E
Physical address | 0x0000 001E | Instance | ADI_0_RF
Description | IFAMP Bias Current Control
Type | RW

Bits | Field Name | Description | Type | Reset
7 | RESERVED7 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RW | 0
6:4 | AAF_CAP_EN | AAF capacitor control. Linear cap steps (ie. Non-linear BW steps) 0x0: Smallest cap, largest BW 0x7: Largest cap, narrowest BW | RW | 0x0
3:0 | IB | IFAMP bias current control. Linear steps. 0x0: Min bias current 0x7: Default bias current 0xF: Max bias current | RW | 0x0

### TOP:ADI_0_RF:STAT

Address offset | 0x0000 001F
Physical address | 0x0000 001F | Instance | ADI_0_RF
Description | Status LDO and Calibration Status
Type | RO

Bits | Field Name | Description | Type | Reset
7:3 | IFADC_CALVAL_OUT | Quant Cal values from either I or Q quantizer Use: IFADCTEST.QCALDBCSEL to select comparator, IFADCTEST.QCALDBIQSEL to select I/Q, and IFADCQUANT1.DBG_CAL_LEGSEL to select leg | RO | 0x00
2 | IFADC_CALDONE | IFADC quantizer calibration done | RO | 0
1 | IFLDOS_RDY | IFADC LDOs Ready (if only one is enabled the bit indicate the status of the enabled LDO) | RO | 0
0 | RF_LDO | RF LDO Ready | RO | 0