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udma.h
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1 /******************************************************************************
2 * Filename: udma.h
3 * Revised: 2015-01-14 12:12:44 +0100 (on, 14 jan 2015)
4 * Revision: 42373
5 *
6 * Description: Defines and prototypes for the uDMA controller.
7 *
8 * Copyright (c) 2015, Texas Instruments Incorporated
9 * All rights reserved.
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions are met:
13 *
14 * 1) Redistributions of source code must retain the above copyright notice,
15 * this list of conditions and the following disclaimer.
16 *
17 * 2) Redistributions in binary form must reproduce the above copyright notice,
18 * this list of conditions and the following disclaimer in the documentation
19 * and/or other materials provided with the distribution.
20 *
21 * 3) Neither the name of the ORGANIZATION nor the names of its contributors may
22 * be used to endorse or promote products derived from this software without
23 * specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
26 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
28 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
29 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
35 * POSSIBILITY OF SUCH DAMAGE.
36 *
37 ******************************************************************************/
38
39 //*****************************************************************************
40 //
43 //
44 //*****************************************************************************
45
46 #ifndef __UDMA_H__
47 #define __UDMA_H__
48
49 //*****************************************************************************
50 //
51 // If building with a C++ compiler, make all of the definitions in this header
52 // have a C binding.
53 //
54 //*****************************************************************************
55 #ifdef __cplusplus
56 extern "C"
57 {
58 #endif
59
60 #include <stdbool.h>
61 #include <stdint.h>
62 #include <inc/hw_types.h>
63 #include <inc/hw_ints.h>
64 #include <inc/hw_memmap.h>
65 #include <inc/hw_udma.h>
66 #include <driverlib/debug.h>
67 #include <driverlib/interrupt.h>
68
69 //*****************************************************************************
70 //
71 // Support for DriverLib in ROM:
72 // This section renames all functions that are not "static inline", so that
73 // calling these functions will default to implementation in flash. At the end
74 // of this file a second renaming will change the defaults to implementation in
75 // ROM for available functions.
76 //
77 // To force use of the implementation in flash, e.g. for debugging:
78 // - Globally: Define DRIVERLIB_NOROM at project level
79 // - Per function: Use prefix "NOROM_" when calling the function
80 //
81 // Do not define DRIVERLIB_GENERATE_ROM!
82 //
83 //*****************************************************************************
84 #ifndef DRIVERLIB_GENERATE_ROM
85 #define uDMAChannelAttributeEnable NOROM_uDMAChannelAttributeEnable
86 #define uDMAChannelAttributeDisable NOROM_uDMAChannelAttributeDisable
87 #define uDMAChannelAttributeGet NOROM_uDMAChannelAttributeGet
88 #define uDMAChannelControlSet NOROM_uDMAChannelControlSet
89 #define uDMAChannelTransferSet NOROM_uDMAChannelTransferSet
90 #define uDMAChannelScatterGatherSet NOROM_uDMAChannelScatterGatherSet
91 #define uDMAChannelSizeGet NOROM_uDMAChannelSizeGet
92 #define uDMAChannelModeGet NOROM_uDMAChannelModeGet
93 #endif
94
95 //*****************************************************************************
96 //
101 //
102 //*****************************************************************************
103 typedef struct
104 {
105 volatile void *pvSrcEndAddr;
106 volatile void *pvDstEndAddr;
107 volatile uint32_t ui32Control;
108 volatile uint32_t ui32Spare;
109 }
110 tDMAControlTable;
111
112 //*****************************************************************************
113 //
127
139 //
179 //*****************************************************************************
180 #define uDMATaskStructEntry(ui32TransferCount, \
181 ui32ItemSize, \
182 ui32SrcIncrement, \
183 pvSrcAddr, \
184 ui32DstIncrement, \
185 pvDstAddr, \
186 ui32ArbSize, \
187 ui32Mode) \
188 { \
189 (((ui32SrcIncrement) == UDMA_SRC_INC_NONE) ? (pvSrcAddr) : \
190 ((void *)(&((uint8_t *)(pvSrcAddr))[((ui32TransferCount) << \
191 ((ui32SrcIncrement) >> 26)) - 1]))), \
192 (((ui32DstIncrement) == UDMA_DST_INC_NONE) ? (pvDstAddr) : \
193 ((void *)(&((uint8_t *)(pvDstAddr))[((ui32TransferCount) << \
194 ((ui32DstIncrement) >> 30)) - 1]))), \
195 (ui32SrcIncrement) | (ui32DstIncrement) | (ui32ItemSize) | \
196 (ui32ArbSize) | (((ui32TransferCount) - 1) << 4) | \
197 ((((ui32Mode) == UDMA_MODE_MEM_SCATTER_GATHER) || \
198 ((ui32Mode) == UDMA_MODE_PER_SCATTER_GATHER)) ? \
199 (ui32Mode) | UDMA_MODE_ALT_SELECT : (ui32Mode)), 0 \
200 }
201
202 //*****************************************************************************
203 //
204 // The hardware configured number of uDMA channels.
205 //
206 //*****************************************************************************
207 #define UDMA_NUM_CHANNELS 21
208
209 //*****************************************************************************
210 //
211 // The level of priority for the uDMA channels
212 //
213 //*****************************************************************************
214 #define UDMA_PRIORITY_LOW 0x00000000
215 #define UDMA_PRIORITY_HIGH 0x00000001
216
217 //*****************************************************************************
218 //
219 // Flags that can be passed to uDMAChannelAttributeEnable(),
220 // uDMAChannelAttributeDisable(), and returned from uDMAChannelAttributeGet().
221 //
222 //*****************************************************************************
223 #define UDMA_ATTR_USEBURST 0x00000001
224 #define UDMA_ATTR_ALTSELECT 0x00000002
225 #define UDMA_ATTR_HIGH_PRIORITY 0x00000004
226 #define UDMA_ATTR_REQMASK 0x00000008
227 #define UDMA_ATTR_ALL 0x0000000F
228
229 //*****************************************************************************
230 //
231 // DMA control modes that can be passed to uDMAChannelModeSet() and returned
232 // uDMAChannelModeGet().
233 //
234 //*****************************************************************************
235 #define UDMA_MODE_STOP 0x00000000
236 #define UDMA_MODE_BASIC 0x00000001
237 #define UDMA_MODE_AUTO 0x00000002
238 #define UDMA_MODE_PINGPONG 0x00000003
239 #define UDMA_MODE_MEM_SCATTER_GATHER \
240 0x00000004
241 #define UDMA_MODE_PER_SCATTER_GATHER \
242 0x00000006
243 #define UDMA_MODE_M 0x00000007 // uDMA Transfer Mode
244 #define UDMA_MODE_ALT_SELECT 0x00000001
245
246 //*****************************************************************************
247 //
248 // Channel configuration values that can be passed to uDMAControlSet().
249 //
250 //*****************************************************************************
251 #define UDMA_DST_INC_8 0x00000000
252 #define UDMA_DST_INC_16 0x40000000
253 #define UDMA_DST_INC_32 0x80000000
254 #define UDMA_DST_INC_NONE 0xC0000000
255 #define UDMA_DST_INC_M 0xC0000000 // Destination Address Increment
256 #define UDMA_DST_INC_S 30
257 #define UDMA_SRC_INC_8 0x00000000
258 #define UDMA_SRC_INC_16 0x04000000
259 #define UDMA_SRC_INC_32 0x08000000
260 #define UDMA_SRC_INC_NONE 0x0c000000
261 #define UDMA_SRC_INC_M 0x0C000000 // Source Address Increment
262 #define UDMA_SRC_INC_S 26
263 #define UDMA_SIZE_8 0x00000000
264 #define UDMA_SIZE_16 0x11000000
265 #define UDMA_SIZE_32 0x22000000
266 #define UDMA_SIZE_M 0x33000000 // Data Size
267 #define UDMA_SIZE_S 24
268 #define UDMA_ARB_1 0x00000000
269 #define UDMA_ARB_2 0x00004000
270 #define UDMA_ARB_4 0x00008000
271 #define UDMA_ARB_8 0x0000c000
272 #define UDMA_ARB_16 0x00010000
273 #define UDMA_ARB_32 0x00014000
274 #define UDMA_ARB_64 0x00018000
275 #define UDMA_ARB_128 0x0001c000
276 #define UDMA_ARB_256 0x00020000
277 #define UDMA_ARB_512 0x00024000
278 #define UDMA_ARB_1024 0x00028000
279 #define UDMA_ARB_M 0x0003C000 // Arbitration Size
280 #define UDMA_ARB_S 14
281 #define UDMA_NEXT_USEBURST 0x00000008
282 #define UDMA_XFER_SIZE_MAX 1024
283 #define UDMA_XFER_SIZE_M 0x00003FF0 // Transfer size
284 #define UDMA_XFER_SIZE_S 4
285
286 //*****************************************************************************
287 //
288 // Channel numbers to be passed to API functions that require a channel number
289 // ID.
290 //
291 //*****************************************************************************
292 #define UDMA_CHAN_SW_EVT0 0 // Software Event Channel 0
293 #define UDMA_CHAN_UART0_RX 1 // UART0 RX Data
294 #define UDMA_CHAN_UART0_TX 2 // UART0 RX Data
295 #define UDMA_CHAN_SSI0_RX 3 // SSI0 RX Data
296 #define UDMA_CHAN_SSI0_TX 4 // SSI0 RX Data
297 #define UDMA_CHAN_SPIS_RX 5 // SPIS RX Data
298 #define UDMA_CHAN_SPIS_TX 6 // SPIS RX Data
299 #define UDMA_CHAN_AUX_ADC 7 // AUX ADC event
300 #define UDMA_CHAN_AUX_SW 8 // AUX Software event
301 #define UDMA_CHAN_TIMER0_A 9 // Timer0 A event
302 #define UDMA_CHAN_TIMER0_B 10 // Timer0 B event
303 #define UDMA_CHAN_TIMER1_A 11
304 #define UDMA_CHAN_TIMER1_B 12
305 #define UDMA_CHAN_AON_PROG2 13
306 #define UDMA_CHAN_DMA_PROG 14
307 #define UDMA_CHAN_AON_RTC 15
308 #define UDMA_CHAN_SSI1_RX 16
309 #define UDMA_CHAN_SSI1_TX 17
310 #define UDMA_CHAN_SW_EVT1 18
311 #define UDMA_CHAN_SW_EVT2 19
312 #define UDMA_CHAN_SW_EVT3 20
313
314 //*****************************************************************************
315 //
316 // Flags to be OR'd with the channel ID to indicate if the primary or alternate
317 // control structure should be used.
318 //
319 //*****************************************************************************
320 #define UDMA_PRI_SELECT 0x00000000
321 #define UDMA_ALT_SELECT 0x00000020
322
323 //*****************************************************************************
324 //
325 // API Functions and prototypes
326 //
327 //*****************************************************************************
328
329 #ifdef DRIVERLIB_DEBUG
330 //*****************************************************************************
331 //
342 //
343 //*****************************************************************************
344 static bool
345 uDMABaseValid(uint32_t ui32Base)
346 {
347 return(ui32Base == UDMA0_BASE);
348 }
349 #endif
350
351 //*****************************************************************************
352 //
361 //
362 //*****************************************************************************
363 __STATIC_INLINE void
364 uDMAEnable(uint32_t ui32Base)
365 {
366 //
367 // Check the arguments.
368 //
369 ASSERT(uDMABaseValid(ui32Base));
370
371 //
372 // Set the master enable bit in the config register.
373 //
374 HWREG(ui32Base + UDMA_O_CFG) = UDMA_CFG_MASTERENABLE;
375 }
376
377 //*****************************************************************************
378 //
387 //
388 //*****************************************************************************
389 __STATIC_INLINE void
390 uDMADisable(uint32_t ui32Base)
391 {
392 //
393 // Check the arguments.
394 //
395 ASSERT(uDMABaseValid(ui32Base));
396
397 //
398 // Clear the master enable bit in the config register.
399 //
400 HWREG(ui32Base + UDMA_O_CFG) = 0;
401 }
402
403 //*****************************************************************************
404 //
414 //
415 //*****************************************************************************
416 __STATIC_INLINE uint32_t
417 uDMAErrorStatusGet(uint32_t ui32Base)
418 {
419 //
420 // Check the arguments.
421 //
422 ASSERT(uDMABaseValid(ui32Base));
423
424 //
425 // Return the uDMA error status.
426 //
427 return(HWREG(ui32Base + UDMA_O_ERROR));
428 }
429
430 //*****************************************************************************
431 //
440 //
441 //*****************************************************************************
442 __STATIC_INLINE void
443 uDMAErrorStatusClear(uint32_t ui32Base)
444 {
445 //
446 // Check the arguments.
447 //
448 ASSERT(uDMABaseValid(ui32Base));
449
450 //
451 // Clear the uDMA error interrupt.
452 //
453 HWREG(ui32Base + UDMA_O_ERROR) = UDMA_ERROR_STATUS;
454 }
455
456 //*****************************************************************************
457 //
472 //
473 //*****************************************************************************
474 __STATIC_INLINE void
475 uDMAChannelEnable(uint32_t ui32Base, uint32_t ui32ChannelNum)
476 {
477 //
478 // Check the arguments.
479 //
480 ASSERT(uDMABaseValid(ui32Base));
481 ASSERT(ui32ChannelNum < UDMA_NUM_CHANNELS);
482
483 //
484 // Set the bit for this channel in the enable set register.
485 //
486 HWREG(ui32Base + UDMA_O_SETCHANNELEN) = 1 << ui32ChannelNum;
487 }
488
489 //*****************************************************************************
490 //
501 //
502 //*****************************************************************************
503 __STATIC_INLINE void
504 uDMAChannelDisable(uint32_t ui32Base, uint32_t ui32ChannelNum)
505 {
506 //
507 // Check the arguments.
508 //
509 ASSERT(uDMABaseValid(ui32Base));
510 ASSERT(ui32ChannelNum < UDMA_NUM_CHANNELS);
511
512 //
513 // Set the bit for this channel in the enable clear register.
514 //
515 HWREG(ui32Base + UDMA_O_CLEARCHANNELEN) = 1 << ui32ChannelNum;
516 }
517
518 //*****************************************************************************
519 //
532 //
533 //*****************************************************************************
534 __STATIC_INLINE bool
535 uDMAChannelIsEnabled(uint32_t ui32Base, uint32_t ui32ChannelNum)
536 {
537 //
538 // Check the arguments.
539 //
540 ASSERT(uDMABaseValid(ui32Base));
541 ASSERT(ui32ChannelNum < UDMA_NUM_CHANNELS);
542
543 //
544 // AND the specified channel bit with the enable register, and return the
545 // result.
546 //
547 return((HWREG(ui32Base + UDMA_O_SETCHANNELEN) & (1 << ui32ChannelNum)) ?
548 true : false);
549 }
550
551 //*****************************************************************************
552 //
577 //
578 //*****************************************************************************
579 __STATIC_INLINE void
580 uDMAControlBaseSet(uint32_t ui32Base, void *pControlTable)
581 {
582 //
583 // Check the arguments.
584 //
585 ASSERT(uDMABaseValid(ui32Base));
586 ASSERT(((uint32_t)pControlTable & ~0x3FF) ==
587 (uint32_t)pControlTable);
588 ASSERT((uint32_t)pControlTable >= SRAM_BASE);
589
590 //
591 // Program the base address into the register.
592 //
593 HWREG(ui32Base + UDMA_O_CTRL) = (uint32_t)pControlTable;
594 }
595
596 //*****************************************************************************
597 //
607 //
608 //*****************************************************************************
609 __STATIC_INLINE void *
610 uDMAControlBaseGet(uint32_t ui32Base)
611 {
612 //
613 // Check the arguments.
614 //
615
616 ASSERT(uDMABaseValid(ui32Base));
617 //
618 // Read the current value of the control base register, and return it to
619 // the caller.
620 //
621 return((void *)HWREG(ui32Base + UDMA_O_CTRL));
622 }
623
624 //*****************************************************************************
625 //
635 //
636 //*****************************************************************************
637 __STATIC_INLINE void *
638 uDMAControlAlternateBaseGet(uint32_t ui32Base)
639 {
640 //
641 // Check the arguments.
642 //
643 ASSERT(uDMABaseValid(ui32Base));
644
645 //
646 // Read the current value of the control base register, and return it to
647 // the caller.
648 //
649 return((void *)HWREG(ui32Base + UDMA_O_ALTCTRL));
650 }
651
652 //*****************************************************************************
653 //
671 //
672 //*****************************************************************************
673 __STATIC_INLINE void
674 uDMAChannelRequest(uint32_t ui32Base, uint32_t ui32ChannelNum)
675 {
676 //
677 // Check the arguments.
678 //
679 ASSERT(uDMABaseValid(ui32Base));
680 ASSERT(ui32ChannelNum < UDMA_NUM_CHANNELS);
681
682 //
683 // Set the bit for this channel in the software uDMA request register.
684 //
685 HWREG(ui32Base + UDMA_O_SOFTREQ) = 1 << ui32ChannelNum;
686 }
687
688 //*****************************************************************************
689 //
706 //
707 //*****************************************************************************
708 extern void uDMAChannelAttributeEnable(uint32_t ui32Base,
709 uint32_t ui32ChannelNum,
710 uint32_t ui32Attr);
711
712 //*****************************************************************************
713 //
730 //
731 //*****************************************************************************
732 extern void uDMAChannelAttributeDisable(uint32_t ui32Base,
733 uint32_t ui32ChannelNum,
734 uint32_t ui32Attr);
735
736 //*****************************************************************************
737 //
754 //
755 //*****************************************************************************
756 extern uint32_t uDMAChannelAttributeGet(uint32_t ui32Base,
757 uint32_t ui32ChannelNum);
758
759 //*****************************************************************************
760 //
799 //
800 //*****************************************************************************
801 extern void uDMAChannelControlSet(uint32_t ui32Base,
802 uint32_t ui32ChannelStructIndex,
803 uint32_t ui32Control);
804
805 //*****************************************************************************
806 //
863 //
864 //*****************************************************************************
865 extern void uDMAChannelTransferSet(uint32_t ui32Base,
866 uint32_t ui32ChannelStructIndex,
867 uint32_t ui32Mode, void *pvSrcAddr,
868 void *pvDstAddr, uint32_t ui32TransferSize);
869
870 //*****************************************************************************
871 //
896 //
897 //*****************************************************************************
898 extern void uDMAChannelScatterGatherSet(uint32_t ui32Base,
899 uint32_t ui32ChannelNum,
900 uint32_t ui32TaskCount,
901 void *pvTaskList,
902 uint32_t ui32IsPeriphSG);
903
904 //*****************************************************************************
905 //
920 //
921 //*****************************************************************************
922 extern uint32_t uDMAChannelSizeGet(uint32_t ui32Base,
923 uint32_t ui32ChannelStructIndex);
924
925 //*****************************************************************************
926 //
946 //
947 //*****************************************************************************
948 extern uint32_t uDMAChannelModeGet(uint32_t ui32Base,
949 uint32_t ui32ChannelStructIndex);
950
951 //*****************************************************************************
952 //
976 //
977 //*****************************************************************************
978 __STATIC_INLINE void
979 uDMAIntRegister(uint32_t ui32Base, uint32_t ui32IntChannel,
980 void (*pfnHandler)(void))
981 {
982 //
983 // Check the arguments.
984 //
985 ASSERT(uDMABaseValid(ui32Base));
986 ASSERT(pfnHandler);
987 ASSERT((ui32IntChannel == INT_UDMA) || (ui32IntChannel == INT_UDMAERR));
988
989 //
990 // Register the interrupt handler.
991 //
992 IntRegister(ui32IntChannel, pfnHandler);
993
994 //
995 // Enable the memory management fault.
996 //
997 IntEnable(ui32IntChannel);
998 }
999
1000 //*****************************************************************************
1001 //
1018 //
1019 //*****************************************************************************
1020 __STATIC_INLINE void
1021 uDMAIntUnregister(uint32_t ui32Base, uint32_t ui32IntChannel)
1022 {
1023 //
1024 // Check the arguments.
1025 //
1026 ASSERT(uDMABaseValid(ui32Base));
1027 ASSERT((ui32IntChannel == INT_UDMA) || (ui32IntChannel == INT_UDMAERR));
1028
1029 //
1030 // Disable the interrupt.
1031 //
1032 IntDisable(ui32IntChannel);
1033
1034 //
1035 // Unregister the interrupt handler.
1036 //
1037 IntUnregister(ui32IntChannel);
1038 }
1039
1040 //*****************************************************************************
1041 //
1053 //
1054 //*****************************************************************************
1055 __STATIC_INLINE void
1056 uDMAIntClear(uint32_t ui32Base, uint32_t ui32ChanMask)
1057 {
1058 //
1059 // Check the arguments.
1060 //
1061 ASSERT(uDMABaseValid(ui32Base));
1062
1063 //
1064 // Clear the requested bits in the uDMA interrupt status register.
1065 //
1066 HWREG(ui32Base + UDMA_O_REQDONE) = ui32ChanMask;
1067 }
1068
1069 //*****************************************************************************
1070 //
1080 //
1081 //*****************************************************************************
1082 __STATIC_INLINE uint32_t
1083 uDMAIntStatus(uint32_t ui32Base)
1084 {
1085 //
1086 // Check the arguments.
1087 //
1088 ASSERT(uDMABaseValid(ui32Base));
1089
1090 //
1091 // Return the uDMA interrupt status register.
1092 //
1093 return (HWREG(ui32Base + UDMA_O_REQDONE));
1094 }
1095
1096 //*****************************************************************************
1097 //
1112 //
1113 //*****************************************************************************
1114 __STATIC_INLINE void
1115 uDMAIntSwEventEnable(uint32_t ui32Base, uint32_t ui32IntChannel)
1116 {
1117 //
1118 // Check the arguments.
1119 //
1120 ASSERT(uDMABaseValid(ui32Base));
1121 ASSERT(ui32IntChannel < UDMA_NUM_CHANNELS);
1122
1123 //
1124 // Enable the channel.
1125 //
1126 HWREG(ui32Base + UDMA_O_DONEMASK) |= 1 << ui32IntChannel;
1127 }
1128
1129 //*****************************************************************************
1130 //
1143 //
1144 //*****************************************************************************
1145 __STATIC_INLINE void
1146 uDMAIntSwEventDisable(uint32_t ui32Base, uint32_t ui32IntChannel)
1147 {
1148 //
1149 // Check the arguments.
1150 //
1151 ASSERT(uDMABaseValid(ui32Base));
1152 ASSERT(ui32IntChannel < UDMA_NUM_CHANNELS);
1153
1154 //
1155 // Disable the SW channel.
1156 //
1157 HWREG(ui32Base + UDMA_O_DONEMASK) &= ~(1 << ui32IntChannel);
1158 }
1159
1160 //*****************************************************************************
1161 //
1169 //
1170 //*****************************************************************************
1171 __STATIC_INLINE uint32_t
1172 uDMAGetStatus(uint32_t ui32Base)
1173 {
1174 //
1175 // Check the arguments.
1176 //
1177 ASSERT(uDMABaseValid(ui32Base));
1178
1179 //
1180 // Read and return the status register.
1181 //
1182 return HWREG(ui32Base + UDMA_O_STATUS);
1183 }
1184
1185 //*****************************************************************************
1186 //
1196 //
1197 //*****************************************************************************
1198 __STATIC_INLINE void
1199 uDMAChannelPrioritySet(uint32_t ui32Base, uint32_t ui32ChannelNum)
1200 {
1201 //
1202 // Check the arguments.
1203 //
1204 ASSERT(uDMABaseValid(ui32Base));
1205 ASSERT(ui32ChannelNum < UDMA_NUM_CHANNELS);
1206
1207 //
1208 // Set the channel priority to high.
1209 //
1210 HWREG(ui32Base + UDMA_O_SETCHNLPRIORITY) = 1 << ui32ChannelNum;
1211 }
1212
1213 //*****************************************************************************
1214 //
1223 //
1224 //*****************************************************************************
1225 __STATIC_INLINE bool
1226 uDMAChannelPriorityGet(uint32_t ui32Base, uint32_t ui32ChannelNum)
1227 {
1228 //
1229 // Check the arguments.
1230 //
1231 ASSERT(uDMABaseValid(ui32Base));
1232 ASSERT(ui32ChannelNum < UDMA_NUM_CHANNELS);
1233
1234 //
1235 // Return the channel priority.
1236 //
1237 return(HWREG(ui32Base + UDMA_O_SETCHNLPRIORITY) & (1 << ui32ChannelNum) ?
1238 UDMA_PRIORITY_HIGH : UDMA_PRIORITY_LOW);
1239 }
1240
1241 //*****************************************************************************
1242 //
1252 //
1253 //*****************************************************************************
1254 __STATIC_INLINE void
1255 uDMAChannelPriorityClear(uint32_t ui32Base, uint32_t ui32ChannelNum)
1256 {
1257 //
1258 // Check the arguments.
1259 //
1260 ASSERT(uDMABaseValid(ui32Base));
1261 ASSERT(ui32ChannelNum < UDMA_NUM_CHANNELS);
1262
1263 //
1264 // Clear the channel priority.
1265 //
1266 HWREG(ui32Base + UDMA_O_CLEARCHNLPRIORITY) = 1 << ui32ChannelNum;
1267 }
1268
1269 //*****************************************************************************
1270 //
1271 // Support for DriverLib in ROM:
1272 // Redirect to implementation in ROM when available.
1273 //
1274 //*****************************************************************************
1275 #ifndef DRIVERLIB_NOROM
1276 #include <driverlib/rom.h>
1277 #ifdef ROM_uDMAChannelAttributeEnable
1278 #undef uDMAChannelAttributeEnable
1279 #define uDMAChannelAttributeEnable ROM_uDMAChannelAttributeEnable
1280 #endif
1281 #ifdef ROM_uDMAChannelAttributeDisable
1282 #undef uDMAChannelAttributeDisable
1283 #define uDMAChannelAttributeDisable ROM_uDMAChannelAttributeDisable
1284 #endif
1285 #ifdef ROM_uDMAChannelAttributeGet
1286 #undef uDMAChannelAttributeGet
1287 #define uDMAChannelAttributeGet ROM_uDMAChannelAttributeGet
1288 #endif
1289 #ifdef ROM_uDMAChannelControlSet
1290 #undef uDMAChannelControlSet
1291 #define uDMAChannelControlSet ROM_uDMAChannelControlSet
1292 #endif
1293 #ifdef ROM_uDMAChannelTransferSet
1294 #undef uDMAChannelTransferSet
1295 #define uDMAChannelTransferSet ROM_uDMAChannelTransferSet
1296 #endif
1297 #ifdef ROM_uDMAChannelScatterGatherSet
1298 #undef uDMAChannelScatterGatherSet
1299 #define uDMAChannelScatterGatherSet ROM_uDMAChannelScatterGatherSet
1300 #endif
1301 #ifdef ROM_uDMAChannelSizeGet
1302 #undef uDMAChannelSizeGet
1303 #define uDMAChannelSizeGet ROM_uDMAChannelSizeGet
1304 #endif
1305 #ifdef ROM_uDMAChannelModeGet
1306 #undef uDMAChannelModeGet
1307 #define uDMAChannelModeGet ROM_uDMAChannelModeGet
1308 #endif
1309 #endif
1310
1311 //*****************************************************************************
1312 //
1313 // Mark the end of the C bindings section for C++ compilers.
1314 //
1315 //*****************************************************************************
1316 #ifdef __cplusplus
1317 }
1318 #endif
1319
1320 #endif // __UDMA_H__
1321
1322 //*****************************************************************************
1323 //
1326 //
1327 //*****************************************************************************
uDMAGetStatus
__STATIC_INLINE uint32_t uDMAGetStatus(uint32_t ui32Base)
Return the status of the uDMA module.
Definition: udma.h:1172
UDMA_NUM_CHANNELS
#define UDMA_NUM_CHANNELS
Definition: udma.h:207
uDMAIntSwEventDisable
__STATIC_INLINE void uDMAIntSwEventDisable(uint32_t ui32Base, uint32_t ui32IntChannel)
Disable interrupt on software event driven uDMA transfers.
Definition: udma.h:1146
uDMAChannelModeGet
uint32_t uDMAChannelModeGet(uint32_t ui32Base, uint32_t ui32ChannelStructIndex)
Gets the transfer mode for a uDMA channel control structure.
Definition: udma.c:514
uDMAIntSwEventEnable
__STATIC_INLINE void uDMAIntSwEventEnable(uint32_t ui32Base, uint32_t ui32IntChannel)
Enable interrupt on software event driven uDMA transfers.
Definition: udma.h:1115
tDMAControlTable::pvSrcEndAddr
volatile void * pvSrcEndAddr
The ending source address of the data transfer.
Definition: udma.h:105
uDMAControlAlternateBaseGet
__STATIC_INLINE void * uDMAControlAlternateBaseGet(uint32_t ui32Base)
Gets the base address for the channel control table alternate structures.
Definition: udma.h:638
debug.h
uDMAIntStatus
__STATIC_INLINE uint32_t uDMAIntStatus(uint32_t ui32Base)
Get the uDMA interrupt status.
Definition: udma.h:1083
uDMAChannelScatterGatherSet
void uDMAChannelScatterGatherSet(uint32_t ui32Base, uint32_t ui32ChannelNum, uint32_t ui32TaskCount, void *pvTaskList, uint32_t ui32IsPeriphSG)
Configures a uDMA channel for scatter-gather mode.
Definition: udma.c:391
UDMA_PRIORITY_LOW
#define UDMA_PRIORITY_LOW
Definition: udma.h:214
ASSERT
#define ASSERT(expr)
Definition: debug.h:65
uDMAEnable
__STATIC_INLINE void uDMAEnable(uint32_t ui32Base)
Enables the uDMA controller for use.
Definition: udma.h:364
uDMAChannelAttributeDisable
void uDMAChannelAttributeDisable(uint32_t ui32Base, uint32_t ui32ChannelNum, uint32_t ui32Attr)
Disables attributes of an uDMA channel.
Definition: udma.c:123
uDMAErrorStatusGet
__STATIC_INLINE uint32_t uDMAErrorStatusGet(uint32_t ui32Base)
Gets the uDMA error status.
Definition: udma.h:417
uDMAChannelAttributeEnable
void uDMAChannelAttributeEnable(uint32_t ui32Base, uint32_t ui32ChannelNum, uint32_t ui32Attr)
Enables attributes of a uDMA channel.
Definition: udma.c:72
uDMAChannelControlSet
void uDMAChannelControlSet(uint32_t ui32Base, uint32_t ui32ChannelStructIndex, uint32_t ui32Control)
Sets the control parameters for a uDMA channel control structure.
Definition: udma.c:228
uDMAIntRegister
__STATIC_INLINE void uDMAIntRegister(uint32_t ui32Base, uint32_t ui32IntChannel, void(*pfnHandler)(void))
Registers an interrupt handler for the uDMA controller.
Definition: udma.h:979
uDMAChannelEnable
__STATIC_INLINE void uDMAChannelEnable(uint32_t ui32Base, uint32_t ui32ChannelNum)
Enables a uDMA channel for operation.
Definition: udma.h:475
tDMAControlTable::ui32Spare
volatile uint32_t ui32Spare
An unused location.
Definition: udma.h:108
uDMAChannelPriorityGet
__STATIC_INLINE bool uDMAChannelPriorityGet(uint32_t ui32Base, uint32_t ui32ChannelNum)
Get the priority of a uDMA channel.
Definition: udma.h:1226
uDMAChannelPriorityClear
__STATIC_INLINE void uDMAChannelPriorityClear(uint32_t ui32Base, uint32_t ui32ChannelNum)
Clear the priority of a uDMA channel.
Definition: udma.h:1255
uDMAControlBaseGet
__STATIC_INLINE void * uDMAControlBaseGet(uint32_t ui32Base)
Gets the base address for the channel control table.
Definition: udma.h:610
uDMADisable
__STATIC_INLINE void uDMADisable(uint32_t ui32Base)
Disables the uDMA controller for use.
Definition: udma.h:390
uDMAChannelPrioritySet
__STATIC_INLINE void uDMAChannelPrioritySet(uint32_t ui32Base, uint32_t ui32ChannelNum)
Set the priority of a uDMA channel.
Definition: udma.h:1199
uDMAChannelDisable
__STATIC_INLINE void uDMAChannelDisable(uint32_t ui32Base, uint32_t ui32ChannelNum)
Disables a uDMA channel for operation.
Definition: udma.h:504
uDMAChannelIsEnabled
__STATIC_INLINE bool uDMAChannelIsEnabled(uint32_t ui32Base, uint32_t ui32ChannelNum)
Checks if a uDMA channel is enabled for operation.
Definition: udma.h:535
tDMAControlTable::ui32Control
volatile uint32_t ui32Control
The channel control mode.
Definition: udma.h:107
interrupt.h
tDMAControlTable::pvDstEndAddr
volatile void * pvDstEndAddr
The ending destination address of the data transfer.
Definition: udma.h:106
IntUnregister
void IntUnregister(uint32_t ui32Interrupt)
Unregisters the function to be called when an interrupt occurs.
Definition: interrupt.c:205
uDMAChannelTransferSet
void uDMAChannelTransferSet(uint32_t ui32Base, uint32_t ui32ChannelStructIndex, uint32_t ui32Mode, void *pvSrcAddr, void *pvDstAddr, uint32_t ui32TransferSize)
Sets the transfer parameters for a uDMA channel control structure.
Definition: udma.c:265
tDMAControlTable
A structure that defines an entry in the channel control table.
Definition: udma.h:103
uDMAChannelAttributeGet
uint32_t uDMAChannelAttributeGet(uint32_t ui32Base, uint32_t ui32ChannelNum)
Gets the enabled attributes of a uDMA channel.
Definition: udma.c:174
uDMAControlBaseSet
__STATIC_INLINE void uDMAControlBaseSet(uint32_t ui32Base, void *pControlTable)
Sets the base address for the channel control table.
Definition: udma.h:580
uDMAIntClear
__STATIC_INLINE void uDMAIntClear(uint32_t ui32Base, uint32_t ui32ChanMask)
Clears uDMA interrupt done status.
Definition: udma.h:1056
uDMAChannelRequest
__STATIC_INLINE void uDMAChannelRequest(uint32_t ui32Base, uint32_t ui32ChannelNum)
Requests a uDMA channel to start a transfer.
Definition: udma.h:674
rom.h
uDMAChannelSizeGet
uint32_t uDMAChannelSizeGet(uint32_t ui32Base, uint32_t ui32ChannelStructIndex)
Gets the current transfer size for a uDMA channel control structure.
Definition: udma.c:462
uDMAIntUnregister
__STATIC_INLINE void uDMAIntUnregister(uint32_t ui32Base, uint32_t ui32IntChannel)
Unregisters an interrupt handler for the uDMA controller.
Definition: udma.h:1021
UDMA_PRIORITY_HIGH
#define UDMA_PRIORITY_HIGH
Definition: udma.h:215
uDMAErrorStatusClear
__STATIC_INLINE void uDMAErrorStatusClear(uint32_t ui32Base)
Clears the uDMA error interrupt.
Definition: udma.h:443
IntDisable
void IntDisable(uint32_t ui32Interrupt)
Disables an interrupt.
Definition: interrupt.c:383
IntRegister
void IntRegister(uint32_t ui32Interrupt, void(*pfnHandler)(void))
Registers a function to be called when an interrupt occurs.
Definition: interrupt.c:157
IntEnable
void IntEnable(uint32_t ui32Interrupt)
Enables an interrupt.
Definition: interrupt.c:323