## UART0

Instance: UART0
Component: UART
Base address: 0x40001000

Universal Asynchronous Receiver/Transmitter (UART) interface

### TOP:UART0 Register Summary

Register Name | Type | Register Width (Bits) | Register Reset | Address Offset | Physical Address
DR | RW | 32 | 0x0000 0000 | 0x0000 0000 | 0x4000 1000
ECR | WO | 32 | 0x0000 0000 | 0x0000 0004 | 0x4000 1004
RSR | RO | 32 | 0x0000 0000 | 0x0000 0004 | 0x4000 1004
FR | RO | 32 | 0x0000 0090 | 0x0000 0018 | 0x4000 1018
IBRD | RW | 32 | 0x0000 0000 | 0x0000 0024 | 0x4000 1024
FBRD | RW | 32 | 0x0000 0000 | 0x0000 0028 | 0x4000 1028
LCRH | RW | 32 | 0x0000 0000 | 0x0000 002C | 0x4000 102C
CTL | RW | 32 | 0x0000 0300 | 0x0000 0030 | 0x4000 1030
IFLS | RW | 32 | 0x0000 0012 | 0x0000 0034 | 0x4000 1034
IMSC | RW | 32 | 0x0000 0000 | 0x0000 0038 | 0x4000 1038
RIS | RO | 32 | 0x0000 000D | 0x0000 003C | 0x4000 103C
MIS | RO | 32 | 0x0000 0000 | 0x0000 0040 | 0x4000 1040
ICR | WO | 32 | 0x0000 0000 | 0x0000 0044 | 0x4000 1044
DMACTL | RW | 32 | 0x0000 0000 | 0x0000 0048 | 0x4000 1048

### TOP:UART0 Register Descriptions

### TOP:UART:DR

Address offset | 0x0000 0000
Physical address | 0x4000 1000 | Instance | UART0
Description | UART Data For words to be transmitted: - if the FIFOs are enabled (LCRH.FEN = 1), data written to this location is pushed onto the transmit FIFO - if the FIFOs are not enabled (LCRH.FEN = 0), data is stored in the transmitter holding register (the bottom word of the transmit FIFO). The write operation initiates transmission from the UART. The data is prefixed with a start bit, appended with the appropriate parity bit (if parity is enabled), and a stop bit. The resultant word is then transmitted. For received words: - if the FIFOs are enabled (LCRH.FEN = 1), the data byte and the 4-bit status (break, frame, parity, and overrun) is pushed onto the 12-bit wide receive FIFO - if the FIFOs are not enabled (LCRH.FEN = 0), the data byte and status are stored in the receiving holding register (the bottom word of the receive FIFO). The received data byte is read by performing reads from this register along with the corresponding status information. The status information can also be read by a read of the RSR register.
Type | RW

Bits | Field Name | Description | Type | Reset
31:12 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0 0000
11 | OE | UART Overrun Error: This bit is set to 1 if data is received and the receive FIFO is already full. The FIFO contents remain valid because no more data is written when the FIFO is full, , only the contents of the shift register are overwritten. This is cleared to 0 once there is an empty space in the FIFO and a new character can be written to it. | RO | 0
10 | BE | UART Break Error: This bit is set to 1 if a break condition was detected, indicating that the received data input (UARTRXD input pin) was held LOW for longer than a full-word transmission time (defined as start, data, parity and stop bits). In FIFO mode, this error is associated with the character at the top of the FIFO (i.e., the oldest received data character since last read). When a break occurs, a 0 character is loaded into the FIFO. The next character is enabled after the receive data input (UARTRXD input pin) goes to a 1 (marking state), and the next valid start bit is received. | RO | 0
9 | PE | UART Parity Error: When set to 1, it indicates that the parity of the received data character does not match the parity that the LCRH.EPS and LCRH.SPS select. In FIFO mode, this error is associated with the character at the top of the FIFO (i.e., the oldest received data character since last read). | RO | 0
8 | FE | UART Framing Error: When set to 1, it indicates that the received character did not have a valid stop bit (a valid stop bit is 1). In FIFO mode, this error is associated with the character at the top of the FIFO (i.e., the oldest received data character since last read). | RO | 0
7:0 | DATA | Data transmitted or received: On writes, the transmit data character is pushed into the FIFO. On reads, the oldest received data character since the last read is returned. | RW | 0x00

### TOP:UART:ECR

Address offset | 0x0000 0004
Physical address | 0x4000 1004 | Instance | UART0
Description | UART Error Clear Register This register is mapped to the same address as RSR register. Reads from this address are associated with RSR register and return the receive status. Writes to this address are associated with ECR register and clear the receive status flags (framing, parity, break, and overrun errors).
Type | WO

Bits | Field Name | Description | Type | Reset
31:4 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(WO std text) | WO | 0x000 0000
3 | OE | The framing (FE), parity (PE), break (BE) and overrun (OE) errors are cleared to 0 by any write to this register. | WO | 0
2 | BE | The framing (FE), parity (PE), break (BE) and overrun (OE) errors are cleared to 0 by any write to this register. | WO | 0
1 | PE | The framing (FE), parity (PE), break (BE) and overrun (OE) errors are cleared to 0 by any write to this register. | WO | 0
0 | FE | The framing (FE), parity (PE), break (BE) and overrun (OE) errors are cleared to 0 by any write to this register. | WO | 0

### TOP:UART:RSR

Address offset | 0x0000 0004
Physical address | 0x4000 1004 | Instance | UART0
Description | UART Status Register This register is mapped to the same address as ECR register. Reads from this address are associated with RSR register and return the receive status. Writes to this address are associated with ECR register and clear the receive status flags (framing, parity, break, and overrun errors). If the status is read from this register, then the status information for break, framing and parity corresponds to the data character read from the Data Register, DR prior to reading the RSR. The status information for overrun is set immediately when an overrun condition occurs.
Type | RO

Bits | Field Name | Description | Type | Reset
31:4 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x000 0000
3 | OE | UART Overrun Error: This bit is set to 1 if data is received and the receive FIFO is already full. The FIFO contents remain valid because no more data is written when the FIFO is full, , only the contents of the shift register are overwritten. This is cleared to 0 once there is an empty space in the FIFO and a new character can be written to it. | RO | 0
2 | BE | UART Break Error: This bit is set to 1 if a break condition was detected, indicating that the received data input (UARTRXD input pin) was held LOW for longer than a full-word transmission time (defined as start, data, parity and stop bits). When a break occurs, a 0 character is loaded into the FIFO. The next character is enabled after the receive data input (UARTRXD input pin) goes to a 1 (marking state), and the next valid start bit is received. | RO | 0
1 | PE | UART Parity Error: When set to 1, it indicates that the parity of the received data character does not match the parity that the LCRH.EPS and LCRH.SPS select. | RO | 0
0 | FE | UART Framing Error: When set to 1, it indicates that the received character did not have a valid stop bit (a valid stop bit is 1). | RO | 0

### TOP:UART:FR

Address offset | 0x0000 0018
Physical address | 0x4000 1018 | Instance | UART0
Description | UART Flag Register Reads from this register return the UART flags.
Type | RO

Bits | Field Name | Description | Type | Reset
31:8 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x00 0000
7 | TXFE | UART Transmit FIFO Empty: The meaning of this bit depends on the state of LCRH.FEN . - If the FIFO is disabled, this bit is set when the transmit holding register is empty. - If the FIFO is enabled, this bit is set when the transmit FIFO is empty. This bit does not indicate if there is data in the transmit shift register. | RO | 1
6 | RXFF | UART Receive FIFO Full: The meaning of this bit depends on the state of LCRH.FEN. - If the FIFO is disabled, this bit is set when the receive holding register is full. - If the FIFO is enabled, this bit is set when the receive FIFO is full. | RO | 0
5 | TXFF | UART Transmit FIFO Full: Transmit FIFO full. The meaning of this bit depends on the state of LCRH.FEN. - If the FIFO is disabled, this bit is set when the transmit holding register is full. - If the FIFO is enabled, this bit is set when the transmit FIFO is full. | RO | 0
4 | RXFE | UART Receive FIFO Empty: Receive FIFO empty. The meaning of this bit depends on the state of LCRH.FEN. - If the FIFO is disabled, this bit is set when the receive holding register is empty. - If the FIFO is enabled, this bit is set when the receive FIFO is empty. | RO | 1
3 | BUSY | UART Busy: If this bit is set to 1, the UART is busy transmitting data. This bit remains set until the complete byte, including all the stop bits, has been sent from the shift register. This bit is set as soon as the transmit FIFO becomes non-empty, regardless of whether the UART is enabled or not. | RO | 0
2:1 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0
0 | CTS | Clear To Send: This bit is the complement of the active-low UART CTS input pin. That is, the bit is 1 when CTS input pin is LOW. | RO | 0

### TOP:UART:IBRD

Address offset | 0x0000 0024
Physical address | 0x4000 1024 | Instance | UART0
Description | UART Integer Baud-Rate Divisor If this register is modified while trasmission or reception is on-going, the baudrate will not be updated until transmission or reception of the current character is complete.
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text) | RW | 0x0000
15:0 | DIVINT | The integer baud rate divisor: The baud rate divisor is calculated using the formula below: Baud rate divisor = (UART reference clock frequency) / (16 * Baud rate) Baud rate divisor must be minimum 1 and maximum 65535. That is, DIVINT=0 does not give a valid baud rate. Similarly, if DIVINT=0xFFFF, any non-zero values in FBRD.DIVFRAC will be illegal. A valid value must be written to this field before the UART can be used for RX or TX operations. | RW | 0x0000

### TOP:UART:FBRD

Address offset | 0x0000 0028
Physical address | 0x4000 1028 | Instance | UART0
Description | UART Fractional Baud-Rate Divisor If this register is modified while trasmission or reception is on-going, the baudrate will not be updated until transmission or reception of the current character is complete.
Type | RW

Bits | Field Name | Description | Type | Reset
31:6 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text) | RW | 0x000 0000
5:0 | DIVFRAC | Fractional Baud-Rate Divisor: The baud rate divisor is calculated using the formula below: Baud rate divisor = (UART reference clock frequency) / (16 * Baud rate) Baud rate divisor must be minimum 1 and maximum 65535. That is, IBRD.DIVINT=0 does not give a valid baud rate. Similarly, if IBRD.DIVINT=0xFFFF, any non-zero values in DIVFRAC will be illegal. A valid value must be written to this field before the UART can be used for RX or TX operations. | RW | 0x00

### TOP:UART:LCRH

Address offset | 0x0000 002C
Physical address | 0x4000 102C | Instance | UART0
Description | UART Line Control
Type | RW

Bits | Field Name | Description | Type | Reset
31:8 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text) | RW | 0x00 0000
7 | SPS | UART Stick Parity Select: 0: Stick parity is disabled 1: The parity bit is transmitted and checked as invert of EPS field (i.e. the parity bit is transmitted and checked as 1 when EPS = 0). This bit has no effect when PEN disables parity checking and generation. | RW | 0
6:5 | WLEN | UART Word Length: These bits indicate the number of data bits transmitted or received in a frame.
Value | ENUM name | Description
0x0 | 5 | Word Length 5 bits
0x1 | 6 | Word Length 6 bits
0x2 | 7 | Word Length 7 bits
0x3 | 8 | Word Length 8 bits
| RW | 0x0
4 | FEN | UART Enable FIFOs
Value | ENUM name | Description
0 | DIS | FIFOs are disabled (character mode) that is, the FIFOs become 1-byte-deep holding registers.
1 | EN | Transmit and receive FIFO buffers are enabled (FIFO mode)
| RW | 0
3 | STP2 | UART Two Stop Bits Select: If this bit is set to 1, two stop bits are transmitted at the end of the frame. The receive logic does not check for two stop bits being received. | RW | 0
2 | EPS | UART Even Parity Select
Value | ENUM name | Description
0 | ODD | Odd parity: The UART generates or checks for an odd number of 1s in the data and parity bits.
1 | EVEN | Even parity: The UART generates or checks for an even number of 1s in the data and parity bits.
| RW | 0
1 | PEN | UART Parity Enable This bit controls generation and checking of parity bit.
Value | ENUM name | Description
0 | DIS | Parity is disabled and no parity bit is added to the data frame
1 | EN | Parity checking and generation is enabled.
| RW | 0
0 | BRK | UART Send Break If this bit is set to 1, a low-level is continually output on the UARTTXD output pin, after completing transmission of the current character. For the proper execution of the break command, the software must set this bit for at least two complete frames. For normal use, this bit must be cleared to 0. | RW | 0

### TOP:UART:CTL

Address offset | 0x0000 0030
Physical address | 0x4000 1030 | Instance | UART0
Description | UART Control
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0000
15 | CTSEN | CTS hardware flow control enable
Value | ENUM name | Description
0 | DIS | CTS hardware flow control disabled
1 | EN | CTS hardware flow control enabled
| RW | 0
14 | RTSEN | RTS hardware flow control enable
Value | ENUM name | Description
0 | DIS | RTS hardware flow control disabled
1 | EN | RTS hardware flow control enabled
| RW | 0
13:12 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text) | RW | 0x0
11 | RTS | Request to Send This bit is the complement of the active-low UART RTS output. That is, when the bit is programmed to a 1 then RTS output on the pins is LOW. | RW | 0
10 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text) | RW | 0
9 | RXE | UART Receive Enable If the UART is disabled in the middle of reception, it completes the current character before stopping.
Value | ENUM name | Description
0 | DIS | UART Receive disabled
1 | EN | UART Receive enabled
| RW | 1
8 | TXE | UART Transmit Enable If the UART is disabled in the middle of transmission, it completes the current character before stopping.
Value | ENUM name | Description
0 | DIS | UART Transmit disabled
1 | EN | UART Transmit enabled
| RW | 1
7 | LBE | UART Loop Back Enable: Enabling the loop-back mode connects the UARTTXD output from the UART to UARTRXD input of the UART.
Value | ENUM name | Description
0 | DIS | Loop Back disabled
1 | EN | Loop Back enabled
| RW | 0
6:1 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text) | RW | 0x00
0 | UARTEN | UART Enable
Value | ENUM name | Description
0 | DIS | UART disabled
1 | EN | UART enabled
| RW | 0

### TOP:UART:IFLS

Address offset | 0x0000 0034
Physical address | 0x4000 1034 | Instance | UART0
Description | UART Interrupt FIFO Level Select
Type | RW

Bits | Field Name | Description | Type | Reset
31:6 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text) | RW | 0x000 0000
5:3 | RXSEL | Receive interrupt FIFO level select: This field sets the trigger points for the receive interrupt. Values 0b101-0b111 are reserved.
Value | ENUM name | Description
0x0 | 1_8 | Receive FIFO becomes >= 1/8 full
0x1 | 2_8 | Receive FIFO becomes >= 1/4 full
0x2 | 4_8 | Receive FIFO becomes >= 1/2 full
0x3 | 6_8 | Receive FIFO becomes >= 3/4 full
0x4 | 7_8 | Receive FIFO becomes >= 7/8 full
| RW | 0x2
2:0 | TXSEL | Transmit interrupt FIFO level select: This field sets the trigger points for the transmit interrupt. Values 0b101-0b111 are reserved.
Value | ENUM name | Description
0x0 | 1_8 | Transmit FIFO becomes <= 1/8 full
0x1 | 2_8 | Transmit FIFO becomes <= 1/4 full
0x2 | 4_8 | Transmit FIFO becomes <= 1/2 full
0x3 | 6_8 | Transmit FIFO becomes <= 3/4 full
0x4 | 7_8 | Transmit FIFO becomes <= 7/8 full
| RW | 0x2

### TOP:UART:IMSC

Address offset | 0x0000 0038
Physical address | 0x4000 1038 | Instance | UART0
Description | UART Interrupt Mask Set/Clear Register
Type | RW

Bits | Field Name | Description | Type | Reset
31:11 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text) | RW | 0x00 0000
10 | OEIM | Overrun error interrupt mask. A read returns the current mask for UART's overrun error interrupt. On a write of 1, the mask of the overrun error interrupt is set which means the interrupt state will be reflected in MIS.OEMIS. A write of 0 clears the mask which means MIS.OEMIS will not reflect the interrupt. | RW | 0
9 | BEIM | Break error interrupt mask. A read returns the current mask for UART's break error interrupt. On a write of 1, the mask of the overrun error interrupt is set which means the interrupt state will be reflected in MIS.BEMIS. A write of 0 clears the mask which means MIS.BEMIS will not reflect the interrupt. | RW | 0
8 | PEIM | Parity error interrupt mask. A read returns the current mask for UART's parity error interrupt. On a write of 1, the mask of the overrun error interrupt is set which means the interrupt state will be reflected in MIS.PEMIS. A write of 0 clears the mask which means MIS.PEMIS will not reflect the interrupt. | RW | 0
7 | FEIM | Framing error interrupt mask. A read returns the current mask for UART's framing error interrupt. On a write of 1, the mask of the overrun error interrupt is set which means the interrupt state will be reflected in MIS.FEMIS. A write of 0 clears the mask which means MIS.FEMIS will not reflect the interrupt. | RW | 0
6 | RTIM | Receive timeout interrupt mask. A read returns the current mask for UART's receive timeout interrupt. On a write of 1, the mask of the overrun error interrupt is set which means the interrupt state will be reflected in MIS.RTMIS. A write of 0 clears the mask which means this bitfield will not reflect the interrupt. The raw interrupt for receive timeout RIS.RTRIS cannot be set unless the mask is set (RTIM = 1). This is because the mask acts as an enable for power saving. That is, the same status can be read from MIS.RTMIS and RIS.RTRIS. | RW | 0
5 | TXIM | Transmit interrupt mask. A read returns the current mask for UART's transmit interrupt. On a write of 1, the mask of the overrun error interrupt is set which means the interrupt state will be reflected in MIS.TXMIS. A write of 0 clears the mask which means MIS.TXMIS will not reflect the interrupt. | RW | 0
4 | RXIM | Receive interrupt mask. A read returns the current mask for UART's receive interrupt. On a write of 1, the mask of the overrun error interrupt is set which means the interrupt state will be reflected in MIS.RXMIS. A write of 0 clears the mask which means MIS.RXMIS will not reflect the interrupt. | RW | 0
3:2 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text) | RW | 0x0
1 | CTSMIM | Clear to Send (CTS) modem interrupt mask. A read returns the current mask for UART's clear to send interrupt. On a write of 1, the mask of the overrun error interrupt is set which means the interrupt state will be reflected in MIS.CTSMMIS. A write of 0 clears the mask which means MIS.CTSMMIS will not reflect the interrupt. | RW | 0
0 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text) | RW | 0

### TOP:UART:RIS

Address offset | 0x0000 003C
Physical address | 0x4000 103C | Instance | UART0
Description | Raw Interrupt Status Register
Type | RO

Bits | Field Name | Description | Type | Reset
31:11 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x00 0000
10 | OERIS | Overrun error interrupt status: This field returns the raw interrupt state of UART's overrun error interrupt. Overrun error occurs if data is received and the receive FIFO is full. | RO | 0
9 | BERIS | Break error interrupt status: This field returns the raw interrupt state of UART's break error interrupt. Break error is set when a break condition is detected, indicating that the received data input (UARTRXD input pin) was held LOW for longer than a full-word transmission time (defined as start, data, parity and stop bits). | RO | 0
8 | PERIS | Parity error interrupt status: This field returns the raw interrupt state of UART's parity error interrupt. Parity error is set if the parity of the received data character does not match the parity that the LCRH.EPS and LCRH.SPS select. | RO | 0
7 | FERIS | Framing error interrupt status: This field returns the raw interrupt state of UART's framing error interrupt. Framing error is set if the received character does not have a valid stop bit (a valid stop bit is 1). | RO | 0
6 | RTRIS | Receive timeout interrupt status: This field returns the raw interrupt state of UART's receive timeout interrupt. The receive timeout interrupt is asserted when the receive FIFO is not empty, and no more data is received during a 32-bit period. The receive timeout interrupt is cleared either when the FIFO becomes empty through reading all the data, or when a 1 is written to ICR.RTIC. The raw interrupt for receive timeout cannot be set unless the mask is set (IMSC.RTIM = 1). This is because the mask acts as an enable for power saving. That is, the same status can be read from MIS.RTMIS and RTRIS. | RO | 0
5 | TXRIS | Transmit interrupt status: This field returns the raw interrupt state of UART's transmit interrupt. When FIFOs are enabled (LCRH.FEN = 1), the transmit interrupt is asserted if the number of bytes in transmit FIFO is equal to or lower than the programmed trigger level (IFLS.TXSEL). The transmit interrupt is cleared by writing data to the transmit FIFO until it becomes greater than the trigger level, or by clearing the interrupt through ICR.TXIC. When FIFOs are disabled (LCRH.FEN = 0), that is they have a depth of one location, the transmit interrupt is asserted if there is no data present in the transmitters single location. It is cleared by performing a single write to the transmit FIFO, or by clearing the interrupt through ICR.TXIC. | RO | 0
4 | RXRIS | Receive interrupt status: This field returns the raw interrupt state of UART's receive interrupt. When FIFOs are enabled (LCRH.FEN = 1), the receive interrupt is asserted if the receive FIFO reaches the programmed trigger level (IFLS.RXSEL). The receive interrupt is cleared by reading data from the receive FIFO until it becomes less than the trigger level, or by clearing the interrupt through ICR.RXIC. When FIFOs are disabled (LCRH.FEN = 0), that is they have a depth of one location, the receive interrupt is asserted if data is received thereby filling the location. The receive interrupt is cleared by performing a single read of the receive FIFO, or by clearing the interrupt through ICR.RXIC. | RO | 0
3:2 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x3
1 | CTSRMIS | Clear to Send (CTS) modem interrupt status: This field returns the raw interrupt state of UART's clear to send interrupt. | RO | 0
0 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 1

### TOP:UART:MIS

Address offset | 0x0000 0040
Physical address | 0x4000 1040 | Instance | UART0
Description | UART Masked Interrupt Status Register
Type | RO

Bits | Field Name | Description | Type | Reset
31:11 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x00 0000
10 | OEMIS | Overrun error masked interrupt status: This field returns the masked interrupt state of the overrun interrupt which is the AND product of raw interrupt state RIS.OERIS and the mask setting IMSC.OEIM. | RO | 0
9 | BEMIS | Break error masked interrupt status: This field returns the masked interrupt state of the break error interrupt which is the AND product of raw interrupt state RIS.BERIS and the mask setting IMSC.BEIM. | RO | 0
8 | PEMIS | Parity error masked interrupt status: This field returns the masked interrupt state of the parity error interrupt which is the AND product of raw interrupt state RIS.PERIS and the mask setting IMSC.PEIM. | RO | 0
7 | FEMIS | Framing error masked interrupt status: Returns the masked interrupt state of the framing error interrupt which is the AND product of raw interrupt state RIS.FERIS and the mask setting IMSC.FEIM. | RO | 0
6 | RTMIS | Receive timeout masked interrupt status: Returns the masked interrupt state of the receive timeout interrupt. The raw interrupt for receive timeout cannot be set unless the mask is set (IMSC.RTIM = 1). This is because the mask acts as an enable for power saving. That is, the same status can be read from RTMIS and RIS.RTRIS. | RO | 0
5 | TXMIS | Transmit masked interrupt status: This field returns the masked interrupt state of the transmit interrupt which is the AND product of raw interrupt state RIS.TXRIS and the mask setting IMSC.TXIM. | RO | 0
4 | RXMIS | Receive masked interrupt status: This field returns the masked interrupt state of the receive interrupt which is the AND product of raw interrupt state RIS.RXRIS and the mask setting IMSC.RXIM. | RO | 0
3:2 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0
1 | CTSMMIS | Clear to Send (CTS) modem masked interrupt status: This field returns the masked interrupt state of the clear to send interrupt which is the AND product of raw interrupt state RIS.CTSRMIS and the mask setting IMSC.CTSMIM. | RO | 0
0 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0

### TOP:UART:ICR

Address offset | 0x0000 0044
Physical address | 0x4000 1044 | Instance | UART0
Description | UART Interrupt Clear On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect.
Type | WO

Bits | Field Name | Description | Type | Reset
31:16 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(WO std text) | WO | 0x0000
15:11 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(WO std text) | WO | 0x00
10 | OEIC | Overrun error interrupt clear: Writing 1 to this field clears the overrun error interrupt (RIS.OERIS). Writing 0 has no effect. | WO | 0
9 | BEIC | Break error interrupt clear: Writing 1 to this field clears the break error interrupt (RIS.BERIS). Writing 0 has no effect. | WO | 0
8 | PEIC | Parity error interrupt clear: Writing 1 to this field clears the parity error interrupt (RIS.PERIS). Writing 0 has no effect. | WO | 0
7 | FEIC | Framing error interrupt clear: Writing 1 to this field clears the framing error interrupt (RIS.FERIS). Writing 0 has no effect. | WO | 0
6 | RTIC | Receive timeout interrupt clear: Writing 1 to this field clears the receive timeout interrupt (RIS.RTRIS). Writing 0 has no effect. | WO | 0
5 | TXIC | Transmit interrupt clear: Writing 1 to this field clears the transmit interrupt (RIS.TXRIS). Writing 0 has no effect. | WO | 0
4 | RXIC | Receive interrupt clear: Writing 1 to this field clears the receive interrupt (RIS.RXRIS). Writing 0 has no effect. | WO | 0
3:2 | RESERVED2 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. Write 0 | WO | 0x0
1 | CTSMIC | Clear to Send (CTS) modem interrupt clear: Writing 1 to this field clears the clear to send interrupt (RIS.CTSRMIS). Writing 0 has no effect. | WO | 0
0 | RESERVED0 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. Write 0. | WO | 0

### TOP:UART:DMACTL

Address offset | 0x0000 0048
Physical address | 0x4000 1048 | Instance | UART0
Description | DMA Control Register
Type | RW

Bits | Field Name | Description | Type | Reset
31:3 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text) | RW | 0x0000 0000
2 | DMAONERR | DMA on error. If this bit is set to 1, the DMA receive request outputs (for single and burst requests) are disabled when the UART error interrupt is asserted (more specifically if any of the error interrupts RIS.PERIS, RIS.BERIS, RIS.FERIS or RIS.OERIS are asserted). | RW | 0
1 | TXDMAE | Transmit DMA enable. If this bit is set to 1, DMA for the transmit FIFO is enabled. | RW | 0
0 | RXDMAE | Receive DMA enable. If this bit is set to 1, DMA for the receive FIFO is enabled. | RW | 0