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aon_wuc.c
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1 /******************************************************************************
2 * Filename: aon_wuc.c
3 * Revised: 2015-01-13 16:59:55 +0100 (ti, 13 jan 2015)
4 * Revision: 42365
5 *
6 * Description: Driver for the AON Wake-Up Controller.
7 *
8 * Copyright (c) 2015, Texas Instruments Incorporated
9 * All rights reserved.
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions are met:
13 *
14 * 1) Redistributions of source code must retain the above copyright notice,
15 * this list of conditions and the following disclaimer.
16 *
17 * 2) Redistributions in binary form must reproduce the above copyright notice,
18 * this list of conditions and the following disclaimer in the documentation
19 * and/or other materials provided with the distribution.
20 *
21 * 3) Neither the name of the ORGANIZATION nor the names of its contributors may
22 * be used to endorse or promote products derived from this software without
23 * specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
26 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
28 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
29 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
35 * POSSIBILITY OF SUCH DAMAGE.
36 *
37 ******************************************************************************/
38
39 #include <driverlib/aon_wuc.h>
40
41 //*****************************************************************************
42 //
43 // Handle support for DriverLib in ROM:
44 // This section will undo prototype renaming made in the header file
45 //
46 //*****************************************************************************
47 #ifndef DRIVERLIB_GENERATE_ROM
48 #undef AONWUCAuxClockConfigSet
49 #define AONWUCAuxClockConfigSet NOROM_AONWUCAuxClockConfigSet
50 #undef AONWUCAuxSRamConfig
51 #define AONWUCAuxSRamConfig NOROM_AONWUCAuxSRamConfig
52 #undef AONWUCAuxWakeupEvent
53 #define AONWUCAuxWakeupEvent NOROM_AONWUCAuxWakeupEvent
54 #undef AONWUCAuxReset
55 #define AONWUCAuxReset NOROM_AONWUCAuxReset
56 #undef AONWUCRechargeCtrlConfigSet
57 #define AONWUCRechargeCtrlConfigSet NOROM_AONWUCRechargeCtrlConfigSet
58 #undef AONWUCOscConfig
59 #define AONWUCOscConfig NOROM_AONWUCOscConfig
60 #endif
61
62 //*****************************************************************************
63 //
65 //
66 //*****************************************************************************
67 void
68 AONWUCAuxClockConfigSet(uint32_t ui32ClkSrc, uint32_t ui32ClkDiv)
69 {
70 uint32_t ui32Reg;
71
72 //
73 // Check the arguments.
74 //
75 ASSERT((ui32ClkSrc == AONWUC_CLOCK_SRC_HF) ||
76 (ui32ClkSrc == AONWUC_CLOCK_SRC_MF) ||
77 (ui32ClkSrc == AONWUC_CLOCK_SRC_LF));
78 ASSERT((ui32ClkDiv == AUX_CLOCK_DIV_2) ||
79 (ui32ClkDiv == AUX_CLOCK_DIV_4) ||
80 (ui32ClkDiv == AUX_CLOCK_DIV_8) ||
81 (ui32ClkDiv == AUX_CLOCK_DIV_16) ||
82 (ui32ClkDiv == AUX_CLOCK_DIV_32) ||
83 (ui32ClkDiv == AUX_CLOCK_DIV_64) ||
84 (ui32ClkDiv == AUX_CLOCK_DIV_128) ||
85 (ui32ClkDiv == AUX_CLOCK_DIV_256) ||
86 (ui32ClkDiv == AUX_CLOCK_DIV_UNUSED));
87
88 //
89 // Configure the clock for the AUX domain.
90 //
91 ui32Reg = HWREG(AON_WUC_BASE + AON_WUC_O_AUXCLK);
92
93 //
94 // Check if we need to update the clock division factor
95 //
96 if(ui32ClkDiv != AUX_CLOCK_DIV_UNUSED)
97 {
98 ui32Reg = (ui32Reg & ~AON_WUC_AUXCLK_SCLK_HF_DIV_M) | ui32ClkDiv;
99 HWREG(AON_WUC_BASE + AON_WUC_O_AUXCLK) = ui32Reg;
100
101 // If switching to a HF clocks source for AUX it is necessary to
102 // synchronize the write on the AON RTC to ensure the clock division is
103 // updated before requesting the clock source
104 //
105 if(ui32ClkSrc == AONWUC_CLOCK_SRC_HF)
106 {
107 HWREG(AON_RTC_BASE + AON_RTC_O_SYNC);
108 }
109 }
110
111 //
112 // Configure the clock for the AUX domain.
113 //
114 ui32Reg &= ~AON_WUC_AUXCLK_SRC_M;
115 if(ui32ClkSrc == AONWUC_CLOCK_SRC_HF)
116 {
117 ui32Reg |= AON_WUC_AUXCLK_SRC_SCLK_HF;
118 }
119 else if(ui32ClkSrc == AONWUC_CLOCK_SRC_MF)
120 {
121 ui32Reg |= AON_WUC_AUXCLK_SRC_SCLK_MF;
122 }
123 else if(ui32ClkSrc == AONWUC_CLOCK_SRC_LF)
124 {
125 ui32Reg |= AON_WUC_AUXCLK_SRC_SCLK_LF;
126 }
127 HWREG(AON_WUC_BASE + AON_WUC_O_AUXCLK) = ui32Reg;
128 }
129
130 //*****************************************************************************
131 //
133 //
134 //*****************************************************************************
135 void
136 AONWUCAuxSRamConfig(uint32_t ui32Retention)
137 {
138
139 //
140 // Enable/disable the retention.
141 //
142 if(ui32Retention)
143 {
144 HWREG(AON_WUC_BASE + AON_WUC_O_AUXCFG) |= AON_WUC_AUXCFG_RAM_RET_EN;
145 }
146 else
147 {
148 HWREG(AON_WUC_BASE + AON_WUC_O_AUXCFG) &= ~AON_WUC_AUXCFG_RAM_RET_EN;
149 }
150 }
151
152 //*****************************************************************************
153 //
155 //
156 //*****************************************************************************
157 void
158 AONWUCAuxWakeupEvent(uint32_t ui32Mode)
159 {
160 uint32_t ui32Reg;
161
162 //
163 // Check the arguments.
164 //
165 ASSERT((ui32Mode == AONWUC_AUX_WAKEUP_SWEVT) ||
166 (ui32Mode == AONWUC_AUX_WAKEUP) ||
167 (ui32Mode == AONWUC_AUX_ALLOW_SLEEP));
168
169 //
170 // Wake up the AUX domain.
171 //
172 ui32Reg = HWREG(AON_WUC_BASE + AON_WUC_O_AUXCTL);
173
174 if(ui32Mode == AONWUC_AUX_ALLOW_SLEEP)
175 {
176 ui32Reg &= ~AON_WUC_AUXCTL_AUX_FORCE_ON;
177 }
178 else
179 {
180 ui32Reg |= ui32Mode;
181 }
182
183 HWREG(AON_WUC_BASE + AON_WUC_O_AUXCTL) = ui32Reg;
184 }
185
186 //*****************************************************************************
187 //
189 //
190 //*****************************************************************************
191 void
192 AONWUCAuxReset(void)
193 {
194 //
195 // Reset the AUX domain.
196 //
197 HWREG(AON_WUC_BASE + AON_WUC_O_AUXCTL) |= AON_WUC_AUXCTL_RESET_REQ;
198
199 //
200 // Wait for AON interface to be in sync.
201 //
202 HWREG(AON_RTC_BASE + AON_RTC_O_SYNC);
203
204 //
205 // De-assert reset on the AUX domain.
206 //
207 HWREG(AON_WUC_BASE + AON_WUC_O_AUXCTL) &= ~AON_WUC_AUXCTL_RESET_REQ;
208
209 //
210 // Wait for AON interface to be in sync.
211 //
212 HWREG(AON_RTC_BASE + AON_RTC_O_SYNC);
213 }
214
215 //*****************************************************************************
216 //
218 //
219 //*****************************************************************************
220 void
221 AONWUCRechargeCtrlConfigSet(bool bAdaptEnable, uint32_t ui32AdaptRate,
222 uint32_t ui32Period, uint32_t ui32MaxPeriod)
223 {
224 uint32_t ui32Shift;
225 uint32_t ui32C1;
226 uint32_t ui32C2;
227 uint32_t ui32Reg;
228 uint32_t ui32Exponent;
229 uint32_t ui32MaxExponent;
230 uint32_t ui32Mantissa;
231 uint32_t ui32MaxMantissa;
232
233 //
234 // Check the arguments.
235 //
236 ASSERT((ui32AdaptRate >= RC_RATE_MIN) ||
237 (ui32AdaptRate <= RC_RATE_MAX));
238
239 ui32C1 = 0;
240 ui32C2 = 0;
241 ui32Shift = 9;
242
243 //
244 // Clear the previous values.
245 //
246 ui32Reg = HWREG(AON_WUC_BASE + AON_WUC_O_RECHARGECFG);
247 ui32Reg &= ~(AON_WUC_RECHARGECFG_MAX_PER_M_M | AON_WUC_RECHARGECFG_MAX_PER_E_M |
248 AON_WUC_RECHARGECFG_ADAPTIVE_EN_M | AON_WUC_RECHARGECFG_PER_M_M |
249 AON_WUC_RECHARGECFG_PER_E_M | AON_WUC_RECHARGECFG_C1_M |
250 AON_WUC_RECHARGECFG_C2_M);
251
252 //
253 // Check if the recharge controller adaption algorithm should be active.
254 //
255 if(bAdaptEnable)
256 {
257 //
258 // Calculate adaption parameters.
259 //
260 while(ui32AdaptRate)
261 {
262 if(ui32AdaptRate & (1 << ui32Shift))
263 {
264 if(!ui32C1)
265 {
266 ui32C1 = ui32Shift;
267 }
268 else if(!ui32C2)
269 {
270 if((2 * ui32AdaptRate) > ((uint32_t)(3 << ui32Shift)))
271 {
272 ui32C2 = ui32Shift + 1;
273 }
274 else
275 {
276 ui32C2 = ui32Shift;
277 }
278 }
279 else
280 {
281 break;
282 }
283 ui32AdaptRate &= ~(1 << ui32Shift);
284 }
285 ui32Shift--;
286 }
287 if(!ui32C2)
288 {
289 ui32C2 = ui32C1 = ui32C1 - 1;
290 }
291
292 ui32C1 = 10 - ui32C1;
293 ui32C2 = 10 - ui32C2;
294
295 //
296 // Update the recharge rate parameters.
297 //
298 ui32Reg &= ~(AON_WUC_RECHARGECFG_C1_M | AON_WUC_RECHARGECFG_C2_M);
299 ui32Reg |= (ui32C1 << AON_WUC_RECHARGECFG_C1_S) |
300 (ui32C2 << AON_WUC_RECHARGECFG_C2_S) |
301 AON_WUC_RECHARGECFG_ADAPTIVE_EN_M;
302 }
303
304 //
305 // Resolve the period into an exponent and mantissa.
306 //
307 ui32Period = (ui32Period >> 4);
308 ui32Exponent = 0;
309 while(ui32Period > (AON_WUC_RECHARGECFG_PER_M_M >> AON_WUC_RECHARGECFG_PER_M_S))
310 {
311 ui32Period >>= 1;
312 ui32Exponent++;
313 }
314 ui32Mantissa = ui32Period;
315
316 //
317 // Resolve the max period into an exponent and mantissa.
318 //
319 ui32MaxPeriod = (ui32MaxPeriod >> 4);
320 ui32MaxExponent = 0;
321 while(ui32MaxPeriod > (AON_WUC_RECHARGECFG_MAX_PER_M_M >> AON_WUC_RECHARGECFG_MAX_PER_M_S))
322 {
323 ui32MaxPeriod >>= 1;
324 ui32MaxExponent++;
325 }
326 ui32MaxMantissa = ui32MaxPeriod;
327
328 //
329 // Configure the controller.
330 //
331 ui32Reg |= ((ui32MaxMantissa << AON_WUC_RECHARGECFG_MAX_PER_M_S) |
332 (ui32MaxExponent << AON_WUC_RECHARGECFG_MAX_PER_E_S) |
333 (ui32Mantissa << AON_WUC_RECHARGECFG_PER_M_S) |
334 (ui32Exponent << AON_WUC_RECHARGECFG_PER_E_S));
335 HWREG(AON_WUC_BASE + AON_WUC_O_RECHARGECFG) = ui32Reg;
336
337 }
338
339 //*****************************************************************************
340 //
342 //
343 //*****************************************************************************
344 void
345 AONWUCOscConfig(uint32_t ui32Period)
346 {
347 uint32_t ui32Mantissa;
348 uint32_t ui32Exponent;
349 uint32_t ui32Reg;
350
351 //
352 // Resolve the period into a exponent and mantissa.
353 //
354 ui32Period = (ui32Period >> 4);
355 ui32Exponent = 0;
356 while(ui32Period > (AON_WUC_OSCCFG_PER_M_M >> AON_WUC_OSCCFG_PER_M_S))
357 {
358 ui32Period >>= 1;
359 ui32Exponent++;
360 }
361 ui32Mantissa = ui32Period;
362
363 //
364 // Update the period for the oscillator amplitude calibration.
365 //
366 HWREG(AON_WUC_BASE + AON_WUC_O_OSCCFG) =
367 (ui32Mantissa << AON_WUC_OSCCFG_PER_M_S) |
368 (ui32Exponent << AON_WUC_OSCCFG_PER_E_S);
369
370 //
371 // Set the maximum reacharge period equal to the oscillator amplitude
372 // calibration period.
373 //
374 ui32Reg = HWREG(AON_WUC_BASE + AON_WUC_O_RECHARGECFG);
375 ui32Reg &= ~(AON_WUC_RECHARGECFG_MAX_PER_M_M | AON_WUC_RECHARGECFG_MAX_PER_E_M);
376 ui32Reg |= ((ui32Mantissa << AON_WUC_RECHARGECFG_MAX_PER_M_S) |
377 (ui32Exponent << AON_WUC_RECHARGECFG_MAX_PER_E_S));
378
379 //
380 // Write the configuration.
381 //
382 HWREG(AON_WUC_BASE + AON_WUC_O_RECHARGECFG) = ui32Reg;
383 }
AUX_CLOCK_DIV_32
#define AUX_CLOCK_DIV_32
Definition: aon_wuc.h:117
AUX_CLOCK_DIV_2
#define AUX_CLOCK_DIV_2
Definition: aon_wuc.h:113
AONWUCAuxSRamConfig
void AONWUCAuxSRamConfig(uint32_t ui32Retention)
Configure the rentention on the AUX SRAM.
Definition: aon_wuc.c:136
AUX_CLOCK_DIV_16
#define AUX_CLOCK_DIV_16
Definition: aon_wuc.h:116
AONWUCOscConfig
void AONWUCOscConfig(uint32_t ui32Period)
Configure the interval for oscillator amplitude calibration.
Definition: aon_wuc.c:345
ASSERT
#define ASSERT(expr)
Definition: debug.h:65
AONWUCAuxReset
void AONWUCAuxReset(void)
Reset the AUX domain.
Definition: aon_wuc.c:192
AONWUC_CLOCK_SRC_MF
#define AONWUC_CLOCK_SRC_MF
Definition: aon_wuc.h:101
AONWUC_CLOCK_SRC_HF
#define AONWUC_CLOCK_SRC_HF
Definition: aon_wuc.h:99
AONWUC_CLOCK_SRC_LF
#define AONWUC_CLOCK_SRC_LF
Definition: aon_wuc.h:103
AONWUCRechargeCtrlConfigSet
void AONWUCRechargeCtrlConfigSet(bool bAdaptEnable, uint32_t ui32AdaptRate, uint32_t ui32Period, uint32_t ui32MaxPeriod)
Configure the recharge controller.
Definition: aon_wuc.c:221
AONWUC_AUX_ALLOW_SLEEP
#define AONWUC_AUX_ALLOW_SLEEP
Definition: aon_wuc.h:159
AONWUC_AUX_WAKEUP
#define AONWUC_AUX_WAKEUP
Definition: aon_wuc.h:158
AUX_CLOCK_DIV_UNUSED
#define AUX_CLOCK_DIV_UNUSED
Definition: aon_wuc.h:121
AUX_CLOCK_DIV_64
#define AUX_CLOCK_DIV_64
Definition: aon_wuc.h:118
AUX_CLOCK_DIV_8
#define AUX_CLOCK_DIV_8
Definition: aon_wuc.h:115
AONWUCAuxClockConfigSet
void AONWUCAuxClockConfigSet(uint32_t ui32ClkSrc, uint32_t ui32ClkDiv)
Set the clock source for the AUX domain.
Definition: aon_wuc.c:68
RC_RATE_MIN
#define RC_RATE_MIN
Definition: aon_wuc.h:212
AONWUCAuxWakeupEvent
void AONWUCAuxWakeupEvent(uint32_t ui32Mode)
Control the wake up procedure of the AUX domain.
Definition: aon_wuc.c:158
RC_RATE_MAX
#define RC_RATE_MAX
Definition: aon_wuc.h:210
AONWUC_AUX_WAKEUP_SWEVT
#define AONWUC_AUX_WAKEUP_SWEVT
Definition: aon_wuc.h:157
aon_wuc.h
AUX_CLOCK_DIV_4
#define AUX_CLOCK_DIV_4
Definition: aon_wuc.h:114
AUX_CLOCK_DIV_256
#define AUX_CLOCK_DIV_256
Definition: aon_wuc.h:120
AUX_CLOCK_DIV_128
#define AUX_CLOCK_DIV_128
Definition: aon_wuc.h:119