JTAG_TAP;EFUSE
JTAG_TAP;EFUSE;DIE_ID_0
JTAG_TAP;EFUSE;DIE_ID_0;ID_31_0
JTAG_TAP;EFUSE;DIE_ID_1
JTAG_TAP;EFUSE;DIE_ID_1;ID_63_32
JTAG_TAP;EFUSE;DIE_ID_2
JTAG_TAP;EFUSE;DIE_ID_2;ID_95_64
JTAG_TAP;EFUSE;DIE_ID_3
JTAG_TAP;EFUSE;DIE_ID_3;ID_127_96
JTAG_TAP;EFUSE;SCAN_DATA0
JTAG_TAP;EFUSE;SCAN_DATA0;ULL_MCU_RAM1_REP
JTAG_TAP;EFUSE;SCAN_DATA0;ULL_MCU_RAM2_REP
JTAG_TAP;EFUSE;SCAN_DATA0;ULL_MCU_RAM3_REP
JTAG_TAP;EFUSE;SCAN_DATA0;ULL_AUX_RAM_REP
JTAG_TAP;EFUSE;SCAN_DATA0;TAP_DAP_LOCK
JTAG_TAP;EFUSE;SCAN_DATA1
JTAG_TAP;EFUSE;SCAN_DATA1;RESERVED
JTAG_TAP;EFUSE;SCAN_DATA1;ULL_MCU_RAM0_REP
JTAG_TAP;EFUSE;SCAN_DATA1;ULL_MCU_RAM1_REP
JTAG_TAP;EFUSE;SCAN_DATA2_BOOT
JTAG_TAP;EFUSE;SCAN_DATA2_BOOT;FLASH_RDY
JTAG_TAP;EFUSE;SCAN_DATA2_BOOT;STANDBY_MODE_SEL_INT
JTAG_TAP;EFUSE;SCAN_DATA2_BOOT;STANDBY_PW_SEL_INT
JTAG_TAP;EFUSE;SCAN_DATA2_BOOT;DIS_STANDBY_INT
JTAG_TAP;EFUSE;SCAN_DATA2_BOOT;VIN_AT_X_INT
JTAG_TAP;EFUSE;SCAN_DATA2_BOOT;STANDBY_MODE_SEL_EXT
JTAG_TAP;EFUSE;SCAN_DATA2_BOOT;STANDBY_PW_SEL_EXT
JTAG_TAP;EFUSE;SCAN_DATA2_BOOT;DIS_STANDBY_EXT
JTAG_TAP;EFUSE;SCAN_DATA2_BOOT;VIN_AT_X_EXT
JTAG_TAP;EFUSE;SCAN_DATA2_BOOT;RESERVED
JTAG_TAP;EFUSE;SCAN_DATA2_BOOT;CRC
JTAG_TAP;EFUSE;SCAN_DATA2_BOOT;TAP_DAP_LOCK_N
JTAG_TAP;EFUSE;BANK_TRIM_BOOT
JTAG_TAP;EFUSE;BANK_TRIM_BOOT;RESERVED
JTAG_TAP;EFUSE;BANK_TRIM_BOOT;ROM_BOOT
JTAG_TAP;EFUSE;BANK_TRIM_BOOT;TRIM3P4
JTAG_TAP;EFUSE;BANK_TRIM_BOOT;VCG2P5CT
JTAG_TAP;EFUSE;BANK_TRIM_BOOT;VREADCT
JTAG_TAP;EFUSE;BANK_TRIM_BOOT;TRIM_0P8
JTAG_TAP;EFUSE;BANK_TRIM_BOOT;TRIM_SADLY
JTAG_TAP;EFUSE;BANK_TRIM_BOOT;TRIM_NMOS
JTAG_TAP;EFUSE;BANK_TRIM_BOOT;TRIM_PMOS
JTAG_TAP;EFUSE;OSC_BIAS_LDO_TRIM
JTAG_TAP;EFUSE;OSC_BIAS_LDO_TRIM;RESERVED
JTAG_TAP;EFUSE;OSC_BIAS_LDO_TRIM;SET_RCOSC_HF_COARSE_RESISTOR
JTAG_TAP;EFUSE;OSC_BIAS_LDO_TRIM;TRIMMAG
JTAG_TAP;EFUSE;OSC_BIAS_LDO_TRIM;TRIMIREF
JTAG_TAP;EFUSE;OSC_BIAS_LDO_TRIM;ITRIM_DIG_LDO
JTAG_TAP;EFUSE;OSC_BIAS_LDO_TRIM;VTRIM_DIG
JTAG_TAP;EFUSE;OSC_BIAS_LDO_TRIM;VTRIM_COARSE
JTAG_TAP;EFUSE;OSC_BIAS_LDO_TRIM;RCOSCHF_CTRIM
JTAG_TAP;EFUSE;ANA_TRIM
JTAG_TAP;EFUSE;ANA_TRIM;RESERVED
JTAG_TAP;EFUSE;ANA_TRIM;BOD_BANDGAP_TRIM_CNF
JTAG_TAP;EFUSE;ANA_TRIM;VDDR_ENABLE_PG1
JTAG_TAP;EFUSE;ANA_TRIM;VDDR_OK_HYS
JTAG_TAP;EFUSE;ANA_TRIM;IPTAT_TRIM
JTAG_TAP;EFUSE;ANA_TRIM;VDDR_TRIM
JTAG_TAP;EFUSE;ANA_TRIM;TRIMBOD_INTMODE
JTAG_TAP;EFUSE;ANA_TRIM;TRIMBOD_EXTMODE
JTAG_TAP;EFUSE;ANA_TRIM;TRIMTEMP
JTAG_TAP;PRCM
JTAG_TAP;PRCM;CLK_OVR
JTAG_TAP;PRCM;CLK_OVR;CLK_SYSBUS
JTAG_TAP;PRCM;CLK_OVR;CLK_CPUFREE
JTAG_TAP;PRCM;CLK_OVR;CLK_CPUCORE
JTAG_TAP;PRCM;RESET_OVR
JTAG_TAP;PRCM;RESET_OVR;RESET_SYSBUS_N
JTAG_TAP;PRCM;RESET_OVR;SPARE
JTAG_TAP;PRCM;RESET_OVR;RESET_CPUCORE_N
JTAG_TAP;PRCM;POWER_OVR
JTAG_TAP;PRCM;POWER_OVR;POWER_ON_ALL
JTAG_TAP;PRCM;POWER_OVR;CPU
JTAG_TAP;PRCM;POWER_OVR;BUS
JTAG_TAP;PRCM;OBS_CLK
JTAG_TAP;PRCM;OBS_CLK;OBS_CLK_I2S
JTAG_TAP;PRCM;OBS_CLK;OBS_CLK_SSI_1
JTAG_TAP;PRCM;OBS_CLK;OBS_CLK_SSI_0
JTAG_TAP;PRCM;OBS_CLK;OBS_CLK_UART_1
JTAG_TAP;PRCM;OBS_CLK;OBS_CLK_UART_0
JTAG_TAP;PRCM;OBS_CLK;OBS_CLK_I2C_1
JTAG_TAP;PRCM;OBS_CLK;OBS_CLK_I2C_0
JTAG_TAP;PRCM;OBS_CLK;OBS_CLK_SSI_DMA_1
JTAG_TAP;PRCM;OBS_CLK;OBS_CLK_UART_DMA
JTAG_TAP;PRCM;OBS_CLK;OBS_CLK_GPTM_3
JTAG_TAP;PRCM;OBS_CLK;OBS_CLK_GPTM_2
JTAG_TAP;PRCM;OBS_CLK;OBS_CLK_GPTM_1
JTAG_TAP;PRCM;OBS_CLK;OBS_CLK_GPTM_0
JTAG_TAP;PRCM;OBS_CLK;OBS_CLK_GPIO
JTAG_TAP;PRCM;OBS_CLK;OBS_CLK_DMA
JTAG_TAP;PRCM;OBS_CLK;OBS_CLK_TRNG
JTAG_TAP;PRCM;OBS_CLK;OBS_CLK_SEC
JTAG_TAP;PRCM;OBS_CLK;OBS_CLK_PERBUSCPU
JTAG_TAP;PRCM;OBS_CLK;OBS_CLK_CPUCORE
JTAG_TAP;PRCM;OBS_CLK;OBS_CLK_CPUFREE
JTAG_TAP;PRCM;OBS_CLK;OBS_CLK_SYSBUS
JTAG_TAP;PRCM;OBS_CLK;OBS_CLK_FLASH
JTAG_TAP;PRCM;OBS_CLK;OBS_CLK_RFCORE
JTAG_TAP;PRCM;OBS_CLK;OBS_CLK_PERBUSULL
JTAG_TAP;PRCM;OBS_RESET
JTAG_TAP;PRCM;OBS_RESET;OBS_RESET_I2S_N
JTAG_TAP;PRCM;OBS_RESET;OBS_RESET_SSI_N_1
JTAG_TAP;PRCM;OBS_RESET;OBS_RESET_SSI_N_0
JTAG_TAP;PRCM;OBS_RESET;OBS_RESET_UART_N_1
JTAG_TAP;PRCM;OBS_RESET;OBS_RESET_UART_N_0
JTAG_TAP;PRCM;OBS_RESET;OBS_RESET_I2C_N_1
JTAG_TAP;PRCM;OBS_RESET;OBS_RESET_I2C_N_0
JTAG_TAP;PRCM;OBS_RESET;OBS_RESET_PERDMA_N
JTAG_TAP;PRCM;OBS_RESET;OBS_RESET_PERBUSDMA_N
JTAG_TAP;PRCM;OBS_RESET;OBS_RESET_GPTM_N_3
JTAG_TAP;PRCM;OBS_RESET;OBS_RESET_GPTM_N_2
JTAG_TAP;PRCM;OBS_RESET;OBS_RESET_GPTM_N_1
JTAG_TAP;PRCM;OBS_RESET;OBS_RESET_GPTM_N_0
JTAG_TAP;PRCM;OBS_RESET;OBS_RESET_GPIO_N
JTAG_TAP;PRCM;OBS_RESET;OBS_RESET_DMA_N
JTAG_TAP;PRCM;OBS_RESET;OBS_RESET_TRNG_N
JTAG_TAP;PRCM;OBS_RESET;OBS_RESET_SEC_N
JTAG_TAP;PRCM;OBS_RESET;OBS_RESET_PERBUSCPU_N
JTAG_TAP;PRCM;OBS_RESET;OBS_RESET_CPUCORE_N
JTAG_TAP;PRCM;OBS_RESET;OBS_RESET_CPUFREE_N
JTAG_TAP;PRCM;OBS_RESET;OBS_RESET_SYSBUS_N
JTAG_TAP;PRCM;OBS_RESET;OBS_RESET_FLASH_N
JTAG_TAP;PRCM;OBS_RESET;OBS_RESET_RFCORE_N
JTAG_TAP;PRCM;OBS_RESET;OBS_RESET_PERBUSULL_N
JTAG_TAP;PRCM;OBS_POWER
JTAG_TAP;PRCM;OBS_POWER;OBS_RFCORE
JTAG_TAP;PRCM;OBS_POWER;OBS_SERIAL
JTAG_TAP;PRCM;OBS_POWER;OBS_PERIPH
JTAG_TAP;PRCM;OBS_POWER;SPARE
JTAG_TAP;PRCM;OBS_POWER;OBS_CPU
JTAG_TAP;PRCM;OBS_POWER;OBS_VIMS
JTAG_TAP;PRCM;OBS_POWER;OBS_BUS
JTAG_TAP;PRCM;OBS_POWER;OBS_CLKCTRL
JTAG_TAP;TEST
JTAG_TAP;TEST;DOM_ENBL0
JTAG_TAP;TEST;DOM_ENBL0;DOM_ENBL_0_89
JTAG_TAP;TEST;DOM_ENBL0;DOM_ENBL_0_88
JTAG_TAP;TEST;DOM_ENBL0;DOM_ENBL_0_87
JTAG_TAP;TEST;DOM_ENBL0;DOM_ENBL_0_86
JTAG_TAP;TEST;DOM_ENBL0;DOM_ENBL_0_85
JTAG_TAP;TEST;DOM_ENBL0;DOM_ENBL_0_84
JTAG_TAP;TEST;DOM_ENBL0;DOM_ENBL_0_83
JTAG_TAP;TEST;DOM_ENBL0;DOM_ENBL_0_82
JTAG_TAP;TEST;DOM_ENBL0;DOM_ENBL_0_81
JTAG_TAP;TEST;DOM_ENBL0;DOM_ENBL_0_80
JTAG_TAP;TEST;DOM_ENBL0;DOM_ENBL_0_79
JTAG_TAP;TEST;DOM_ENBL0;DOM_ENBL_0_78
JTAG_TAP;TEST;DOM_ENBL0;DOM_ENBL_0_77
JTAG_TAP;TEST;DOM_ENBL0;DOM_ENBL_0_76
JTAG_TAP;TEST;DOM_ENBL0;DOM_ENBL_0_75
JTAG_TAP;TEST;DOM_ENBL0;DOM_ENBL_0_74
JTAG_TAP;TEST;DOM_ENBL0;DOM_ENBL_0_73
JTAG_TAP;TEST;DOM_ENBL0;DOM_ENBL_0_72
JTAG_TAP;TEST;DOM_ENBL0;DOM_ENBL_0_71
JTAG_TAP;TEST;DOM_ENBL0;DOM_ENBL_0_70
JTAG_TAP;TEST;DOM_ENBL0;DOM_ENBL_0_69
JTAG_TAP;TEST;DOM_ENBL0;DOM_ENBL_0_68
JTAG_TAP;TEST;DOM_ENBL0;DOM_ENBL_0_67
JTAG_TAP;TEST;DOM_ENBL0;DOM_ENBL_0_66
JTAG_TAP;TEST;DOM_ENBL0;DOM_ENBL_0_65
JTAG_TAP;TEST;DOM_ENBL0;DOM_ENBL_0_64
JTAG_TAP;TEST;DOM_ENBL0;DOM_ENBL_0_63
JTAG_TAP;TEST;DOM_ENBL0;DOM_ENBL_0_62
JTAG_TAP;TEST;DOM_ENBL0;DOM_ENBL_0_61
JTAG_TAP;TEST;DOM_ENBL0;DOM_ENBL_0_60
JTAG_TAP;TEST;DOM_ENBL0;DOM_ENBL_0_59
JTAG_TAP;TEST;DOM_ENBL0;DOM_ENBL_0_58
JTAG_TAP;TEST;DOM_ENBL0;DOM_ENBL_0_57
JTAG_TAP;TEST;DOM_ENBL0;DOM_ENBL_0_56
JTAG_TAP;TEST;DOM_ENBL0;DOM_ENBL_0_55
JTAG_TAP;TEST;DOM_ENBL0;DOM_ENBL_0_54
JTAG_TAP;TEST;DOM_ENBL0;DOM_ENBL_0_53
JTAG_TAP;TEST;DOM_ENBL0;DOM_ENBL_0_52
JTAG_TAP;TEST;DOM_ENBL0;DOM_ENBL_0_51
JTAG_TAP;TEST;DOM_ENBL0;DOM_ENBL_0_50
JTAG_TAP;TEST;DOM_ENBL0;DOM_ENBL_0_49
JTAG_TAP;TEST;DOM_ENBL0;DOM_ENBL_0_48
JTAG_TAP;TEST;DOM_ENBL0;DOM_ENBL_0_47
JTAG_TAP;TEST;DOM_ENBL0;DOM_ENBL_0_46
JTAG_TAP;TEST;DOM_ENBL0;DOM_ENBL_0_45
JTAG_TAP;TEST;DOM_ENBL0;DOM_ENBL_0_44
JTAG_TAP;TEST;DOM_ENBL0;DOM_ENBL_0_43
JTAG_TAP;TEST;DOM_ENBL0;DOM_ENBL_0_42
JTAG_TAP;TEST;DOM_ENBL0;DOM_ENBL_0_41
JTAG_TAP;TEST;DOM_ENBL0;DOM_ENBL_0_40
JTAG_TAP;TEST;DOM_ENBL0;DOM_ENBL_0_39
JTAG_TAP;TEST;DOM_ENBL0;DOM_ENBL_0_38
JTAG_TAP;TEST;DOM_ENBL0;DOM_ENBL_0_37
JTAG_TAP;TEST;DOM_ENBL0;DOM_ENBL_0_36
JTAG_TAP;TEST;DOM_ENBL0;DOM_ENBL_0_35
JTAG_TAP;TEST;DOM_ENBL0;DOM_ENBL_0_34
JTAG_TAP;TEST;DOM_ENBL0;DOM_ENBL_0_33
JTAG_TAP;TEST;DOM_ENBL0;DOM_ENBL_0_32
JTAG_TAP;TEST;DOM_ENBL0;DOM_ENBL_0_31
JTAG_TAP;TEST;DOM_ENBL0;DOM_ENBL_0_30
JTAG_TAP;TEST;DOM_ENBL0;DOM_ENBL_0_29
JTAG_TAP;TEST;DOM_ENBL0;DOM_ENBL_0_28
JTAG_TAP;TEST;DOM_ENBL0;DOM_ENBL_0_27
JTAG_TAP;TEST;DOM_ENBL0;DOM_ENBL_0_26
JTAG_TAP;TEST;DOM_ENBL0;DOM_ENBL_0_25
JTAG_TAP;TEST;DOM_ENBL0;DOM_ENBL_0_24
JTAG_TAP;TEST;DOM_ENBL0;DOM_ENBL_0_23
JTAG_TAP;TEST;DOM_ENBL0;DOM_ENBL_0_22
JTAG_TAP;TEST;DOM_ENBL0;DOM_ENBL_0_21
JTAG_TAP;TEST;DOM_ENBL0;DOM_ENBL_0_20
JTAG_TAP;TEST;DOM_ENBL0;DOM_ENBL_0_19
JTAG_TAP;TEST;DOM_ENBL0;DOM_ENBL_0_18
JTAG_TAP;TEST;DOM_ENBL0;DOM_ENBL_0_17
JTAG_TAP;TEST;DOM_ENBL0;DOM_ENBL_0_16
JTAG_TAP;TEST;DOM_ENBL0;DOM_ENBL_0_15
JTAG_TAP;TEST;DOM_ENBL0;DOM_ENBL_0_14
JTAG_TAP;TEST;DOM_ENBL0;DOM_ENBL_0_13
JTAG_TAP;TEST;DOM_ENBL0;DOM_ENBL_0_12
JTAG_TAP;TEST;DOM_ENBL0;DOM_ENBL_0_11
JTAG_TAP;TEST;DOM_ENBL0;DOM_ENBL_0_10
JTAG_TAP;TEST;DOM_ENBL0;DOM_ENBL_0_9
JTAG_TAP;TEST;DOM_ENBL0;DOM_ENBL_0_8
JTAG_TAP;TEST;DOM_ENBL0;DOM_ENBL_0_7
JTAG_TAP;TEST;DOM_ENBL0;DOM_ENBL_0_6
JTAG_TAP;TEST;DOM_ENBL0;DOM_ENBL_0_5
JTAG_TAP;TEST;DOM_ENBL0;DOM_ENBL_0_4
JTAG_TAP;TEST;DOM_ENBL0;DOM_ENBL_0_3
JTAG_TAP;TEST;DOM_ENBL0;DOM_ENBL_0_2
JTAG_TAP;TEST;DOM_ENBL0;DOM_ENBL_0_1
JTAG_TAP;TEST;DOM_ENBL0;DOM_ENBL_0_0
JTAG_TAP;TEST;DOM_ENBL1
JTAG_TAP;TEST;DOM_ENBL1;DOM_ENBL_1_89
JTAG_TAP;TEST;DOM_ENBL1;DOM_ENBL_1_88
JTAG_TAP;TEST;DOM_ENBL1;DOM_ENBL_1_87
JTAG_TAP;TEST;DOM_ENBL1;DOM_ENBL_1_86
JTAG_TAP;TEST;DOM_ENBL1;DOM_ENBL_1_85
JTAG_TAP;TEST;DOM_ENBL1;DOM_ENBL_1_84
JTAG_TAP;TEST;DOM_ENBL1;DOM_ENBL_1_83
JTAG_TAP;TEST;DOM_ENBL1;DOM_ENBL_1_82
JTAG_TAP;TEST;DOM_ENBL1;DOM_ENBL_1_81
JTAG_TAP;TEST;DOM_ENBL1;DOM_ENBL_1_80
JTAG_TAP;TEST;DOM_ENBL1;DOM_ENBL_1_79
JTAG_TAP;TEST;DOM_ENBL1;DOM_ENBL_1_78
JTAG_TAP;TEST;DOM_ENBL1;DOM_ENBL_1_77
JTAG_TAP;TEST;DOM_ENBL1;DOM_ENBL_1_76
JTAG_TAP;TEST;DOM_ENBL1;DOM_ENBL_1_75
JTAG_TAP;TEST;DOM_ENBL1;DOM_ENBL_1_74
JTAG_TAP;TEST;DOM_ENBL1;DOM_ENBL_1_73
JTAG_TAP;TEST;DOM_ENBL1;DOM_ENBL_1_72
JTAG_TAP;TEST;DOM_ENBL1;DOM_ENBL_1_71
JTAG_TAP;TEST;DOM_ENBL1;DOM_ENBL_1_70
JTAG_TAP;TEST;DOM_ENBL1;DOM_ENBL_1_69
JTAG_TAP;TEST;DOM_ENBL1;DOM_ENBL_1_68
JTAG_TAP;TEST;DOM_ENBL1;DOM_ENBL_1_67
JTAG_TAP;TEST;DOM_ENBL1;DOM_ENBL_1_66
JTAG_TAP;TEST;DOM_ENBL1;DOM_ENBL_1_65
JTAG_TAP;TEST;DOM_ENBL1;DOM_ENBL_1_64
JTAG_TAP;TEST;DOM_ENBL1;DOM_ENBL_1_63
JTAG_TAP;TEST;DOM_ENBL1;DOM_ENBL_1_62
JTAG_TAP;TEST;DOM_ENBL1;DOM_ENBL_1_61
JTAG_TAP;TEST;DOM_ENBL1;DOM_ENBL_1_60
JTAG_TAP;TEST;DOM_ENBL1;DOM_ENBL_1_59
JTAG_TAP;TEST;DOM_ENBL1;DOM_ENBL_1_58
JTAG_TAP;TEST;DOM_ENBL1;DOM_ENBL_1_57
JTAG_TAP;TEST;DOM_ENBL1;DOM_ENBL_1_56
JTAG_TAP;TEST;DOM_ENBL1;DOM_ENBL_1_55
JTAG_TAP;TEST;DOM_ENBL1;DOM_ENBL_1_54
JTAG_TAP;TEST;DOM_ENBL1;DOM_ENBL_1_53
JTAG_TAP;TEST;DOM_ENBL1;DOM_ENBL_1_52
JTAG_TAP;TEST;DOM_ENBL1;DOM_ENBL_1_51
JTAG_TAP;TEST;DOM_ENBL1;DOM_ENBL_1_50
JTAG_TAP;TEST;DOM_ENBL1;DOM_ENBL_1_49
JTAG_TAP;TEST;DOM_ENBL1;DOM_ENBL_1_48
JTAG_TAP;TEST;DOM_ENBL1;DOM_ENBL_1_47
JTAG_TAP;TEST;DOM_ENBL1;DOM_ENBL_1_46
JTAG_TAP;TEST;DOM_ENBL1;DOM_ENBL_1_45
JTAG_TAP;TEST;DOM_ENBL1;DOM_ENBL_1_44
JTAG_TAP;TEST;DOM_ENBL1;DOM_ENBL_1_43
JTAG_TAP;TEST;DOM_ENBL1;DOM_ENBL_1_42
JTAG_TAP;TEST;DOM_ENBL1;DOM_ENBL_1_41
JTAG_TAP;TEST;DOM_ENBL1;DOM_ENBL_1_40
JTAG_TAP;TEST;DOM_ENBL1;DOM_ENBL_1_39
JTAG_TAP;TEST;DOM_ENBL1;DOM_ENBL_1_38
JTAG_TAP;TEST;DOM_ENBL1;DOM_ENBL_1_37
JTAG_TAP;TEST;DOM_ENBL1;DOM_ENBL_1_36
JTAG_TAP;TEST;DOM_ENBL1;DOM_ENBL_1_35
JTAG_TAP;TEST;DOM_ENBL1;DOM_ENBL_1_34
JTAG_TAP;TEST;DOM_ENBL1;DOM_ENBL_1_33
JTAG_TAP;TEST;DOM_ENBL1;DOM_ENBL_1_32
JTAG_TAP;TEST;DOM_ENBL1;DOM_ENBL_1_31
JTAG_TAP;TEST;DOM_ENBL1;DOM_ENBL_1_30
JTAG_TAP;TEST;DOM_ENBL1;DOM_ENBL_1_29
JTAG_TAP;TEST;DOM_ENBL1;DOM_ENBL_1_28
JTAG_TAP;TEST;DOM_ENBL1;DOM_ENBL_1_27
JTAG_TAP;TEST;DOM_ENBL1;DOM_ENBL_1_26
JTAG_TAP;TEST;DOM_ENBL1;DOM_ENBL_1_25
JTAG_TAP;TEST;DOM_ENBL1;DOM_ENBL_1_24
JTAG_TAP;TEST;DOM_ENBL1;DOM_ENBL_1_23
JTAG_TAP;TEST;DOM_ENBL1;DOM_ENBL_1_22
JTAG_TAP;TEST;DOM_ENBL1;DOM_ENBL_1_21
JTAG_TAP;TEST;DOM_ENBL1;DOM_ENBL_1_20
JTAG_TAP;TEST;DOM_ENBL1;DOM_ENBL_1_19
JTAG_TAP;TEST;DOM_ENBL1;DOM_ENBL_1_18
JTAG_TAP;TEST;DOM_ENBL1;DOM_ENBL_1_17
JTAG_TAP;TEST;DOM_ENBL1;DOM_ENBL_1_16
JTAG_TAP;TEST;DOM_ENBL1;DOM_ENBL_1_15
JTAG_TAP;TEST;DOM_ENBL1;DOM_ENBL_1_14
JTAG_TAP;TEST;DOM_ENBL1;DOM_ENBL_1_13
JTAG_TAP;TEST;DOM_ENBL1;DOM_ENBL_1_12
JTAG_TAP;TEST;DOM_ENBL1;DOM_ENBL_1_11
JTAG_TAP;TEST;DOM_ENBL1;DOM_ENBL_1_10
JTAG_TAP;TEST;DOM_ENBL1;DOM_ENBL_1_9
JTAG_TAP;TEST;DOM_ENBL1;DOM_ENBL_1_8
JTAG_TAP;TEST;DOM_ENBL1;DOM_ENBL_1_7
JTAG_TAP;TEST;DOM_ENBL1;DOM_ENBL_1_6
JTAG_TAP;TEST;DOM_ENBL1;DOM_ENBL_1_5
JTAG_TAP;TEST;DOM_ENBL1;DOM_ENBL_1_4
JTAG_TAP;TEST;DOM_ENBL1;DOM_ENBL_1_3
JTAG_TAP;TEST;DOM_ENBL1;DOM_ENBL_1_2
JTAG_TAP;TEST;DOM_ENBL1;DOM_ENBL_1_1
JTAG_TAP;TEST;DOM_ENBL1;DOM_ENBL_1_0
JTAG_TAP;TEST;SCAN
JTAG_TAP;TEST;SCAN;SLDO_BYPASS_EN
JTAG_TAP;TEST;SCAN;VDD_BYPASS_EN
JTAG_TAP;TEST;SCAN;MCU_PSCON_SPARE
JTAG_TAP;TEST;SCAN;MCU_PSCON_AONONLY_SEL
JTAG_TAP;TEST;SCAN;MCU_PSCON_TSTCLK_BYPASS
JTAG_TAP;TEST;SCAN;MCU_PSCON_BLOCKOUT
JTAG_TAP;TEST;SCAN;MCU_PSCON_MODE
JTAG_TAP;TEST;SCAN;MCU_PSCON_MCUTM_SEL
JTAG_TAP;TEST;SCAN;SPARE
JTAG_TAP;TEST;SCAN;TEST_TAP_CLK_MX_SEL
JTAG_TAP;TEST;SCAN;PACKAGED_DEVIC
JTAG_TAP;TEST;SCAN;BURNIN_MODE
JTAG_TAP;TEST;SCAN;IO_FLASH_IDDQ_MODE
JTAG_TAP;TEST;SCAN;LCG_BROADCAST_EN
JTAG_TAP;TEST;SCAN;DTCTESTSIGDFT_ISO_LATCH_OVERRIDE
JTAG_TAP;TEST;SCAN;DTCTESTSIGDFT_ISO_EN_OVERRIDE
JTAG_TAP;TEST;SCAN;ISOTESTMODE
JTAG_TAP;TEST;SCAN;SHAPER_ON
JTAG_TAP;TEST;SCAN;SHAPER_CLK_EN
JTAG_TAP;TEST;SCAN;TEST_EVENT_CTRL
JTAG_TAP;TEST;SCAN;TEST_LATCH_EN
JTAG_TAP;TEST;SCAN;TEST_CLK_BYPASS
JTAG_TAP;TEST;SCAN;TFTMODE
JTAG_TAP;TEST;SCAN;DTCTESTSIGPCG_EN
JTAG_TAP;TEST;SCAN;CLKINVDIS
JTAG_TAP;TEST;SCAN;RCG_EN
JTAG_TAP;TEST;SCAN;LCG_CTRL_EN_N
JTAG_TAP;TEST;SCAN;DFT_RST_BYPASS
JTAG_TAP;TEST;DFTMODE
JTAG_TAP;TEST;DFTMODE;SPARE
JTAG_TAP;TEST;DFTMODE;ONE_HOT_CLUSTER_LCG_DOMAIN_EN_MODE
JTAG_TAP;TEST;DFTMODE;MR_DR
JTAG_TAP;TEST;DFTMODE;MARGIN_MODE_OVRD
JTAG_TAP;TEST;DFTMODE;GLG_VDDAR_VDD_SW
JTAG_TAP;TEST;DFTMODE;PBIST_MODE
JTAG_TAP;TEST;DFTMODE;GXG_DFT_MODE
JTAG_TAP;TEST;DFTMODE;GLX_DFT_MODE
JTAG_TAP;TEST;DFTMODE;GLG_DFT_MODE
JTAG_TAP;TEST;DFTMODE;GLG_VDDAR_SW
JTAG_TAP;TEST;DFTMODE;GLGULL_VDDAR_VDD_SW
JTAG_TAP;TEST;DFTMODE;PBIST_COMBINER_SEL
JTAG_TAP;TEST;DFTMODE;PBIST_DATALOG_EN
JTAG_TAP;TEST;DFTMODE;COMPMODE
JTAG_TAP;TEST;DFTMODE;ATPG_MODE
JTAG_TAP;TEST;SPARE
JTAG_TAP;TEST;SPARE;DTC_DTC_SIGNAL_SPARE25
JTAG_TAP;TEST;SPARE;DTC_TEST_SIGNAL_SPARE
JTAG_TAP;TEST;SPARE;PARTIAL_SCAN_SPARE
JTAG_TAP;TEST;SPARE;PARTIAL_SCAN_FLASH
JTAG_TAP;TEST;SPARE;RARTIAL_SCAN_RAM_ROM
JTAG_TAP;TEST;SPARE;PARTIAL_SCAN_DLO_DTX
JTAG_TAP;TEST;SPARE;PARTIAL_SCAN_OSCDIG_DCDC_ADC
JTAG_TAP;TEST;SPARE;PARTIAL_SCAN_ADI3_ADI4
JTAG_TAP;TEST;SPARE;PARTIAL_SCAN_ADI1
JTAG_TAP;TEST;SPARE;PARTIAL_SCAN_ADI0_ADI2
JTAG_TAP;TEST;SPARE;DTC_DTC_SIGNAL_SPARE
JTAG_TAP;TEST;SPARE;DTC_DTC_SIGNAL_T2C_DFT_RETENTION
JTAG_TAP;TEST;SPARE;DTC_DTC_SIGNAL_DFT_ISO_LATCH_OVERRIDE
JTAG_TAP;TEST;SPARE;DTC_DTC_SIGNAL_DFT_ISO_EN_OVERRIDE
JTAG_TAP;TEST;SPARE;T2C_VDDAR_SW_OVERRIDE
JTAG_TAP;TEST;SPARE;EFC_EFCCLK_CLKINEN_
JTAG_TAP;TEST;SPARE;DEBUGSS_CLK_BYPASS
JTAG_TAP;TEST;SPARE;DEBUGSS_PCG_EN
JTAG_TAP;TEST;SPARE;DEBUGSS_RCG_EN
JTAG_TAP;TEST;SPARE;DTC_DTC_SIGNAL_PCG_EN
JTAG_TAP;TEST;SPARE;DTC_DTC_SIGNAL_ISOOVERRIDE_MEM
JTAG_TAP;TEST;SPARE;DTC_DTC_SIGNAL_ISOOVERRIDE
JTAG_TAP;TEST;SPARE;DTC_DTC_SIGNAL_DFT_RST_N
JTAG_TAP;TEST;SPARE;DTC_TEST_SIGNAL_ISOOVERRIDE_MEM
JTAG_TAP;TEST;SPARE;DTC_TEST_SIGNAL_ISOOVERRIDE
JTAG_TAP;TEST;SPARE;SPARE0
JTAG_TAP;TEST;TRNG_CTL
JTAG_TAP;TEST;TRNG_CTL;GONOGOEN
JTAG_TAP;TEST;TRNG_CTL;GONOGORESETN
JTAG_TAP;TEST;TRNG_CTL;TST_FRO_DELAY
JTAG_TAP;TEST;TRNG_CTL;TST_FRO_ENABLE
JTAG_TAP;TEST;TRNG_CTL;TST_FRO_SELECT
JTAG_TAP;TEST;TRNG_CTL;TESTOSC
JTAG_TAP;TEST;TRNG_CTL;TST_FRO_CTRL_EN
JTAG_TAP;TEST;TRNG_OBS
JTAG_TAP;TEST;TRNG_OBS;GONOGO
JTAG_TAP;TEST;TRNG_OBS;SPARE0
JTAG_TAP;TEST;SPAREIRDR
JTAG_TAP;TEST;SPAREIRDR;TITAN_SPARE
JTAG_TAP;TEST;TEST_CTL
JTAG_TAP;TEST;TEST_CTL;SPARE
JTAG_TAP;TEST;TEST_CTL;TITAN_SCAN_PIPE_BYPASS_EN_DR
JTAG_TAP;TEST;TEST_CTL;TITAN_IODFT_EN_STICKY_ERROR
JTAG_TAP;TEST;TEST_CTL;TITAN_IODFT_GZ
JTAG_TAP;TEST;TEST_CTL;TITAN_BURNIN_MODE_DR
JTAG_TAP;TEST;TEST_CTL;TITAN_INTRL_SCAN_EN_DR
JTAG_TAP;TEST;TEST_CTL;TITAN_JTAG_IO_BYPASS_EN_DR
JTAG_TAP;TEST;TEST_CTL;IO_LBEN
JTAG_TAP;TEST;TEST_CTL;IO_LATCHCTRL
JTAG_TAP;TEST;TEST_CTL;TITAN_IO_TESTMODE
JTAG_TAP;TEST;TEST_CTL;TITAN_IODFT_ERR_OUT_SEL_DR
JTAG_TAP;TEST;TEST_CTL;TITAN_EXTRNL_SCAN_EN_DR
JTAG_TAP;TEST;TEST_CTL;TITAN_IODFT_MODE_DR
JTAG_TAP;TEST;TEST_CTL;TITAN_PBIST_MODE_DR
JTAG_TAP;TEST;TEST_CTL;TITAN_ESTAC_SRL_MODE_DR
JTAG_TAP;TEST;TEST_CTL;TITAN_ATPG_MODE_DR
JTAG_TAP;TEST;TEST_CTL;CNTRL
JTAG_TAP;TEST;IODFT_MASK
JTAG_TAP;TEST;IODFT_MASK;TITAN_IODFT_MASK_DR
JTAG_TAP;TEST;INTRL_SE_CTL
JTAG_TAP;TEST;INTRL_SE_CTL;SPARE
JTAG_TAP;TEST;INTRL_SE_CTL;TITAN_CAPT_CNT_DR
JTAG_TAP;TEST;INTRL_SE_CTL;TITAN_SCAN_CAPT_OFFSET_DR
JTAG_TAP;TEST;INTRL_SE_CTL;BYTEFILL
JTAG_TAP;TEST;INTRL_SE_CTL;TITAN_SCAN_OFF_CNT_DR
JTAG_TAP;TEST;INTRL_SE_CTL;TITAN_SCAN_ON_CNT_DR
JTAG_TAP;TEST;SCAN_CHNL
JTAG_TAP;TEST;SCAN_CHNL;MCU_ATPG_SO7
JTAG_TAP;TEST;SCAN_CHNL;TEST_TAP_TDI9
JTAG_TAP;TEST;ODPCTL
JTAG_TAP;TEST;ODPCTL;SENSE_ENABLE_2
JTAG_TAP;TEST;ODPCTL;SENSE_ENABLE_1
JTAG_TAP;TEST;ODPCTL;SENSE_ENABLE_0
JTAG_TAP;TEST;ODPCTL;GATE_DRIVE_ENABLE
JTAG_TAP;TEST;ODPCTL;XTR_TYPE
JTAG_TAP;TEST;ODPCTL;DUT_ENABLE
JTAG_TAP;TEST;ODPCTL;SELECT
JTAG_TAP;TEST;ESTAC_INSTR_EN
JTAG_TAP;TEST;ESTAC_INSTR_EN;ESTAC_SO
JTAG_TAP;TEST;ESTAC_INSTR_EN;TEST_TAP_TDI12
JTAG_TAP;AON
JTAG_TAP;AON;SECURITY_OBS
JTAG_TAP;AON;SECURITY_OBS;RES7
JTAG_TAP;AON;SECURITY_OBS;RES6
JTAG_TAP;AON;SECURITY_OBS;RES5
JTAG_TAP;AON;SECURITY_OBS;RES4
JTAG_TAP;AON;SECURITY_OBS;RES3
JTAG_TAP;AON;SECURITY_OBS;RES2
JTAG_TAP;AON;SECURITY_OBS;RES1
JTAG_TAP;AON;SECURITY_OBS;BDACK
JTAG_TAP;AON;SECURITY_CTRL
JTAG_TAP;AON;SECURITY_CTRL;RES7
JTAG_TAP;AON;SECURITY_CTRL;RES6
JTAG_TAP;AON;SECURITY_CTRL;MCU_RESET_REQ
JTAG_TAP;AON;SECURITY_CTRL;AUX_RESET_REQ
JTAG_TAP;AON;SECURITY_CTRL;BDRDY
JTAG_TAP;AON;SECURITY_CTRL;BDDAT
JTAG_TAP;AON;SECURITY_CTRL;TOTALERASE
JTAG_TAP;AON;SECURITY_CTRL;CHIPERASE
JTAG_TAP;AON;SYSCTRL
JTAG_TAP;AON;SYSCTRL;WR_EVENT_O_VAL
JTAG_TAP;AON;SYSCTRL;DEBUG_EN_CLR_VAL
JTAG_TAP;AON;SYSCTRL;DEBUG_EN_SET_VAL
JTAG_TAP;AON;SYSCTRL;SCLK_HF_EN_O_VAL
JTAG_TAP;AON;SYSCTRL;SYSCTRLPD_O_VAL
JTAG_TAP;AON;SYSCTRL;CLK_ADC_EN_O_VAL
JTAG_TAP;AON;SYSCTRL;CLK_CHP_EN_O_VAL
JTAG_TAP;AON;SYSCTRL;FORCE_RCOSC_HF_O_VAL
JTAG_TAP;AON;SYSCTRL;CLK_DCDC_EN_O_VAL
JTAG_TAP;AON;SYSCTRL;RESET_VDDSZ_EN_O_VAL
JTAG_TAP;AON;SYSCTRL;PAD_RING_SLEEP_N_O_VAL
JTAG_TAP;AON;SYSCTRL;SHUTDOWN_O_VAL
JTAG_TAP;AON;SYSCTRL;BYPASS_OSCDIG_VAL
JTAG_TAP;AON;SYSCTRL;VDD_BOD_EN_O_VAL
JTAG_TAP;AON;SYSCTRL;VREF_SH_O_VAL
JTAG_TAP;AON;SYSCTRL;VREF_TRIM_EN_O_VAL
JTAG_TAP;AON;SYSCTRL;DIG_LDO_PRESLEEP_O_VAL
JTAG_TAP;AON;SYSCTRL;VDD_LDO_EN_O_VAL
JTAG_TAP;AON;SYSCTRL;SLEEP_MODE_EN_O_VAL
JTAG_TAP;AON;SYSCTRL;DCDC_EN_O_VAL
JTAG_TAP;AON;SYSCTRL;VDDR_REG_EN_O_VAL
JTAG_TAP;AON;SYSCTRL;GBIAS_EN_O_VAL
JTAG_TAP;AON;SYSCTRL;BGAP_EN_O_VAL
JTAG_TAP;AON;SYSCTRL;VDDS_BOD_EN_O_VAL
JTAG_TAP;AON;SYSCTRL;VDD_OK_OR_O_VAL
JTAG_TAP;AON;SYSCTRL;VDDR_OK_OR_O_VAL
JTAG_TAP;AON;SYSCTRL;VDDS_OK_OR_O_VAL
JTAG_TAP;AON;SYSCTRL;CLK_LOSS_OR_N_O_VAL
JTAG_TAP;AON;SYSCTRL_OBS
JTAG_TAP;AON;SYSCTRL_OBS;SYSCTRL_NC
JTAG_TAP;AON;SYSCTRL_OBS;SYSCTRL_VDDR_OK_I
JTAG_TAP;AON;SYSCTRL_OBS;SYSCTRL_FSMSTATE
JTAG_TAP;AON;SYSCTRL_OBS;VDDR_OK
JTAG_TAP;AON;SYSCTRL_OBS;VDDS_BOD_OK
JTAG_TAP;AON;SYSCTRL_OR
JTAG_TAP;AON;SYSCTRL_OR;WR_EVENT_O_OR
JTAG_TAP;AON;SYSCTRL_OR;DEBUG_EN_CLR_OR
JTAG_TAP;AON;SYSCTRL_OR;DEBUG_EN_SET_OR
JTAG_TAP;AON;SYSCTRL_OR;SCLK_HF_EN_O_OR
JTAG_TAP;AON;SYSCTRL_OR;SYSCTRLPD_O_OR
JTAG_TAP;AON;SYSCTRL_OR;CLK_ADC_EN_O_OR
JTAG_TAP;AON;SYSCTRL_OR;CLK_CHP_EN_O_OR
JTAG_TAP;AON;SYSCTRL_OR;FORCE_RCOSC_HF_O_OR
JTAG_TAP;AON;SYSCTRL_OR;CLK_DCDC_EN_O_OR
JTAG_TAP;AON;SYSCTRL_OR;RESET_VDDSZ_EN_O_OR
JTAG_TAP;AON;SYSCTRL_OR;PAD_RING_SLEEP_N_O_OR
JTAG_TAP;AON;SYSCTRL_OR;SHUTDOWN_O_OR
JTAG_TAP;AON;SYSCTRL_OR;BYPASS_OSCDIG_OR
JTAG_TAP;AON;SYSCTRL_OR;VDD_BOD_EN_O_OR
JTAG_TAP;AON;SYSCTRL_OR;VREF_SH_O_OR
JTAG_TAP;AON;SYSCTRL_OR;VREF_TRIM_EN_O_OR
JTAG_TAP;AON;SYSCTRL_OR;DIG_LDO_PRESLEEP_O_OR
JTAG_TAP;AON;SYSCTRL_OR;VDD_LDO_EN_O_OR
JTAG_TAP;AON;SYSCTRL_OR;SLEEP_MODE_EN_O_OR
JTAG_TAP;AON;SYSCTRL_OR;DCDC_EN_O_OR
JTAG_TAP;AON;SYSCTRL_OR;VDDR_REG_EN_O_OR
JTAG_TAP;AON;SYSCTRL_OR;GBIAS_EN_O_OR
JTAG_TAP;AON;SYSCTRL_OR;BGAP_EN_O_OR
JTAG_TAP;AON;SYSCTRL_OR;VDDS_BOD_EN_O_OR
JTAG_TAP;AON;SYSCTRL_OR;VDD_OK_OR_O_OR
JTAG_TAP;AON;SYSCTRL_OR;VDDR_OK_OR_O_OR
JTAG_TAP;AON;SYSCTRL_OR;VDDS_OK_OR_O_OR
JTAG_TAP;AON;SYSCTRL_OR;CLK_LOSS_OR_N_O_OR
JTAG_TAP;AON;MISC
JTAG_TAP;AON;MISC;MISC_NC
JTAG_TAP;AON;MISC;MCU_CLK_HF_FREQ_O_VAL
JTAG_TAP;AON;MISC;SCLK_LF_STOP_VAL
JTAG_TAP;AON;MISC;JTAG_DONOTRESET_WUCTAP_VAL
JTAG_TAP;AON;MISC;REPAIR_DONE_VAL
JTAG_TAP;AON;MISC;GOTO_ACT_MODE_VAL
JTAG_TAP;AON;MISC;GOTO_PD_MODE_VAL
JTAG_TAP;AON;MISC;JTAG_DONOTPOWERUP_VAL
JTAG_TAP;AON;MISC_OBS
JTAG_TAP;AON;MISC_OBS;NC7
JTAG_TAP;AON;MISC_OBS;JTAG_PGOODIN
JTAG_TAP;AON;MISC_OBS;JTAG_PONIN
JTAG_TAP;AON;MISC_OBS;JTAG_STATE
JTAG_TAP;AON;MISC_OBS;PM_STATE
JTAG_TAP;AON;MISC_OR
JTAG_TAP;AON;MISC_OR;MISC_NC7
JTAG_TAP;AON;MISC_OR;MCU_CLK_HF_FREQ_O_OR
JTAG_TAP;AON;MISC_OR;MISC_NC5
JTAG_TAP;AON;MISC_OR;MISC_NC4
JTAG_TAP;AON;MISC_OR;REPAIR_DONE_OR
JTAG_TAP;AON;MISC_OR;GOTO_ACT_MODE_OR
JTAG_TAP;AON;MISC_OR;GOTO_PD_MODE_OR
JTAG_TAP;AON;MISC_OR;MISC_NC0
JTAG_TAP;AON;MCUVD
JTAG_TAP;AON;MCUVD;MCU_LATCH_EN_VAL
JTAG_TAP;AON;MCUVD;MCU_RESET_N_O_VAL
JTAG_TAP;AON;MCUVD;MCU_ISO_EN_VAL
JTAG_TAP;AON;MCUVD;MCU_VDD_PON_VAL
JTAG_TAP;AON;MCUVD;MCU_VDD_PGOOD_VAL
JTAG_TAP;AON;MCUVD;MCU_SRAM_PGOOD_VAL
JTAG_TAP;AON;MCUVD;MCU_SRAM_PON_VAL
JTAG_TAP;AON;MCUVD;MCU_SRAM_ERASE_VAL
JTAG_TAP;AON;MCUVD;MCU_SRAM_AGOOD_VAL
JTAG_TAP;AON;MCUVD;MCU_SRAM_AON_VAL
JTAG_TAP;AON;MCUVD;MCU_SRAM_ISO_VAL
JTAG_TAP;AON;MCUVD;MCU_SRAM_RETGOOD_VAL
JTAG_TAP;AON;MCUVD;MCU_SRAM_RETON_VAL
JTAG_TAP;AON;MCUVD_OBS
JTAG_TAP;AON;MCUVD_OBS;NC
JTAG_TAP;AON;MCUVD_OBS;MCU_VDDCTRL_STATE
JTAG_TAP;AON;MCUVD_OR
JTAG_TAP;AON;MCUVD_OR;MCU_LATCH_EN_OR
JTAG_TAP;AON;MCUVD_OR;MCU_RESET_N_O_OR
JTAG_TAP;AON;MCUVD_OR;MCU_ISO_EN_OR
JTAG_TAP;AON;MCUVD_OR;MCU_VDD_PON_OR
JTAG_TAP;AON;MCUVD_OR;MCU_VDD_PGOOD_OR
JTAG_TAP;AON;MCUVD_OR;MCU_SRAM_PGOOD_OR
JTAG_TAP;AON;MCUVD_OR;MCU_SRAM_PON_OR
JTAG_TAP;AON;MCUVD_OR;MCU_SRAM_ERASE_OR
JTAG_TAP;AON;MCUVD_OR;MCU_SRAM_AGOOD_OR
JTAG_TAP;AON;MCUVD_OR;MCU_SRAM_AON_OR
JTAG_TAP;AON;MCUVD_OR;MCU_SRAM_ISO_OR
JTAG_TAP;AON;MCUVD_OR;MCU_SRAM_RETGOOD_OR
JTAG_TAP;AON;MCUVD_OR;MCU_SRAM_RETON_OR
JTAG_TAP;AON;CLK
JTAG_TAP;AON;CLK;AUX_CLK_SRC_VAL
JTAG_TAP;AON;CLK;MCU_CLK_SRC_VAL
JTAG_TAP;AON;CLK;HF_CLK_O_VAL
JTAG_TAP;AON;CLK;MF_CLK_O_VAL
JTAG_TAP;AON;CLK;LF_CLK_O_VAL
JTAG_TAP;AON;CLK_OBS
JTAG_TAP;AON;CLK_OBS;AUX_CLK_STATUS
JTAG_TAP;AON;CLK_OBS;MCU_CLK_STATUS
JTAG_TAP;AON;CLK_OBS;CLK_NC
JTAG_TAP;AON;CLK_OR
JTAG_TAP;AON;CLK_OR;AUX_CLK_SRC_OR
JTAG_TAP;AON;CLK_OR;MCU_CLK_SRC_OR
JTAG_TAP;AON;CLK_OR;HF_CLK_O_OR
JTAG_TAP;AON;CLK_OR;MF_CLK_O_OR
JTAG_TAP;AON;CLK_OR;LF_CLK_O_OR
JTAG_TAP;AON;AUXVD
JTAG_TAP;AON;AUXVD;AUX_RESET_N_O_VAL
JTAG_TAP;AON;AUXVD;MCU_ISO_EN_VAL
JTAG_TAP;AON;AUXVD;MCU_VDD_PON_VAL
JTAG_TAP;AON;AUXVD;MCU_VDD_PGOOD_VAL
JTAG_TAP;AON;AUXVD;AUX_SRAM_PGOOD_VAL
JTAG_TAP;AON;AUXVD;AUX_SRAM_PON_VAL
JTAG_TAP;AON;AUXVD;AUX_SRAM_ERASE_VAL
JTAG_TAP;AON;AUXVD;AUX_SRAM_AGOOD_VAL
JTAG_TAP;AON;AUXVD;AUX_SRAM_AON_VAL
JTAG_TAP;AON;AUXVD;AUX_SRAM_ISO_VAL
JTAG_TAP;AON;AUXVD;AUX_SRAM_RETGOOD_VAL
JTAG_TAP;AON;AUXVD;AUX_SRAM_RETON_VAL
JTAG_TAP;AON;AUXVD_OBS
JTAG_TAP;AON;AUXVD_OBS;AUX_VDCTRL10
JTAG_TAP;AON;AUXVD_OBS;AUX_VDD_PGOODOUT
JTAG_TAP;AON;AUXVD_OBS;AUX_VDD_PONOUT
JTAG_TAP;AON;AUXVD_OBS;AUX_VDCTRL4
JTAG_TAP;AON;AUXVD_OBS;AUX_VDDCTRL_STATE
JTAG_TAP;AON;AUXVD_OR
JTAG_TAP;AON;AUXVD_OR;AUX_RESET_N_O_OR
JTAG_TAP;AON;AUXVD_OR;MCU_ISO_EN_OR
JTAG_TAP;AON;AUXVD_OR;MCU_VDD_PON_OR
JTAG_TAP;AON;AUXVD_OR;MCU_VDD_PGOOD_OR
JTAG_TAP;AON;AUXVD_OR;AUX_SRAM_PGOOD_OR
JTAG_TAP;AON;AUXVD_OR;AUX_SRAM_PON_OR
JTAG_TAP;AON;AUXVD_OR;AUX_SRAM_ERASE_OR
JTAG_TAP;AON;AUXVD_OR;AUX_SRAM_AGOOD_OR
JTAG_TAP;AON;AUXVD_OR;AUX_SRAM_AON_OR
JTAG_TAP;AON;AUXVD_OR;AUX_SRAM_ISO_OR
JTAG_TAP;AON;AUXVD_OR;AUX_SRAM_RETGOOD_OR
JTAG_TAP;AON;AUXVD_OR;AUX_SRAM_RETON_OR
JTAG_TAP;AON;TMS_CTRL
JTAG_TAP;AON;TMS_CTRL;MCU_FORCEACTIVE_O
JTAG_TAP;AON;TMS_CTRL;TMS_EC
JTAG_TAP;AON;TMS_CTRL;TMS_SC
JTAG_TAP;AON;TMS_CTRL;TMS_HC
JTAG_TAP;AON;TMS_CTRL;TMS_STRIN
JTAG_TAP;AON;PSCON_CTRL
JTAG_TAP;AON;PSCON_CTRL;WUC_PSCON_SPARE
JTAG_TAP;AON;PSCON_CTRL;WUC_PSCON_AONONLY_SEL
JTAG_TAP;AON;PSCON_CTRL;WUC_PSCON_TSTCLK_BYPASS
JTAG_TAP;AON;PSCON_CTRL;WUC_PSCON_BLOCKOUT
JTAG_TAP;AON;PSCON_CTRL;WUC_PSCON_MODE
