## SSI1

Instance: SSI1
Component: SSI
Base address: 0x40008000

Synchronous Serial Interface with master and slave capabilities

### TOP:SSI1 Register Summary

Register Name | Type | Register Width (Bits) | Register Reset | Address Offset | Physical Address
CR0 | RW | 32 | 0x0000 0000 | 0x0000 0000 | 0x4000 8000
CR1 | RW | 32 | 0x0000 0000 | 0x0000 0004 | 0x4000 8004
DR | RW | 32 | 0x0000 0000 | 0x0000 0008 | 0x4000 8008
SR | RO | 32 | 0x0000 0003 | 0x0000 000C | 0x4000 800C
CPSR | RW | 32 | 0x0000 0000 | 0x0000 0010 | 0x4000 8010
IMSC | RW | 32 | 0x0000 0000 | 0x0000 0014 | 0x4000 8014
RIS | RO | 32 | 0x0000 0008 | 0x0000 0018 | 0x4000 8018
MIS | RO | 32 | 0x0000 0000 | 0x0000 001C | 0x4000 801C
ICR | WO | 32 | 0x0000 0000 | 0x0000 0020 | 0x4000 8020
DMACR | RW | 32 | 0x0000 0000 | 0x0000 0024 | 0x4000 8024

### TOP:SSI1 Register Descriptions

### TOP:SSI:CR0

Address offset | 0x0000 0000
Physical address | 0x4000 8000 | Instance | SSI1
Description | Control Register 0
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0000
15:8 | SCR | Serial clock rate: This is used to generate the transmit and receive bit rate of the SSI. The bit rate is (SSI's clock frequency)/((SCR+1).CPSR.CPSDVSR). SCR is a value from 0-255. | RW | 0x00
7 | SPH | CLKOUT phase (Motorola SPI frame format only) This bit selects the clock edge that captures data and enables it to change state. It has the most impact on the first bit transmitted by either permitting or not permitting a clock transition before the first data capture edge.
Value | ENUM name | Description
0 | 1ST_CLK_EDGE | Data is captured on the first clock edge transition.
1 | 2ND_CLK_EDGE | Data is captured on the second clock edge transition.
| RW | 0
6 | SPO | CLKOUT polarity (Motorola SPI frame format only)
Value | ENUM name | Description
0 | LOW | SSI produces a steady state LOW value on the CLKOUT pin when data is not being transferred.
1 | HIGH | SSI produces a steady state HIGH value on the CLKOUT pin when data is not being transferred.
| RW | 0
5:4 | FRF | Frame format. The supported frame formats are Motorola SPI, TI synchronous serial and National Microwire. Value 0'b11 is reserved and shall not be used.
Value | ENUM name | Description
0x0 | MOTOROLA_SPI | Motorola SPI frame format
0x1 | TI_SYNC_SERIAL | TI synchronous serial frame format
0x2 | NATIONAL_MICROWIRE | National Microwire frame format
| RW | 0x0
3:0 | DSS | Data Size Select. Values 0b0000, 0b0001, 0b0010 and 0b0011 are reserved and shall not be used.
Value | ENUM name | Description
0x3 | 4_BIT | 4-bit data
0x4 | 5_BIT | 5-bit data
0x5 | 6_BIT | 6-bit data
0x6 | 7_BIT | 7-bit data
0x7 | 8_BIT | 8-bit data
0x8 | 9_BIT | 9-bit data
0x9 | 10_BIT | 10-bit data
0xA | 11_BIT | 11-bit data
0xB | 12_BIT | 12-bit data
0xC | 13_BIT | 13-bit data
0xD | 14_BIT | 14-bit data
0xE | 15_BIT | 15-bit data
0xF | 16_BIT | 16-bit data
| RW | 0x0

### TOP:SSI:CR1

Address offset | 0x0000 0004
Physical address | 0x4000 8004 | Instance | SSI1
Description | Control Register 1
Type | RW

Bits | Field Name | Description | Type | Reset
31:4 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x000 0000
3 | SOD | Slave-mode output disabled This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an SSI master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, this bitfield can be set if the SSI slave is not supposed to drive the TXD line: 0: SSI can drive the TXD output in slave mode. 1: SSI cannot drive the TXD output in slave mode. | RW | 0
2 | MS | Master or slave mode select. This bit can be modified only when SSI is disabled, SSE=0.
Value | ENUM name | Description
0 | MASTER | Device configured as master
1 | SLAVE | Device configured as slave
| RW | 0
1 | SSE | Synchronous serial interface enable.
Value | ENUM name | Description
0 | SSI_DISABLED | Operation disabled
1 | SSI_ENABLED | Operation enabled
| RW | 0
0 | LBM | Loop back mode: 0: Normal serial port operation enabled. 1: Output of transmit serial shifter is connected to input of receive serial shifter internally. | RW | 0

### TOP:SSI:DR

Address offset | 0x0000 0008
Physical address | 0x4000 8008 | Instance | SSI1
Description | Data Register 16-bits wide data register: When read, the entry in the receive FIFO, pointed to by the current FIFO read pointer, is accessed. As data values are removed by the receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. When written, the entry in the transmit FIFO, pointed to by the write pointer, is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the TXD output pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer.
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0000
15:0 | DATA | Transmit/receive data The values read from this field or written to this field must be right-justified when SSI is programmed for a data size that is less than 16 bits (CR0.DSS != 0b1111). Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies. | RW | 0x0000

### TOP:SSI:SR

Address offset | 0x0000 000C
Physical address | 0x4000 800C | Instance | SSI1
Description | Status Register
Type | RO

Bits | Field Name | Description | Type | Reset
31:5 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x000 0000
4 | BSY | Serial interface busy: 0: SSI is idle 1: SSI is currently transmitting and/or receiving a frame or the transmit FIFO is not empty. | RO | 0
3 | RFF | Receive FIFO full: 0: Receive FIFO is not full. 1: Receive FIFO is full. | RO | 0
2 | RNE | Receive FIFO not empty 0: Receive FIFO is empty. 1: Receive FIFO is not empty. | RO | 0
1 | TNF | Transmit FIFO not full: 0: Transmit FIFO is full. 1: Transmit FIFO is not full. | RO | 1
0 | TFE | Transmit FIFO empty: 0: Transmit FIFO is not empty. 1: Transmit FIFO is empty. | RO | 1

### TOP:SSI:CPSR

Address offset | 0x0000 0010
Physical address | 0x4000 8010 | Instance | SSI1
Description | Clock Prescale Register
Type | RW

Bits | Field Name | Description | Type | Reset
31:8 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x00 0000
7:0 | CPSDVSR | Clock prescale divisor: This field specifies the division factor by which the input system clock to SSI must be internally divided before further use. The value programmed into this field must be an even non-zero number (2-254). The least significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least significant bit as zero. | RW | 0x00

### TOP:SSI:IMSC

Address offset | 0x0000 0014
Physical address | 0x4000 8014 | Instance | SSI1
Description | Interrupt Mask Set and Clear Register
Type | RW

Bits | Field Name | Description | Type | Reset
31:4 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x000 0000
3 | TXIM | Transmit FIFO interrupt mask: A read returns the current mask for transmit FIFO interrupt. On a write of 1, the mask for transmit FIFO interrupt is set which means the interrupt state will be reflected in MIS.TXMIS. A write of 0 clears the mask which means MIS.TXMIS will not reflect the interrupt. | RW | 0
2 | RXIM | Receive FIFO interrupt mask: A read returns the current mask for receive FIFO interrupt. On a write of 1, the mask for receive FIFO interrupt is set which means the interrupt state will be reflected in MIS.RXMIS. A write of 0 clears the mask which means MIS.RXMIS will not reflect the interrupt. | RW | 0
1 | RTIM | Receive timeout interrupt mask: A read returns the current mask for receive timeout interrupt. On a write of 1, the mask for receive timeout interrupt is set which means the interrupt state will be reflected in MIS.RTMIS. A write of 0 clears the mask which means MIS.RTMIS will not reflect the interrupt. | RW | 0
0 | RORIM | Receive overrun interrupt mask: A read returns the current mask for receive overrun interrupt. On a write of 1, the mask for receive overrun interrupt is set which means the interrupt state will be reflected in MIS.RORMIS. A write of 0 clears the mask which means MIS.RORMIS will not reflect the interrupt. | RW | 0

### TOP:SSI:RIS

Address offset | 0x0000 0018
Physical address | 0x4000 8018 | Instance | SSI1
Description | Raw Interrupt Status Register
Type | RO

Bits | Field Name | Description | Type | Reset
31:4 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x000 0000
3 | TXRIS | Raw transmit FIFO interrupt status: The transmit interrupt is asserted when there are four or fewer valid entries in the transmit FIFO. The transmit interrupt is not qualified with the SSI enable signal. Therefore one of the following ways can be used: - data can be written to the transmit FIFO prior to enabling the SSI and the interrupts. - SSI and interrupts can be enabled so that data can be written to the transmit FIFO by an interrupt service routine. | RO | 1
2 | RXRIS | Raw interrupt state of receive FIFO interrupt: The receive interrupt is asserted when there are four or more valid entries in the receive FIFO. | RO | 0
1 | RTRIS | Raw interrupt state of receive timeout interrupt: The receive timeout interrupt is asserted when the receive FIFO is not empty and SSI has remained idle for a fixed 32 bit period. This mechanism can be used to notify the user that data is still present in the receive FIFO and requires servicing. This interrupt is deasserted if the receive FIFO becomes empty by subsequent reads, or if new data is received on RXD. It can also be cleared by writing to ICR.RTIC. | RO | 0
0 | RORRIS | Raw interrupt state of receive overrun interrupt: The receive overrun interrupt is asserted when the FIFO is already full and an additional data frame is received, causing an overrun of the FIFO. Data is over-written in the receive shift register, but not the FIFO so the FIFO contents stay valid. It can also be cleared by writing to ICR.RORIC. | RO | 0

### TOP:SSI:MIS

Address offset | 0x0000 001C
Physical address | 0x4000 801C | Instance | SSI1
Description | Masked Interrupt Status Register
Type | RO

Bits | Field Name | Description | Type | Reset
31:4 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x000 0000
3 | TXMIS | Masked interrupt state of transmit FIFO interrupt: This field returns the masked interrupt state of transmit FIFO interrupt which is the AND product of raw interrupt state RIS.TXRIS and the mask setting IMSC.TXIM. | RO | 0
2 | RXMIS | Masked interrupt state of receive FIFO interrupt: This field returns the masked interrupt state of receive FIFO interrupt which is the AND product of raw interrupt state RIS.RXRIS and the mask setting IMSC.RXIM. | RO | 0
1 | RTMIS | Masked interrupt state of receive timeout interrupt: This field returns the masked interrupt state of receive timeout interrupt which is the AND product of raw interrupt state RIS.RTRIS and the mask setting IMSC.RTIM. | RO | 0
0 | RORMIS | Masked interrupt state of receive overrun interrupt: This field returns the masked interrupt state of receive overrun interrupt which is the AND product of raw interrupt state RIS.RORRIS and the mask setting IMSC.RORIM. | RO | 0

### TOP:SSI:ICR

Address offset | 0x0000 0020
Physical address | 0x4000 8020 | Instance | SSI1
Description | Interrupt Clear Register On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect.
Type | WO

Bits | Field Name | Description | Type | Reset
31:2 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(WO std text) | WO | 0x0000 0000
1 | RTIC | Clear the receive timeout interrupt: Writing 1 to this field clears the timeout interrupt (RIS.RTRIS). Writing 0 has no effect. | WO | 0
0 | RORIC | Clear the receive overrun interrupt: Writing 1 to this field clears the overrun error interrupt (RIS.RORRIS). Writing 0 has no effect. | WO | 0

### TOP:SSI:DMACR

Address offset | 0x0000 0024
Physical address | 0x4000 8024 | Instance | SSI1
Description | DMA Control Register
Type | RW

Bits | Field Name | Description | Type | Reset
31:2 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0000 0000
1 | TXDMAE | Transmit DMA enable. If this bit is set to 1, DMA for the transmit FIFO is enabled. | RW | 0
0 | RXDMAE | Receive DMA enable. If this bit is set to 1, DMA for the receive FIFO is enabled. | RW | 0