## ADI_4_AUX

Instance: ADI_4_AUX
Component: ADI_4_AUX
Base address: 0x400cb000

Configuration registers controlling analog peripherals of AUX. Registers Fields should be considered static unless otherwise noted (as dynamic)

### TOP:ADI_4_AUX Register Summary

Register Name | Type | Register Width (Bits) | Register Reset | Address Offset | Physical Address
ISRC | RW | 8 | 0x0000 0000 | 0x0000 0004 | 0x400C B004
COMP | RW | 8 | 0x0000 0000 | 0x0000 0005 | 0x400C B005
CHPTEST | RW | 8 | 0x0000 0000 | 0x0000 0006 | 0x400C B006
ADC0 | RW | 8 | 0x0000 0000 | 0x0000 0008 | 0x400C B008
ADC1 | RW | 8 | 0x0000 0000 | 0x0000 0009 | 0x400C B009
ADCREF0 | RW | 8 | 0x0000 0000 | 0x0000 000A | 0x400C B00A
ADCREF1 | RW | 8 | 0x0000 0000 | 0x0000 000B | 0x400C B00B

### TOP:ADI_4_AUX Register Descriptions

### TOP:ADI_4_AUX:ISRC

Address offset | 0x0000 0004
Physical address | 0x400C B004 | Instance | ADI_4_AUX
Description | Current Source Strength and trim control for current source
Type | RW

Bits | Field Name | Description | Type | Reset
7:2 | TRIM | Adjust current from current source. Output currents may be combined to get desired total current.
Value | ENUM name | Description
0x00 | NC | No current connected
0x01 | 0P25U | 0.25 uA
0x02 | 0P5U | 0.5 uA
0x04 | 1P0U | 1.0 uA
0x08 | 2P0U | 2.0 uA
0x10 | 4P5U | 4.5 uA
0x20 | 11P75U | 11.75 uA
| RW | 0x00
1 | Reserved | Internal | RW | 0
0 | EN | Current source enable | RW | 0

### TOP:ADI_4_AUX:COMP

Address offset | 0x0000 0005
Physical address | 0x400C B005 | Instance | ADI_4_AUX
Description | Comparator Control COMPA and COMPB comparators
Type | RW

Bits | Field Name | Description | Type | Reset
7 | COMPA_REF_RES_EN | Enables 400kohm resistance from COMPA reference node to ground. Used with COMPA_REF_CURR_EN to generate voltage reference for cap-sense. | RW | 0
6 | COMPA_REF_CURR_EN | Enables 2uA IPTAT current from ISRC to COMPA reference node. Requires ISRC.EN = 1. Used with COMPA_REF_RES_EN to generate voltage reference for cap-sense. | RW | 0
5:3 | COMPB_TRIM | COMPB voltage reference trim temperature coded:
Value | ENUM name | Description
0x0 | DIV1 | No reference division
0x1 | DIV2 | Divide reference by 2
0x3 | DIV3 | Divide reference by 3
0x7 | DIV4 | Divide reference by 4
| RW | 0x0
2 | COMPB_EN | Comparator B enable | RW | 0
1 | Reserved | Internal | RW | 0
0 | COMPA_EN | COMPA enable | RW | 0

### TOP:ADI_4_AUX:CHPTEST

Address offset | 0x0000 0006
Physical address | 0x400C B006 | Instance | ADI_4_AUX
Description | Charge Pump Test Control of charge pump and test modes
Type | RW

Bits | Field Name | Description | Type | Reset
7 | CHP_EN | Enable AUX Charge pump | RW | 0
6 | Reserved | Internal | RW | 0
5 | Reserved | Internal | RW | 0
4:0 | Reserved | Internal | RW | 0x00

### TOP:ADI_4_AUX:ADC0

Address offset | 0x0000 0008
Physical address | 0x400C B008 | Instance | ADI_4_AUX
Description | ADC Control
Type | RW

Bits | Field Name | Description | Type | Reset
7 | SMPL_MODE | ADC Sampling mode: 0: Synchronous mode 1: Asynchronous mode The ADC does a sample-and-hold before conversion. In synchronous mode the sampling starts when the ADC clock detects a rising edge on the trigger signal. Jitter/uncertainty will be inferred in the detection if the trigger signal originates from a domain that is asynchronous to the ADC clock. SMPL_CYCLE_EXP determines the the duration of sampling as 2^(SMPL_CYCLE_EXP+1) * 1/6MHz. Conversion starts immediately after sampling ends. In asynchronous mode the sampling is continuous when enabled. Sampling ends and conversion starts immediately with the rising edge of the trigger signal. Sampling restarts when the conversion has finished. Asynchronous mode is useful when it is important to avoid jitter in the sampling instant of an externally driven signal | RW | 0
6:3 | SMPL_CYCLE_EXP | Controls number of 6 MHz clock cycles in sampling/tracking mode before conversion. The sampling time will be 2^(SMPL_CYCLE_EXP + 1) 6 MHz clock periods. Giving a range of 2 to 65536 clock periods sampling time (up to 10.9ms). This setting only has effect in synchronous mode (SMPL_MODE =0). The default minimum value should be 3 (2.7us sampling time). Less than that should be considered experimental. | RW | 0x0
2 | Reserved | Internal | RW | 0
1 | RESET_N | Reset ADC digital subchip, active low. ADC must be reset every time it is reconfigured. 0: Reset 1: Normal operation | RW | 0
0 | EN | ADC Enable 0: Disable 1: Enable | RW | 0

### TOP:ADI_4_AUX:ADC1

Address offset | 0x0000 0009
Physical address | 0x400C B009 | Instance | ADI_4_AUX
Description | Control ADC
Type | RW

Bits | Field Name | Description | Type | Reset
7:5 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text) | RW | 0x0
4 | Reserved | Internal | RW | 0
3 | Reserved | Internal | RW | 0
2:1 | Reserved | Internal | RW | 0x0
0 | Reserved | Internal | RW | 0

### TOP:ADI_4_AUX:ADCREF0

Address offset | 0x0000 000A
Physical address | 0x400C B00A | Instance | ADI_4_AUX
Description | Analog To Digital Reference 0 Control reference used by the ADC
Type | RW

Bits | Field Name | Description | Type | Reset
7 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text) | RW | 0
6 | REF_ON_IDLE | Keep ADCREF powered up in IDLE state when ADC0.SMPL_MODE = 0. Set to 1 if ADC0.SMPL_CYCLE_EXP is less than 6 (21.3us sampling time) | RW | 0
5 | Reserved | Internal | RW | 0
4 | Reserved | Internal | RW | 0
3 | SRC | ADC reference source: 0: Fixed reference = 4.3V 1: Relative reference = VDDA | RW | 0
2 | Reserved | Internal | RW | 0
1 | Reserved | Internal | RW | 0
0 | EN | ADC reference module enable: 0: ADC reference module powered down 1: ADC reference module enabled | RW | 0

### TOP:ADI_4_AUX:ADCREF1

Address offset | 0x0000 000B
Physical address | 0x400C B00B | Instance | ADI_4_AUX
Description | Analog To Digital Reference 1 Control reference used by the ADC
Type | RW

Bits | Field Name | Description | Type | Reset
7:6 | Reserved | Internal | RW | 0x0
5:0 | VTRIM | Trim output voltage of ADC fixed reference (64 steps, 2's complement). Applies only for ADCREF0.SRC = 0. Examples: 0x00 - nominal voltage 1.43V 0x01 - nominal + 0.4% 1.435V 0x3F - nominal - 0.4% 1.425V 0x1F - maximum voltage 1.6V 0x20 - minimum voltage 1.3V | RW | 0x00