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aux_adc.c
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1 /******************************************************************************
2 * Filename: aux_adc.c
3 * Revised: 2015-01-13 16:59:55 +0100 (ti, 13 jan 2015)
4 * Revision: 42365
5 *
6 * Description: Driver for the AUX Time to Digital Converter interface.
7 *
8 * Copyright (c) 2015, Texas Instruments Incorporated
9 * All rights reserved.
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions are met:
13 *
14 * 1) Redistributions of source code must retain the above copyright notice,
15 * this list of conditions and the following disclaimer.
16 *
17 * 2) Redistributions in binary form must reproduce the above copyright notice,
18 * this list of conditions and the following disclaimer in the documentation
19 * and/or other materials provided with the distribution.
20 *
21 * 3) Neither the name of the ORGANIZATION nor the names of its contributors may
22 * be used to endorse or promote products derived from this software without
23 * specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
26 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
28 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
29 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
35 * POSSIBILITY OF SUCH DAMAGE.
36 *
37 ******************************************************************************/
38
39 #include <driverlib/aux_adc.h>
40 #include <inc/hw_memmap.h>
41 #include <inc/hw_aux_wuc.h>
42 #include <driverlib/adi.h>
43 #include <driverlib/event.h>
44
45 //*****************************************************************************
46 //
48 //
49 //*****************************************************************************
50 void
51 AUXADCDisable(void)
52 {
53 // Disable the ADC reference
54 ADI8BitsClear(AUX_ADI4_BASE, ADI_4_AUX_O_ADCREF0, ADI_4_AUX_ADCREF0_EN_M | ADI_4_AUX_ADCREF0_REF_ON_IDLE_M | ADI_4_AUX_ADCREF0_SRC_M);
55
56 // Assert reset and disable the ADC
57 ADI8BitsClear(AUX_ADI4_BASE, ADI_4_AUX_O_ADC0, ADI_4_AUX_ADC0_EN_M | ADI_4_AUX_ADC0_RESET_N_M | ADI_4_AUX_ADC0_SMPL_MODE_M | ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_M);
58
59 // Disable the ADC clock (no need to wait since IOB_WUC_ADCCLKCTL_ACK goes low immediately)
60 HWREG(AUX_WUC_BASE + AUX_WUC_O_ADCCLKCTL) = 0;
61
62 // Disable the ADC data interface
63 HWREG(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCCTL) = 0;
64 }
65
66 //*****************************************************************************
67 //
68 // Enables the ADC for asynchronous operation
69 //
70 //*****************************************************************************
71 void
72 AUXADCEnableAsync(uint32_t refSource, uint32_t trigger)
73 {
74 // Enable the ADC reference, with the following options:
75 // - SRC: Set when using relative reference
76 // - REF_ON_IDLE: Always cleared since there is no idle state in asynchronous operation
77 ADI8BitsSet(AUX_ADI4_BASE, ADI_4_AUX_O_ADCREF0, refSource | ADI_4_AUX_ADCREF0_EN_M);
78
79 // Enable the ADC clock
80 HWREG(AUX_WUC_BASE + AUX_WUC_O_ADCCLKCTL) = AUX_WUC_ADCCLKCTL_REQ_M;
81 while (!(HWREG(AUX_WUC_BASE + AUX_WUC_O_ADCCLKCTL) & AUX_WUC_ADCCLKCTL_ACK_M));
82
83 // Enable the ADC data interface
84 if (trigger == AUXADC_TRIGGER_MANUAL) {
85 // Manual trigger: No need to configure event routing from GPT
86 HWREG(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCCTL) = AUX_ANAIF_ADCCTL_START_SRC_NO_EVENT0 | AUX_ANAIF_ADCCTL_CMD_EN;
87 } else {
88 // GPT trigger: Configure event routing via MCU_EV to the AUX domain
89 HWREG(EVENT_BASE + EVENT_O_AUXSEL0) = trigger;
90 HWREG(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCCTL) = AUX_ANAIF_ADCCTL_START_SRC_MCU_EV | AUX_ANAIF_ADCCTL_CMD_EN;
91 }
92
93 // Release reset and enable the ADC
94 ADI8BitsSet(AUX_ADI4_BASE, ADI_4_AUX_O_ADC0, ADI_4_AUX_ADC0_EN_M | ADI_4_AUX_ADC0_RESET_N_M | ADI_4_AUX_ADC0_SMPL_MODE_M);
95 }
96
97 //*****************************************************************************
98 //
99 // Enables the ADC for synchronous operation
100 //
101 //*****************************************************************************
102 void
103 AUXADCEnableSync(uint32_t refSource, uint32_t sampleTime, uint32_t trigger)
104 {
105 // Enable the ADC reference, with the following options:
106 // - SRC: Set when using relative reference
107 // - REF_ON_IDLE: Set when using fixed reference and sample time < 6
108 uint8_t adcref0 = refSource | ADI_4_AUX_ADCREF0_EN_M;
109 if (!refSource && (sampleTime < 6)) {
110 adcref0 |= ADI_4_AUX_ADCREF0_REF_ON_IDLE_M;
111 }
112 ADI8BitsSet(AUX_ADI4_BASE, ADI_4_AUX_O_ADCREF0, adcref0);
113
114 // Enable the ADC clock
115 HWREG(AUX_WUC_BASE + AUX_WUC_O_ADCCLKCTL) = AUX_WUC_ADCCLKCTL_REQ_M;
116 while (!(HWREG(AUX_WUC_BASE + AUX_WUC_O_ADCCLKCTL) & AUX_WUC_ADCCLKCTL_ACK_M));
117
118 // Enable the ADC data interface
119 if (trigger == AUXADC_TRIGGER_MANUAL) {
120 // Manual trigger: No need to configure event routing from GPT
121 HWREG(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCCTL) = AUX_ANAIF_ADCCTL_START_SRC_NO_EVENT0 | AUX_ANAIF_ADCCTL_CMD_EN;
122 } else {
123 // GPT trigger: Configure event routing via MCU_EV to the AUX domain
124 HWREG(EVENT_BASE + EVENT_O_AUXSEL0) = trigger;
125 HWREG(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCCTL) = AUX_ANAIF_ADCCTL_START_SRC_MCU_EV | AUX_ANAIF_ADCCTL_CMD_EN;
126 }
127
128 // Release reset and enable the ADC
129 ADI8BitsSet(AUX_ADI4_BASE, ADI_4_AUX_O_ADC0, ADI_4_AUX_ADC0_EN_M | ADI_4_AUX_ADC0_RESET_N_M | sampleTime);
130 }
131
132 //*****************************************************************************
133 //
134 // Flushes the ADC FIFO
135 //
136 //*****************************************************************************
137 void
138 AUXADCFlushFifo(void)
139 {
140 HWREG(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCCTL) |= 0x00000002;
141 HWREG(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCCTL) &= 0x00000002;
142 }
143
144 //*****************************************************************************
145 //
146 // Waits for and returns the first sample in the ADC FIFO
147 //
148 //*****************************************************************************
149 uint32_t
150 AUXADCReadFifo(void) {
151
152 // Wait until there is at least one sample in the FIFO
153 while (HWREG(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCFIFOSTAT) & AUX_ANAIF_ADCFIFOSTAT_EMPTY_M);
154
155 // Return the first sample from the FIFO
156 return HWREG(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCFIFO);
157 }
aux_adc.h
ADI8BitsClear
__STATIC_INLINE void ADI8BitsClear(uint32_t ui32Base, uint32_t ui32Reg, uint8_t ui8Val)
Clear specific bits in an 8 bit ADI register.
Definition: adi.h:774
AUXADCEnableAsync
void AUXADCEnableAsync(uint32_t refSource, uint32_t trigger)
Enables the ADC for asynchronous operation.
Definition: aux_adc.c:72
AUXADCDisable
void AUXADCDisable(void)
Disables the ADC.
Definition: aux_adc.c:51
adi.h
ADI8BitsSet
__STATIC_INLINE void ADI8BitsSet(uint32_t ui32Base, uint32_t ui32Reg, uint8_t ui8Val)
Set specific bits in a single 8 bit ADI register.
Definition: adi.h:603
AUXADCEnableSync
void AUXADCEnableSync(uint32_t refSource, uint32_t sampleTime, uint32_t trigger)
Enables the ADC for synchronous operation.
Definition: aux_adc.c:103
event.h
AUXADC_TRIGGER_MANUAL
#define AUXADC_TRIGGER_MANUAL
Definition: aux_adc.h:95
AUXADCFlushFifo
void AUXADCFlushFifo(void)
Flushes the ADC FIFO.
Definition: aux_adc.c:138
AUXADCReadFifo
uint32_t AUXADCReadFifo(void)
Waits for and returns the first sample in the ADC FIFO.
Definition: aux_adc.c:150