## CPU_SCS

Instance: CPU_SCS
Component: CPU_SCS
Base address: 0xe000e000

Cortex-M's System Control Space (SCS)

### TOP:CPU_SCS Register Summary

Register Name | Type | Register Width (Bits) | Register Reset | Address Offset | Physical Address
ICTR | RO | 32 | 0x0000 0001 | 0x0000 0004 | 0xE000 E004
ACTLR | RW | 32 | 0x0000 0000 | 0x0000 0008 | 0xE000 E008
STCSR | RW | 32 | 0x0000 0004 | 0x0000 0010 | 0xE000 E010
STRVR | RW | 32 | 0x0000 0000 | 0x0000 0014 | 0xE000 E014
STCVR | RW | 32 | 0x0000 0000 | 0x0000 0018 | 0xE000 E018
STCR | RO | 32 | 0xC007 5300 | 0x0000 001C | 0xE000 E01C
NVIC_ISER0 | RW | 32 | 0x0000 0000 | 0x0000 0100 | 0xE000 E100
NVIC_ISER1 | RW | 32 | 0x0000 0000 | 0x0000 0104 | 0xE000 E104
NVIC_ICER0 | RW | 32 | 0x0000 0000 | 0x0000 0180 | 0xE000 E180
NVIC_ICER1 | RW | 32 | 0x0000 0000 | 0x0000 0184 | 0xE000 E184
NVIC_ISPR0 | RW | 32 | 0x0000 0000 | 0x0000 0200 | 0xE000 E200
NVIC_ISPR1 | RW | 32 | 0x0000 0000 | 0x0000 0204 | 0xE000 E204
NVIC_ICPR0 | RW | 32 | 0x0000 0000 | 0x0000 0280 | 0xE000 E280
NVIC_ICPR1 | RW | 32 | 0x0000 0000 | 0x0000 0284 | 0xE000 E284
NVIC_IABR0 | RO | 32 | 0x0000 0000 | 0x0000 0300 | 0xE000 E300
NVIC_IABR1 | RO | 32 | 0x0000 0000 | 0x0000 0304 | 0xE000 E304
NVIC_IPR0 | RW | 32 | 0x0000 0000 | 0x0000 0400 | 0xE000 E400
NVIC_IPR1 | RW | 32 | 0x0000 0000 | 0x0000 0404 | 0xE000 E404
NVIC_IPR2 | RW | 32 | 0x0000 0000 | 0x0000 0408 | 0xE000 E408
NVIC_IPR3 | RW | 32 | 0x0000 0000 | 0x0000 040C | 0xE000 E40C
NVIC_IPR4 | RW | 32 | 0x0000 0000 | 0x0000 0410 | 0xE000 E410
NVIC_IPR5 | RW | 32 | 0x0000 0000 | 0x0000 0414 | 0xE000 E414
NVIC_IPR6 | RW | 32 | 0x0000 0000 | 0x0000 0418 | 0xE000 E418
NVIC_IPR7 | RW | 32 | 0x0000 0000 | 0x0000 041C | 0xE000 E41C
NVIC_IPR8 | RW | 32 | 0x0000 0000 | 0x0000 0420 | 0xE000 E420
CPUID | RO | 32 | 0x412F C231 | 0x0000 0D00 | 0xE000 ED00
ICSR | RW | 32 | 0x0000 0000 | 0x0000 0D04 | 0xE000 ED04
VTOR | RW | 32 | 0x0000 0000 | 0x0000 0D08 | 0xE000 ED08
AIRCR | RW | 32 | 0xFA05 0000 | 0x0000 0D0C | 0xE000 ED0C
SCR | RW | 32 | 0x0000 0000 | 0x0000 0D10 | 0xE000 ED10
CCR | RW | 32 | 0x0000 0200 | 0x0000 0D14 | 0xE000 ED14
SHPR1 | RW | 32 | 0x0000 0000 | 0x0000 0D18 | 0xE000 ED18
SHPR2 | RW | 32 | 0x0000 0000 | 0x0000 0D1C | 0xE000 ED1C
SHPR3 | RW | 32 | 0x0000 0000 | 0x0000 0D20 | 0xE000 ED20
SHCSR | RW | 32 | 0x0000 0000 | 0x0000 0D24 | 0xE000 ED24
CFSR | RW | 32 | 0x0000 0000 | 0x0000 0D28 | 0xE000 ED28
HFSR | RW | 32 | 0x0000 0000 | 0x0000 0D2C | 0xE000 ED2C
DFSR | RW | 32 | 0x0000 0000 | 0x0000 0D30 | 0xE000 ED30
MMFAR | RW | 32 | 0x0000 0000 | 0x0000 0D34 | 0xE000 ED34
BFAR | RW | 32 | 0x0000 0000 | 0x0000 0D38 | 0xE000 ED38
AFSR | RW | 32 | 0x0000 0000 | 0x0000 0D3C | 0xE000 ED3C
ID_PFR0 | RO | 32 | 0x0000 0030 | 0x0000 0D40 | 0xE000 ED40
ID_PFR1 | RO | 32 | 0x0000 0200 | 0x0000 0D44 | 0xE000 ED44
ID_DFR0 | RO | 32 | 0x0010 0000 | 0x0000 0D48 | 0xE000 ED48
ID_AFR0 | RO | 32 | 0x0000 0000 | 0x0000 0D4C | 0xE000 ED4C
ID_MMFR0 | RO | 32 | 0x0010 0030 | 0x0000 0D50 | 0xE000 ED50
ID_MMFR1 | RO | 32 | 0x0000 0000 | 0x0000 0D54 | 0xE000 ED54
ID_MMFR2 | RO | 32 | 0x0100 0000 | 0x0000 0D58 | 0xE000 ED58
ID_MMFR3 | RO | 32 | 0x0000 0000 | 0x0000 0D5C | 0xE000 ED5C
ID_ISAR0 | RO | 32 | 0x0110 1110 | 0x0000 0D60 | 0xE000 ED60
ID_ISAR1 | RO | 32 | 0x0211 1000 | 0x0000 0D64 | 0xE000 ED64
ID_ISAR2 | RO | 32 | 0x2111 2231 | 0x0000 0D68 | 0xE000 ED68
ID_ISAR3 | RO | 32 | 0x0111 1110 | 0x0000 0D6C | 0xE000 ED6C
ID_ISAR4 | RO | 32 | 0x0131 0132 | 0x0000 0D70 | 0xE000 ED70
CPACR | RW | 32 | 0x0000 0000 | 0x0000 0D88 | 0xE000 ED88
DHCSR | RW | 32 | 0x0000 0000 | 0x0000 0DF0 | 0xE000 EDF0
DCRSR | WO | 32 | 0x0000 0000 | 0x0000 0DF4 | 0xE000 EDF4
DCRDR | RW | 32 | 0x0000 0000 | 0x0000 0DF8 | 0xE000 EDF8
DEMCR | RW | 32 | 0x0000 0000 | 0x0000 0DFC | 0xE000 EDFC
STIR | WO | 32 | 0x0000 0000 | 0x0000 0F00 | 0xE000 EF00

### TOP:CPU_SCS Register Descriptions

### TOP:CPU_SCS:ICTR

Address offset | 0x0000 0004
Physical address | 0xE000 E004 | Instance | CPU_SCS
Description | Interrupt Control Type Register Read this register to see the number of interrupt lines that the NVIC supports.
Type | RO

Bits | Field Name | Description | Type | Reset
31:3 | RESERVED3 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0000 0000
2:0 | INTLINESNUM | Total number of interrupt lines in groups of 32. 0: 0...32 1: 33...64 2: 65...96 3: 97...128 4: 129...160 5: 161...192 6: 193...224 7: 225...256 | RO | 0x1

### TOP:CPU_SCS:ACTLR

Address offset | 0x0000 0008
Physical address | 0xE000 E008 | Instance | CPU_SCS
Description | Auxiliary Control Register This register is used to disable certain aspects of functionality within the processor
Type | RW

Bits | Field Name | Description | Type | Reset
31:3 | RESERVED3 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RW | 0x0000 0000
2 | DISFOLD | Disables folding of IT instruction. | RW | 0
1 | DISDEFWBUF | Disables write buffer use during default memory map accesses. This causes all bus faults to be precise bus faults but decreases the performance of the processor because the stores to memory have to complete before the next instruction can be executed. | RW | 0
0 | DISMCYCINT | Disables interruption of multi-cycle instructions. This increases the interrupt latency of the processor becuase LDM/STM completes before interrupt stacking occurs. | RW | 0

### TOP:CPU_SCS:STCSR

Address offset | 0x0000 0010
Physical address | 0xE000 E010 | Instance | CPU_SCS
Description | SysTick Control and Status Register This register enables the SysTick features and returns status flags related to SysTick.
Type | RW

Bits | Field Name | Description | Type | Reset
31:17 | RESERVED17 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0000
16 | COUNTFLAG | Returns 1 if timer counted to 0 since last time this was read. Clears on read by application of any part of the SysTick Control and Status Register. If read by the debugger using the DAP, this bit is cleared on read-only if the MasterType bit in the AHB-AP Control Register is set to 0. Otherwise, COUNTFLAG is not changed by the debugger read. | RO | 0
15:3 | RESERVED3 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0000
2 | CLKSOURCE | Clock source: 0: External reference clock. 1: Core clock External clock is not available in this device. Writes to this field will be ignored. | RO | 1
1 | TICKINT | 0: Counting down to zero does not pend the SysTick handler. Software can use COUNTFLAG to determine if the SysTick handler has ever counted to zero. 1: Counting down to zero pends the SysTick handler. | RW | 0
0 | ENABLE | Enable SysTick counter 0: Counter disabled 1: Counter operates in a multi-shot way. That is, counter loads with the Reload value STRVR.RELOAD and then begins counting down. On reaching 0, it sets COUNTFLAG to 1 and optionally pends the SysTick handler, based on TICKINT. It then loads STRVR.RELOAD again, and begins counting. | RW | 0

### TOP:CPU_SCS:STRVR

Address offset | 0x0000 0014
Physical address | 0xE000 E014 | Instance | CPU_SCS
Description | SysTick Reload Value Register This register is used to specify the start value to load into the current value register STCVR.CURRENT when the counter reaches 0. It can be any value between 1 and 0x00FFFFFF. A start value of 0 is possible, but has no effect because the SysTick interrupt and STCSR.COUNTFLAG are activated when counting from 1 to 0.
Type | RW

Bits | Field Name | Description | Type | Reset
31:24 | RESERVED24 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RW | 0x00
23:0 | RELOAD | Value to load into the SysTick Current Value Register STCVR.CURRENT when the counter reaches 0. | RW | 0x00 0000

### TOP:CPU_SCS:STCVR

Address offset | 0x0000 0018
Physical address | 0xE000 E018 | Instance | CPU_SCS
Description | SysTick Current Value Register Read from this register returns the current value of SysTick counter. Writing to this register resets the SysTick counter (as well as STCSR.COUNTFLAG).
Type | RW

Bits | Field Name | Description | Type | Reset
31:24 | RESERVED24 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RW | 0x00
23:0 | CURRENT | Current value at the time the register is accessed. No read-modify-write protection is provided, so change with care. Writing to it with any value clears the register to 0. Clearing this register also clears STCSR.COUNTFLAG. | RW | 0x00 0000

### TOP:CPU_SCS:STCR

Address offset | 0x0000 001C
Physical address | 0xE000 E01C | Instance | CPU_SCS
Description | SysTick Calibration Value Register Used to enable software to scale to any required speed using divide and multiply.
Type | RO

Bits | Field Name | Description | Type | Reset
31 | NOREF | Reads as one. Indicates that no separate reference clock is provided. | RO | 1
30 | SKEW | Reads as one. The calibration value is not exactly 10ms because of clock frequency. This could affect its suitability as a software real time clock. | RO | 1
29:24 | RESERVED24 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00
23:0 | TENMS | An optional Reload value to be used for 10ms (100Hz) timing, subject to system clock skew errors. The value read is valid only when core clock is at 48MHz. | RO | 0x07 5300

### TOP:CPU_SCS:NVIC_ISER0

Address offset | 0x0000 0100
Physical address | 0xE000 E100 | Instance | CPU_SCS
Description | Irq 0 to 31 Set Enable Register This register is used to enable interrupts and determine which interrupts are currently enabled.
Type | RW

Bits | Field Name | Description | Type | Reset
31 | SETENA31 | Writing 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 31 (See EVENT:CPUIRQSEL31.EV for details). Reading the bit returns its current enable state. | RW | 0
30 | SETENA30 | Writing 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 30 (See EVENT:CPUIRQSEL30.EV for details). Reading the bit returns its current enable state. | RW | 0
29 | SETENA29 | Writing 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 29 (See EVENT:CPUIRQSEL29.EV for details). Reading the bit returns its current enable state. | RW | 0
28 | SETENA28 | Writing 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 28 (See EVENT:CPUIRQSEL28.EV for details). Reading the bit returns its current enable state. | RW | 0
27 | SETENA27 | Writing 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 27 (See EVENT:CPUIRQSEL27.EV for details). Reading the bit returns its current enable state. | RW | 0
26 | SETENA26 | Writing 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 26 (See EVENT:CPUIRQSEL26.EV for details). Reading the bit returns its current enable state. | RW | 0
25 | SETENA25 | Writing 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 25 (See EVENT:CPUIRQSEL25.EV for details). Reading the bit returns its current enable state. | RW | 0
24 | SETENA24 | Writing 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 24 (See EVENT:CPUIRQSEL24.EV for details). Reading the bit returns its current enable state. | RW | 0
23 | SETENA23 | Writing 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 23 (See EVENT:CPUIRQSEL23.EV for details). Reading the bit returns its current enable state. | RW | 0
22 | SETENA22 | Writing 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 22 (See EVENT:CPUIRQSEL22.EV for details). Reading the bit returns its current enable state. | RW | 0
21 | SETENA21 | Writing 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 21 (See EVENT:CPUIRQSEL21.EV for details). Reading the bit returns its current enable state. | RW | 0
20 | SETENA20 | Writing 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 20 (See EVENT:CPUIRQSEL20.EV for details). Reading the bit returns its current enable state. | RW | 0
19 | SETENA19 | Writing 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 19 (See EVENT:CPUIRQSEL19.EV for details). Reading the bit returns its current enable state. | RW | 0
18 | SETENA18 | Writing 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 18 (See EVENT:CPUIRQSEL18.EV for details). Reading the bit returns its current enable state. | RW | 0
17 | SETENA17 | Writing 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 17 (See EVENT:CPUIRQSEL17.EV for details). Reading the bit returns its current enable state. | RW | 0
16 | SETENA16 | Writing 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 16 (See EVENT:CPUIRQSEL16.EV for details). Reading the bit returns its current enable state. | RW | 0
15 | SETENA15 | Writing 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 15 (See EVENT:CPUIRQSEL15.EV for details). Reading the bit returns its current enable state. | RW | 0
14 | SETENA14 | Writing 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 14 (See EVENT:CPUIRQSEL14.EV for details). Reading the bit returns its current enable state. | RW | 0
13 | SETENA13 | Writing 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 13 (See EVENT:CPUIRQSEL13.EV for details). Reading the bit returns its current enable state. | RW | 0
12 | SETENA12 | Writing 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 12 (See EVENT:CPUIRQSEL12.EV for details). Reading the bit returns its current enable state. | RW | 0
11 | SETENA11 | Writing 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 11 (See EVENT:CPUIRQSEL11.EV for details). Reading the bit returns its current enable state. | RW | 0
10 | SETENA10 | Writing 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 10 (See EVENT:CPUIRQSEL10.EV for details). Reading the bit returns its current enable state. | RW | 0
9 | SETENA9 | Writing 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 9 (See EVENT:CPUIRQSEL9.EV for details). Reading the bit returns its current enable state. | RW | 0
8 | SETENA8 | Writing 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 8 (See EVENT:CPUIRQSEL8.EV for details). Reading the bit returns its current enable state. | RW | 0
7 | SETENA7 | Writing 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 7 (See EVENT:CPUIRQSEL7.EV for details). Reading the bit returns its current enable state. | RW | 0
6 | SETENA6 | Writing 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 6 (See EVENT:CPUIRQSEL6.EV for details). Reading the bit returns its current enable state. | RW | 0
5 | SETENA5 | Writing 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 5 (See EVENT:CPUIRQSEL5.EV for details). Reading the bit returns its current enable state. | RW | 0
4 | SETENA4 | Writing 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 4 (See EVENT:CPUIRQSEL4.EV for details). Reading the bit returns its current enable state. | RW | 0
3 | SETENA3 | Writing 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 3 (See EVENT:CPUIRQSEL3.EV for details). Reading the bit returns its current enable state. | RW | 0
2 | SETENA2 | Writing 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 2 (See EVENT:CPUIRQSEL2.EV for details). Reading the bit returns its current enable state. | RW | 0
1 | SETENA1 | Writing 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 1 (See EVENT:CPUIRQSEL1.EV for details). Reading the bit returns its current enable state. | RW | 0
0 | SETENA0 | Writing 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 0 (See EVENT:CPUIRQSEL0.EV for details). Reading the bit returns its current enable state. | RW | 0

### TOP:CPU_SCS:NVIC_ISER1

Address offset | 0x0000 0104
Physical address | 0xE000 E104 | Instance | CPU_SCS
Description | Irq 32 to 63 Set Enable Register This register is used to enable interrupts and determine which interrupts are currently enabled.
Type | RW

Bits | Field Name | Description | Type | Reset
31:2 | RESERVED2 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RW | 0x0000 0000
1 | SETENA33 | Writing 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 33 (See EVENT:CPUIRQSEL33.EV for details). Reading the bit returns its current enable state. | RW | 0
0 | SETENA32 | Writing 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 32 (See EVENT:CPUIRQSEL32.EV for details). Reading the bit returns its current enable state. | RW | 0

### TOP:CPU_SCS:NVIC_ICER0

Address offset | 0x0000 0180
Physical address | 0xE000 E180 | Instance | CPU_SCS
Description | Irq 0 to 31 Clear Enable Register This register is used to disable interrupts and determine which interrupts are currently enabled.
Type | RW

Bits | Field Name | Description | Type | Reset
31 | CLRENA31 | Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 31 (See EVENT:CPUIRQSEL31.EV for details). Reading the bit returns its current enable state. | RW | 0
30 | CLRENA30 | Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 30 (See EVENT:CPUIRQSEL30.EV for details). Reading the bit returns its current enable state. | RW | 0
29 | CLRENA29 | Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 29 (See EVENT:CPUIRQSEL29.EV for details). Reading the bit returns its current enable state. | RW | 0
28 | CLRENA28 | Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 28 (See EVENT:CPUIRQSEL28.EV for details). Reading the bit returns its current enable state. | RW | 0
27 | CLRENA27 | Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 27 (See EVENT:CPUIRQSEL27.EV for details). Reading the bit returns its current enable state. | RW | 0
26 | CLRENA26 | Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 26 (See EVENT:CPUIRQSEL26.EV for details). Reading the bit returns its current enable state. | RW | 0
25 | CLRENA25 | Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 25 (See EVENT:CPUIRQSEL25.EV for details). Reading the bit returns its current enable state. | RW | 0
24 | CLRENA24 | Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 24 (See EVENT:CPUIRQSEL24.EV for details). Reading the bit returns its current enable state. | RW | 0
23 | CLRENA23 | Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 23 (See EVENT:CPUIRQSEL23.EV for details). Reading the bit returns its current enable state. | RW | 0
22 | CLRENA22 | Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 22 (See EVENT:CPUIRQSEL22.EV for details). Reading the bit returns its current enable state. | RW | 0
21 | CLRENA21 | Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 21 (See EVENT:CPUIRQSEL21.EV for details). Reading the bit returns its current enable state. | RW | 0
20 | CLRENA20 | Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 20 (See EVENT:CPUIRQSEL20.EV for details). Reading the bit returns its current enable state. | RW | 0
19 | CLRENA19 | Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 19 (See EVENT:CPUIRQSEL19.EV for details). Reading the bit returns its current enable state. | RW | 0
18 | CLRENA18 | Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 18 (See EVENT:CPUIRQSEL18.EV for details). Reading the bit returns its current enable state. | RW | 0
17 | CLRENA17 | Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 17 (See EVENT:CPUIRQSEL17.EV for details). Reading the bit returns its current enable state. | RW | 0
16 | CLRENA16 | Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 16 (See EVENT:CPUIRQSEL16.EV for details). Reading the bit returns its current enable state. | RW | 0
15 | CLRENA15 | Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 15 (See EVENT:CPUIRQSEL15.EV for details). Reading the bit returns its current enable state. | RW | 0
14 | CLRENA14 | Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 14 (See EVENT:CPUIRQSEL14.EV for details). Reading the bit returns its current enable state. | RW | 0
13 | CLRENA13 | Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 13 (See EVENT:CPUIRQSEL13.EV for details). Reading the bit returns its current enable state. | RW | 0
12 | CLRENA12 | Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 12 (See EVENT:CPUIRQSEL12.EV for details). Reading the bit returns its current enable state. | RW | 0
11 | CLRENA11 | Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 11 (See EVENT:CPUIRQSEL11.EV for details). Reading the bit returns its current enable state. | RW | 0
10 | CLRENA10 | Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 10 (See EVENT:CPUIRQSEL10.EV for details). Reading the bit returns its current enable state. | RW | 0
9 | CLRENA9 | Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 9 (See EVENT:CPUIRQSEL9.EV for details). Reading the bit returns its current enable state. | RW | 0
8 | CLRENA8 | Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 8 (See EVENT:CPUIRQSEL8.EV for details). Reading the bit returns its current enable state. | RW | 0
7 | CLRENA7 | Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 7 (See EVENT:CPUIRQSEL7.EV for details). Reading the bit returns its current enable state. | RW | 0
6 | CLRENA6 | Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 6 (See EVENT:CPUIRQSEL6.EV for details). Reading the bit returns its current enable state. | RW | 0
5 | CLRENA5 | Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 5 (See EVENT:CPUIRQSEL5.EV for details). Reading the bit returns its current enable state. | RW | 0
4 | CLRENA4 | Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 4 (See EVENT:CPUIRQSEL4.EV for details). Reading the bit returns its current enable state. | RW | 0
3 | CLRENA3 | Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 3 (See EVENT:CPUIRQSEL3.EV for details). Reading the bit returns its current enable state. | RW | 0
2 | CLRENA2 | Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 2 (See EVENT:CPUIRQSEL2.EV for details). Reading the bit returns its current enable state. | RW | 0
1 | CLRENA1 | Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 1 (See EVENT:CPUIRQSEL1.EV for details). Reading the bit returns its current enable state. | RW | 0
0 | CLRENA0 | Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 0 (See EVENT:CPUIRQSEL0.EV for details). Reading the bit returns its current enable state. | RW | 0

### TOP:CPU_SCS:NVIC_ICER1

Address offset | 0x0000 0184
Physical address | 0xE000 E184 | Instance | CPU_SCS
Description | Irq 32 to 63 Clear Enable Register This register is used to disable interrupts and determine which interrupts are currently enabled.
Type | RW

Bits | Field Name | Description | Type | Reset
31:2 | RESERVED2 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RW | 0x0000 0000
1 | CLRENA33 | Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 33 (See EVENT:CPUIRQSEL33.EV for details). Reading the bit returns its current enable state. | RW | 0
0 | CLRENA32 | Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 32 (See EVENT:CPUIRQSEL32.EV for details). Reading the bit returns its current enable state. | RW | 0

### TOP:CPU_SCS:NVIC_ISPR0

Address offset | 0x0000 0200
Physical address | 0xE000 E200 | Instance | CPU_SCS
Description | Irq 0 to 31 Set Pending Register This register is used to force interrupts into the pending state and determine which interrupts are currently pending.
Type | RW

Bits | Field Name | Description | Type | Reset
31 | SETPEND31 | Writing 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 31 (See EVENT:CPUIRQSEL31.EV for details). Reading the bit returns its current state. | RW | 0
30 | SETPEND30 | Writing 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 30 (See EVENT:CPUIRQSEL30.EV for details). Reading the bit returns its current state. | RW | 0
29 | SETPEND29 | Writing 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 29 (See EVENT:CPUIRQSEL29.EV for details). Reading the bit returns its current state. | RW | 0
28 | SETPEND28 | Writing 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 28 (See EVENT:CPUIRQSEL28.EV for details). Reading the bit returns its current state. | RW | 0
27 | SETPEND27 | Writing 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 27 (See EVENT:CPUIRQSEL27.EV for details). Reading the bit returns its current state. | RW | 0
26 | SETPEND26 | Writing 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 26 (See EVENT:CPUIRQSEL26.EV for details). Reading the bit returns its current state. | RW | 0
25 | SETPEND25 | Writing 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 25 (See EVENT:CPUIRQSEL25.EV for details). Reading the bit returns its current state. | RW | 0
24 | SETPEND24 | Writing 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 24 (See EVENT:CPUIRQSEL24.EV for details). Reading the bit returns its current state. | RW | 0
23 | SETPEND23 | Writing 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 23 (See EVENT:CPUIRQSEL23.EV for details). Reading the bit returns its current state. | RW | 0
22 | SETPEND22 | Writing 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 22 (See EVENT:CPUIRQSEL22.EV for details). Reading the bit returns its current state. | RW | 0
21 | SETPEND21 | Writing 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 21 (See EVENT:CPUIRQSEL21.EV for details). Reading the bit returns its current state. | RW | 0
20 | SETPEND20 | Writing 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 20 (See EVENT:CPUIRQSEL20.EV for details). Reading the bit returns its current state. | RW | 0
19 | SETPEND19 | Writing 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 19 (See EVENT:CPUIRQSEL19.EV for details). Reading the bit returns its current state. | RW | 0
18 | SETPEND18 | Writing 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 18 (See EVENT:CPUIRQSEL18.EV for details). Reading the bit returns its current state. | RW | 0
17 | SETPEND17 | Writing 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 17 (See EVENT:CPUIRQSEL17.EV for details). Reading the bit returns its current state. | RW | 0
16 | SETPEND16 | Writing 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 16 (See EVENT:CPUIRQSEL16.EV for details). Reading the bit returns its current state. | RW | 0
15 | SETPEND15 | Writing 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 15 (See EVENT:CPUIRQSEL15.EV for details). Reading the bit returns its current state. | RW | 0
14 | SETPEND14 | Writing 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 14 (See EVENT:CPUIRQSEL14.EV for details). Reading the bit returns its current state. | RW | 0
13 | SETPEND13 | Writing 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 13 (See EVENT:CPUIRQSEL13.EV for details). Reading the bit returns its current state. | RW | 0
12 | SETPEND12 | Writing 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 12 (See EVENT:CPUIRQSEL12.EV for details). Reading the bit returns its current state. | RW | 0
11 | SETPEND11 | Writing 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 11 (See EVENT:CPUIRQSEL11.EV for details). Reading the bit returns its current state. | RW | 0
10 | SETPEND10 | Writing 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 10 (See EVENT:CPUIRQSEL10.EV for details). Reading the bit returns its current state. | RW | 0
9 | SETPEND9 | Writing 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 9 (See EVENT:CPUIRQSEL9.EV for details). Reading the bit returns its current state. | RW | 0
8 | SETPEND8 | Writing 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 8 (See EVENT:CPUIRQSEL8.EV for details). Reading the bit returns its current state. | RW | 0
7 | SETPEND7 | Writing 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 7 (See EVENT:CPUIRQSEL7.EV for details). Reading the bit returns its current state. | RW | 0
6 | SETPEND6 | Writing 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 6 (See EVENT:CPUIRQSEL6.EV for details). Reading the bit returns its current state. | RW | 0
5 | SETPEND5 | Writing 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 5 (See EVENT:CPUIRQSEL5.EV for details). Reading the bit returns its current state. | RW | 0
4 | SETPEND4 | Writing 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 4 (See EVENT:CPUIRQSEL4.EV for details). Reading the bit returns its current state. | RW | 0
3 | SETPEND3 | Writing 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 3 (See EVENT:CPUIRQSEL3.EV for details). Reading the bit returns its current state. | RW | 0
2 | SETPEND2 | Writing 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 2 (See EVENT:CPUIRQSEL2.EV for details). Reading the bit returns its current state. | RW | 0
1 | SETPEND1 | Writing 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 1 (See EVENT:CPUIRQSEL1.EV for details). Reading the bit returns its current state. | RW | 0
0 | SETPEND0 | Writing 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 0 (See EVENT:CPUIRQSEL0.EV for details). Reading the bit returns its current state. | RW | 0

### TOP:CPU_SCS:NVIC_ISPR1

Address offset | 0x0000 0204
Physical address | 0xE000 E204 | Instance | CPU_SCS
Description | Irq 32 to 63 Set Pending Register This register is used to force interrupts into the pending state and determine which interrupts are currently pending.
Type | RW

Bits | Field Name | Description | Type | Reset
31:2 | RESERVED2 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RW | 0x0000 0000
1 | SETPEND33 | Writing 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 33 (See EVENT:CPUIRQSEL33.EV for details). Reading the bit returns its current state. | RW | 0
0 | SETPEND32 | Writing 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 32 (See EVENT:CPUIRQSEL32.EV for details). Reading the bit returns its current state. | RW | 0

### TOP:CPU_SCS:NVIC_ICPR0

Address offset | 0x0000 0280
Physical address | 0xE000 E280 | Instance | CPU_SCS
Description | Irq 0 to 31 Clear Pending Register This register is used to clear pending interrupts and determine which interrupts are currently pending.
Type | RW

Bits | Field Name | Description | Type | Reset
31 | CLRPEND31 | Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 31 (See EVENT:CPUIRQSEL31.EV for details). Reading the bit returns its current state. | RW | 0
30 | CLRPEND30 | Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 30 (See EVENT:CPUIRQSEL30.EV for details). Reading the bit returns its current state. | RW | 0
29 | CLRPEND29 | Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 29 (See EVENT:CPUIRQSEL29.EV for details). Reading the bit returns its current state. | RW | 0
28 | CLRPEND28 | Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 28 (See EVENT:CPUIRQSEL28.EV for details). Reading the bit returns its current state. | RW | 0
27 | CLRPEND27 | Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 27 (See EVENT:CPUIRQSEL27.EV for details). Reading the bit returns its current state. | RW | 0
26 | CLRPEND26 | Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 26 (See EVENT:CPUIRQSEL26.EV for details). Reading the bit returns its current state. | RW | 0
25 | CLRPEND25 | Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 25 (See EVENT:CPUIRQSEL25.EV for details). Reading the bit returns its current state. | RW | 0
24 | CLRPEND24 | Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 24 (See EVENT:CPUIRQSEL24.EV for details). Reading the bit returns its current state. | RW | 0
23 | CLRPEND23 | Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 23 (See EVENT:CPUIRQSEL23.EV for details). Reading the bit returns its current state. | RW | 0
22 | CLRPEND22 | Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 22 (See EVENT:CPUIRQSEL22.EV for details). Reading the bit returns its current state. | RW | 0
21 | CLRPEND21 | Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 21 (See EVENT:CPUIRQSEL21.EV for details). Reading the bit returns its current state. | RW | 0
20 | CLRPEND20 | Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 20 (See EVENT:CPUIRQSEL20.EV for details). Reading the bit returns its current state. | RW | 0
19 | CLRPEND19 | Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 19 (See EVENT:CPUIRQSEL19.EV for details). Reading the bit returns its current state. | RW | 0
18 | CLRPEND18 | Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 18 (See EVENT:CPUIRQSEL18.EV for details). Reading the bit returns its current state. | RW | 0
17 | CLRPEND17 | Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 17 (See EVENT:CPUIRQSEL17.EV for details). Reading the bit returns its current state. | RW | 0
16 | CLRPEND16 | Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 16 (See EVENT:CPUIRQSEL16.EV for details). Reading the bit returns its current state. | RW | 0
15 | CLRPEND15 | Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 15 (See EVENT:CPUIRQSEL15.EV for details). Reading the bit returns its current state. | RW | 0
14 | CLRPEND14 | Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 14 (See EVENT:CPUIRQSEL14.EV for details). Reading the bit returns its current state. | RW | 0
13 | CLRPEND13 | Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 13 (See EVENT:CPUIRQSEL13.EV for details). Reading the bit returns its current state. | RW | 0
12 | CLRPEND12 | Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 12 (See EVENT:CPUIRQSEL12.EV for details). Reading the bit returns its current state. | RW | 0
11 | CLRPEND11 | Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 11 (See EVENT:CPUIRQSEL11.EV for details). Reading the bit returns its current state. | RW | 0
10 | CLRPEND10 | Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 10 (See EVENT:CPUIRQSEL10.EV for details). Reading the bit returns its current state. | RW | 0
9 | CLRPEND9 | Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 9 (See EVENT:CPUIRQSEL9.EV for details). Reading the bit returns its current state. | RW | 0
8 | CLRPEND8 | Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 8 (See EVENT:CPUIRQSEL8.EV for details). Reading the bit returns its current state. | RW | 0
7 | CLRPEND7 | Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 7 (See EVENT:CPUIRQSEL7.EV for details). Reading the bit returns its current state. | RW | 0
6 | CLRPEND6 | Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 6 (See EVENT:CPUIRQSEL6.EV for details). Reading the bit returns its current state. | RW | 0
5 | CLRPEND5 | Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 5 (See EVENT:CPUIRQSEL5.EV for details). Reading the bit returns its current state. | RW | 0
4 | CLRPEND4 | Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 4 (See EVENT:CPUIRQSEL4.EV for details). Reading the bit returns its current state. | RW | 0
3 | CLRPEND3 | Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 3 (See EVENT:CPUIRQSEL3.EV for details). Reading the bit returns its current state. | RW | 0
2 | CLRPEND2 | Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 2 (See EVENT:CPUIRQSEL2.EV for details). Reading the bit returns its current state. | RW | 0
1 | CLRPEND1 | Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 1 (See EVENT:CPUIRQSEL1.EV for details). Reading the bit returns its current state. | RW | 0
0 | CLRPEND0 | Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 0 (See EVENT:CPUIRQSEL0.EV for details). Reading the bit returns its current state. | RW | 0

### TOP:CPU_SCS:NVIC_ICPR1

Address offset | 0x0000 0284
Physical address | 0xE000 E284 | Instance | CPU_SCS
Description | Irq 32 to 63 Clear Pending Register This register is used to clear pending interrupts and determine which interrupts are currently pending.
Type | RW

Bits | Field Name | Description | Type | Reset
31:2 | RESERVED2 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RW | 0x0000 0000
1 | CLRPEND33 | Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 33 (See EVENT:CPUIRQSEL33.EV for details). Reading the bit returns its current state. | RW | 0
0 | CLRPEND32 | Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 32 (See EVENT:CPUIRQSEL32.EV for details). Reading the bit returns its current state. | RW | 0

### TOP:CPU_SCS:NVIC_IABR0

Address offset | 0x0000 0300
Physical address | 0xE000 E300 | Instance | CPU_SCS
Description | Irq 0 to 31 Active Bit Register This register is used to determine which interrupts are active. Each flag in the register corresponds to one interrupt.
Type | RO

Bits | Field Name | Description | Type | Reset
31 | ACTIVE31 | Reading 0 from this bit implies that interrupt line 31 is not active. Reading 1 from this bit implies that the interrupt line 31 is active (See EVENT:CPUIRQSEL31.EV for details). | RO | 0
30 | ACTIVE30 | Reading 0 from this bit implies that interrupt line 30 is not active. Reading 1 from this bit implies that the interrupt line 30 is active (See EVENT:CPUIRQSEL30.EV for details). | RO | 0
29 | ACTIVE29 | Reading 0 from this bit implies that interrupt line 29 is not active. Reading 1 from this bit implies that the interrupt line 29 is active (See EVENT:CPUIRQSEL29.EV for details). | RO | 0
28 | ACTIVE28 | Reading 0 from this bit implies that interrupt line 28 is not active. Reading 1 from this bit implies that the interrupt line 28 is active (See EVENT:CPUIRQSEL28.EV for details). | RO | 0
27 | ACTIVE27 | Reading 0 from this bit implies that interrupt line 27 is not active. Reading 1 from this bit implies that the interrupt line 27 is active (See EVENT:CPUIRQSEL27.EV for details). | RO | 0
26 | ACTIVE26 | Reading 0 from this bit implies that interrupt line 26 is not active. Reading 1 from this bit implies that the interrupt line 26 is active (See EVENT:CPUIRQSEL26.EV for details). | RO | 0
25 | ACTIVE25 | Reading 0 from this bit implies that interrupt line 25 is not active. Reading 1 from this bit implies that the interrupt line 25 is active (See EVENT:CPUIRQSEL25.EV for details). | RO | 0
24 | ACTIVE24 | Reading 0 from this bit implies that interrupt line 24 is not active. Reading 1 from this bit implies that the interrupt line 24 is active (See EVENT:CPUIRQSEL24.EV for details). | RO | 0
23 | ACTIVE23 | Reading 0 from this bit implies that interrupt line 23 is not active. Reading 1 from this bit implies that the interrupt line 23 is active (See EVENT:CPUIRQSEL23.EV for details). | RO | 0
22 | ACTIVE22 | Reading 0 from this bit implies that interrupt line 22 is not active. Reading 1 from this bit implies that the interrupt line 22 is active (See EVENT:CPUIRQSEL22.EV for details). | RO | 0
21 | ACTIVE21 | Reading 0 from this bit implies that interrupt line 21 is not active. Reading 1 from this bit implies that the interrupt line 21 is active (See EVENT:CPUIRQSEL21.EV for details). | RO | 0
20 | ACTIVE20 | Reading 0 from this bit implies that interrupt line 20 is not active. Reading 1 from this bit implies that the interrupt line 20 is active (See EVENT:CPUIRQSEL20.EV for details). | RO | 0
19 | ACTIVE19 | Reading 0 from this bit implies that interrupt line 19 is not active. Reading 1 from this bit implies that the interrupt line 19 is active (See EVENT:CPUIRQSEL19.EV for details). | RO | 0
18 | ACTIVE18 | Reading 0 from this bit implies that interrupt line 18 is not active. Reading 1 from this bit implies that the interrupt line 18 is active (See EVENT:CPUIRQSEL18.EV for details). | RO | 0
17 | ACTIVE17 | Reading 0 from this bit implies that interrupt line 17 is not active. Reading 1 from this bit implies that the interrupt line 17 is active (See EVENT:CPUIRQSEL17.EV for details). | RO | 0
16 | ACTIVE16 | Reading 0 from this bit implies that interrupt line 16 is not active. Reading 1 from this bit implies that the interrupt line 16 is active (See EVENT:CPUIRQSEL16.EV for details). | RO | 0
15 | ACTIVE15 | Reading 0 from this bit implies that interrupt line 15 is not active. Reading 1 from this bit implies that the interrupt line 15 is active (See EVENT:CPUIRQSEL15.EV for details). | RO | 0
14 | ACTIVE14 | Reading 0 from this bit implies that interrupt line 14 is not active. Reading 1 from this bit implies that the interrupt line 14 is active (See EVENT:CPUIRQSEL14.EV for details). | RO | 0
13 | ACTIVE13 | Reading 0 from this bit implies that interrupt line 13 is not active. Reading 1 from this bit implies that the interrupt line 13 is active (See EVENT:CPUIRQSEL13.EV for details). | RO | 0
12 | ACTIVE12 | Reading 0 from this bit implies that interrupt line 12 is not active. Reading 1 from this bit implies that the interrupt line 12 is active (See EVENT:CPUIRQSEL12.EV for details). | RO | 0
11 | ACTIVE11 | Reading 0 from this bit implies that interrupt line 11 is not active. Reading 1 from this bit implies that the interrupt line 11 is active (See EVENT:CPUIRQSEL11.EV for details). | RO | 0
10 | ACTIVE10 | Reading 0 from this bit implies that interrupt line 10 is not active. Reading 1 from this bit implies that the interrupt line 10 is active (See EVENT:CPUIRQSEL10.EV for details). | RO | 0
9 | ACTIVE9 | Reading 0 from this bit implies that interrupt line 9 is not active. Reading 1 from this bit implies that the interrupt line 9 is active (See EVENT:CPUIRQSEL9.EV for details). | RO | 0
8 | ACTIVE8 | Reading 0 from this bit implies that interrupt line 8 is not active. Reading 1 from this bit implies that the interrupt line 8 is active (See EVENT:CPUIRQSEL8.EV for details). | RO | 0
7 | ACTIVE7 | Reading 0 from this bit implies that interrupt line 7 is not active. Reading 1 from this bit implies that the interrupt line 7 is active (See EVENT:CPUIRQSEL7.EV for details). | RO | 0
6 | ACTIVE6 | Reading 0 from this bit implies that interrupt line 6 is not active. Reading 1 from this bit implies that the interrupt line 6 is active (See EVENT:CPUIRQSEL6.EV for details). | RO | 0
5 | ACTIVE5 | Reading 0 from this bit implies that interrupt line 5 is not active. Reading 1 from this bit implies that the interrupt line 5 is active (See EVENT:CPUIRQSEL5.EV for details). | RO | 0
4 | ACTIVE4 | Reading 0 from this bit implies that interrupt line 4 is not active. Reading 1 from this bit implies that the interrupt line 4 is active (See EVENT:CPUIRQSEL4.EV for details). | RO | 0
3 | ACTIVE3 | Reading 0 from this bit implies that interrupt line 3 is not active. Reading 1 from this bit implies that the interrupt line 3 is active (See EVENT:CPUIRQSEL3.EV for details). | RO | 0
2 | ACTIVE2 | Reading 0 from this bit implies that interrupt line 2 is not active. Reading 1 from this bit implies that the interrupt line 2 is active (See EVENT:CPUIRQSEL2.EV for details). | RO | 0
1 | ACTIVE1 | Reading 0 from this bit implies that interrupt line 1 is not active. Reading 1 from this bit implies that the interrupt line 1 is active (See EVENT:CPUIRQSEL1.EV for details). | RO | 0
0 | ACTIVE0 | Reading 0 from this bit implies that interrupt line 0 is not active. Reading 1 from this bit implies that the interrupt line 0 is active (See EVENT:CPUIRQSEL0.EV for details). | RO | 0

### TOP:CPU_SCS:NVIC_IABR1

Address offset | 0x0000 0304
Physical address | 0xE000 E304 | Instance | CPU_SCS
Description | Irq 32 to 63 Active Bit Register This register is used to determine which interrupts are active. Each flag in the register corresponds to one interrupt.
Type | RO

Bits | Field Name | Description | Type | Reset
31:2 | RESERVED2 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0000 0000
1 | ACTIVE33 | Reading 0 from this bit implies that interrupt line 33 is not active. Reading 1 from this bit implies that the interrupt line 33 is active (See EVENT:CPUIRQSEL33.EV for details). | RO | 0
0 | ACTIVE32 | Reading 0 from this bit implies that interrupt line 32 is not active. Reading 1 from this bit implies that the interrupt line 32 is active (See EVENT:CPUIRQSEL32.EV for details). | RO | 0

### TOP:CPU_SCS:NVIC_IPR0

Address offset | 0x0000 0400
Physical address | 0xE000 E400 | Instance | CPU_SCS
Description | Irq 0 to 3 Priority Register This register is used to assign a priority from 0 to 255 to each of the available interrupts. 0 is the highest priority, and 255 is the lowest. The interpretation of the Interrupt Priority Registers changes based on the setting in AIRCR.PRIGROUP.
Type | RW

Bits | Field Name | Description | Type | Reset
31:24 | PRI_3 | Priority of interrupt 3 (See EVENT:CPUIRQSEL3.EV for details). | RW | 0x00
23:16 | PRI_2 | Priority of interrupt 2 (See EVENT:CPUIRQSEL2.EV for details). | RW | 0x00
15:8 | PRI_1 | Priority of interrupt 1 (See EVENT:CPUIRQSEL1.EV for details). | RW | 0x00
7:0 | PRI_0 | Priority of interrupt 0 (See EVENT:CPUIRQSEL0.EV for details). | RW | 0x00

### TOP:CPU_SCS:NVIC_IPR1

Address offset | 0x0000 0404
Physical address | 0xE000 E404 | Instance | CPU_SCS
Description | Irq 4 to 7 Priority Register This register is used to assign a priority from 0 to 255 to each of the available interrupts. 0 is the highest priority, and 255 is the lowest. The interpretation of the Interrupt Priority Registers changes based on the setting in AIRCR.PRIGROUP.
Type | RW

Bits | Field Name | Description | Type | Reset
31:24 | PRI_7 | Priority of interrupt 7 (See EVENT:CPUIRQSEL7.EV for details). | RW | 0x00
23:16 | PRI_6 | Priority of interrupt 6 (See EVENT:CPUIRQSEL6.EV for details). | RW | 0x00
15:8 | PRI_5 | Priority of interrupt 5 (See EVENT:CPUIRQSEL5.EV for details). | RW | 0x00
7:0 | PRI_4 | Priority of interrupt 4 (See EVENT:CPUIRQSEL4.EV for details). | RW | 0x00

### TOP:CPU_SCS:NVIC_IPR2

Address offset | 0x0000 0408
Physical address | 0xE000 E408 | Instance | CPU_SCS
Description | Irq 8 to 11 Priority Register This register is used to assign a priority from 0 to 255 to each of the available interrupts. 0 is the highest priority, and 255 is the lowest. The interpretation of the Interrupt Priority Registers changes based on the setting in AIRCR.PRIGROUP.
Type | RW

Bits | Field Name | Description | Type | Reset
31:24 | PRI_11 | Priority of interrupt 11 (See EVENT:CPUIRQSEL11.EV for details). | RW | 0x00
23:16 | PRI_10 | Priority of interrupt 10 (See EVENT:CPUIRQSEL10.EV for details). | RW | 0x00
15:8 | PRI_9 | Priority of interrupt 9 (See EVENT:CPUIRQSEL9.EV for details). | RW | 0x00
7:0 | PRI_8 | Priority of interrupt 8 (See EVENT:CPUIRQSEL8.EV for details). | RW | 0x00

### TOP:CPU_SCS:NVIC_IPR3

Address offset | 0x0000 040C
Physical address | 0xE000 E40C | Instance | CPU_SCS
Description | Irq 12 to 15 Priority Register This register is used to assign a priority from 0 to 255 to each of the available interrupts. 0 is the highest priority, and 255 is the lowest. The interpretation of the Interrupt Priority Registers changes based on the setting in AIRCR.PRIGROUP.
Type | RW

Bits | Field Name | Description | Type | Reset
31:24 | PRI_15 | Priority of interrupt 15 (See EVENT:CPUIRQSEL15.EV for details). | RW | 0x00
23:16 | PRI_14 | Priority of interrupt 14 (See EVENT:CPUIRQSEL14.EV for details). | RW | 0x00
15:8 | PRI_13 | Priority of interrupt 13 (See EVENT:CPUIRQSEL13.EV for details). | RW | 0x00
7:0 | PRI_12 | Priority of interrupt 12 (See EVENT:CPUIRQSEL12.EV for details). | RW | 0x00

### TOP:CPU_SCS:NVIC_IPR4

Address offset | 0x0000 0410
Physical address | 0xE000 E410 | Instance | CPU_SCS
Description | Irq 16 to 19 Priority Register This register is used to assign a priority from 0 to 255 to each of the available interrupts. 0 is the highest priority, and 255 is the lowest. The interpretation of the Interrupt Priority Registers changes based on the setting in AIRCR.PRIGROUP.
Type | RW

Bits | Field Name | Description | Type | Reset
31:24 | PRI_19 | Priority of interrupt 19 (See EVENT:CPUIRQSEL19.EV for details). | RW | 0x00
23:16 | PRI_18 | Priority of interrupt 18 (See EVENT:CPUIRQSEL18.EV for details). | RW | 0x00
15:8 | PRI_17 | Priority of interrupt 17 (See EVENT:CPUIRQSEL17.EV for details). | RW | 0x00
7:0 | PRI_16 | Priority of interrupt 16 (See EVENT:CPUIRQSEL16.EV for details). | RW | 0x00

### TOP:CPU_SCS:NVIC_IPR5

Address offset | 0x0000 0414
Physical address | 0xE000 E414 | Instance | CPU_SCS
Description | Irq 20 to 23 Priority Register This register is used to assign a priority from 0 to 255 to each of the available interrupts. 0 is the highest priority, and 255 is the lowest. The interpretation of the Interrupt Priority Registers changes based on the setting in AIRCR.PRIGROUP.
Type | RW

Bits | Field Name | Description | Type | Reset
31:24 | PRI_23 | Priority of interrupt 23 (See EVENT:CPUIRQSEL23.EV for details). | RW | 0x00
23:16 | PRI_22 | Priority of interrupt 22 (See EVENT:CPUIRQSEL22.EV for details). | RW | 0x00
15:8 | PRI_21 | Priority of interrupt 21 (See EVENT:CPUIRQSEL21.EV for details). | RW | 0x00
7:0 | PRI_20 | Priority of interrupt 20 (See EVENT:CPUIRQSEL20.EV for details). | RW | 0x00

### TOP:CPU_SCS:NVIC_IPR6

Address offset | 0x0000 0418
Physical address | 0xE000 E418 | Instance | CPU_SCS
Description | Irq 24 to 27 Priority Register This register is used to assign a priority from 0 to 255 to each of the available interrupts. 0 is the highest priority, and 255 is the lowest. The interpretation of the Interrupt Priority Registers changes based on the setting in AIRCR.PRIGROUP.
Type | RW

Bits | Field Name | Description | Type | Reset
31:24 | PRI_27 | Priority of interrupt 27 (See EVENT:CPUIRQSEL27.EV for details). | RW | 0x00
23:16 | PRI_26 | Priority of interrupt 26 (See EVENT:CPUIRQSEL26.EV for details). | RW | 0x00
15:8 | PRI_25 | Priority of interrupt 25 (See EVENT:CPUIRQSEL25.EV for details). | RW | 0x00
7:0 | PRI_24 | Priority of interrupt 24 (See EVENT:CPUIRQSEL24.EV for details). | RW | 0x00

### TOP:CPU_SCS:NVIC_IPR7

Address offset | 0x0000 041C
Physical address | 0xE000 E41C | Instance | CPU_SCS
Description | Irq 28 to 31 Priority Register This register is used to assign a priority from 0 to 255 to each of the available interrupts. 0 is the highest priority, and 255 is the lowest. The interpretation of the Interrupt Priority Registers changes based on the setting in AIRCR.PRIGROUP.
Type | RW

Bits | Field Name | Description | Type | Reset
31:24 | PRI_31 | Priority of interrupt 31 (See EVENT:CPUIRQSEL31.EV for details). | RW | 0x00
23:16 | PRI_30 | Priority of interrupt 30 (See EVENT:CPUIRQSEL30.EV for details). | RW | 0x00
15:8 | PRI_29 | Priority of interrupt 29 (See EVENT:CPUIRQSEL29.EV for details). | RW | 0x00
7:0 | PRI_28 | Priority of interrupt 28 (See EVENT:CPUIRQSEL28.EV for details). | RW | 0x00

### TOP:CPU_SCS:NVIC_IPR8

Address offset | 0x0000 0420
Physical address | 0xE000 E420 | Instance | CPU_SCS
Description | Irq 32 to 35 Priority Register This register is used to assign a priority from 0 to 255 to each of the available interrupts. 0 is the highest priority, and 255 is the lowest. The interpretation of the Interrupt Priority Registers changes based on the setting in AIRCR.PRIGROUP.
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | RESERVED16 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RW | 0x0000
15:8 | PRI_33 | Priority of interrupt 33 (See EVENT:CPUIRQSEL33.EV for details). | RW | 0x00
7:0 | PRI_32 | Priority of interrupt 32 (See EVENT:CPUIRQSEL32.EV for details). | RW | 0x00

### TOP:CPU_SCS:CPUID

Address offset | 0x0000 0D00
Physical address | 0xE000 ED00 | Instance | CPU_SCS
Description | CPUID Base Register This register determines the ID number of the processor core, the version number of the processor core and the implementation details of the processor core.
Type | RO

Bits | Field Name | Description | Type | Reset
31:24 | IMPLEMENTER | Implementor code. | RO | 0x41
23:20 | VARIANT | Implementation defined variant number. | RO | 0x2
19:16 | CONSTANT | Reads as 0xF | RO | 0xF
15:4 | PARTNO | Number of processor within family. | RO | 0xC23
3:0 | REVISION | Implementation defined revision number. | RO | 0x1

### TOP:CPU_SCS:ICSR

Address offset | 0x0000 0D04
Physical address | 0xE000 ED04 | Instance | CPU_SCS
Description | Interrupt Control State Register This register is used to set a pending Non-Maskable Interrupt (NMI), set or clear a pending SVC, set or clear a pending SysTick, check for pending exceptions, check the vector number of the highest priority pended exception, and check the vector number of the active exception.
Type | RW

Bits | Field Name | Description | Type | Reset
31 | NMIPENDSET | Set pending NMI bit. Setting this bit pends and activates an NMI. Because NMI is the highest-priority interrupt, it takes effect as soon as it registers. 0: No action 1: Set pending NMI | RW | 0
30:29 | RESERVED29 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RW | 0x0
28 | PENDSVSET | Set pending pendSV bit. 0: No action 1: Set pending PendSV | RW | 0
27 | PENDSVCLR | Clear pending pendSV bit 0: No action 1: Clear pending pendSV | WO | 0
26 | PENDSTSET | Set a pending SysTick bit. 0: No action 1: Set pending SysTick | RW | 0
25 | PENDSTCLR | Clear pending SysTick bit 0: No action 1: Clear pending SysTick | WO | 0
24 | RESERVED24 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0
23 | ISRPREEMPT | This field can only be used at debug time. It indicates that a pending interrupt is to be taken in the next running cycle. If DHCSR.C_MASKINTS= 0, the interrupt is serviced. 0: A pending exception is not serviced. 1: A pending exception is serviced on exit from the debug halt state | RO | 0
22 | ISRPENDING | Interrupt pending flag. Excludes NMI and faults. 0x0: Interrupt not pending 0x1: Interrupt pending | RO | 0
21:18 | RESERVED18 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0
17:12 | VECTPENDING | Pending ISR number field. This field contains the interrupt number of the highest priority pending ISR. | RO | 0x00
11 | RETTOBASE | Indicates whether there are preempted active exceptions: 0: There are preempted active exceptions to execute 1: There are no active exceptions, or the currently-executing exception is the only active exception. | RO | 0
10:9 | RESERVED9 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0
8:0 | VECTACTIVE | Active ISR number field. Reset clears this field. | RO | 0x000

### TOP:CPU_SCS:VTOR

Address offset | 0x0000 0D08
Physical address | 0xE000 ED08 | Instance | CPU_SCS
Description | Vector Table Offset Register This register is used to relocated the vector table base address. The vector table base offset determines the offset from the bottom of the memory map. The two most significant bits and the seven least significant bits of the vector table base offset must be 0. The portion of vector table base offset that is allowed to change is TBLOFF.
Type | RW

Bits | Field Name | Description | Type | Reset
31:30 | RESERVED30 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RW | 0x0
29:7 | TBLOFF | Bits 29 down to 7 of the vector table base offset. | RW | 0x00 0000
6:0 | RESERVED0 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RW | 0x00

### TOP:CPU_SCS:AIRCR

Address offset | 0x0000 0D0C
Physical address | 0xE000 ED0C | Instance | CPU_SCS
Description | Application Interrupt/Reset Control Register This register is used to determine data endianness, clear all active state information for debug or to recover from a hard failure, execute a system reset, alter the priority grouping position (binary point).
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | VECTKEY | Register key. Writing to this register (AIRCR) requires 0x05FA in VECTKEY. Otherwise the write value is ignored. Read always returns 0xFA05. | RW | 0xFA05
15 | ENDIANESS | Data endianness bit
Value | ENUM name | Description
0 | LITTLE | Little endian
1 | BIG | Big endian
| RO | 0
14:11 | RESERVED11 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0
10:8 | PRIGROUP | Interrupt priority grouping field. This field is a binary point position indicator for creating subpriorities for exceptions that share the same pre-emption level. It divides the PRI_n field in the Interrupt Priority Registers (NVIC_IPR0, NVIC_IPR1,..., and NVIC_IPR8) into a pre-emption level and a subpriority level. The binary point is a left-of value. This means that the PRIGROUP value represents a point starting at the left of the Least Significant Bit (LSB). The lowest value might not be 0 depending on the number of bits allocated for priorities, and implementation choices. | RW | 0x0
7:3 | RESERVED3 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RW | 0x00
2 | SYSRESETREQ | Requests a warm reset. Setting this bit does not prevent Halting Debug from running. | WO | 0
1 | VECTCLRACTIVE | Clears all active state information for active NMI, fault, and interrupts. It is the responsibility of the application to reinitialize the stack. This bit is for returning to a known state during debug. The bit self-clears. IPSR is not cleared by this operation. So, if used by an application, it must only be used at the base level of activation, or within a system handler whose active bit can be set. | WO | 0
0 | VECTRESET | System Reset bit. Resets the system, with the exception of debug components. This bit is reserved for debug use and can be written to 1 only when the core is halted. The bit self-clears. Writing this bit to 1 while core is not halted may result in unpredictable behavior. | WO | 0

### TOP:CPU_SCS:SCR

Address offset | 0x0000 0D10
Physical address | 0xE000 ED10 | Instance | CPU_SCS
Description | System Control Register This register is used for power-management functions, i.e., signaling to the system when the processor can enter a low power state, controlling how the processor enters and exits low power states.
Type | RW

Bits | Field Name | Description | Type | Reset
31:5 | RESERVED5 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RW | 0x000 0000
4 | SEVONPEND | Send Event on Pending bit: 0: Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded 1: Enabled events and all interrupts, including disabled interrupts, can wakeup the processor. When an event or interrupt enters pending state, the event signal wakes up the processor from WFE. If the processor is not waiting for an event, the event is registered and affects the next WFE. The processor also wakes up on execution of an SEV instruction. | RW | 0
3 | RESERVED3 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RW | 0
2 | SLEEPDEEP | Controls whether the processor uses sleep or deep sleep as its low power mode
Value | ENUM name | Description
0 | SLEEP | Sleep
1 | DEEPSLEEP | Deep sleep
| RW | 0
1 | SLEEPONEXIT | Sleep on exit when returning from Handler mode to Thread mode. Enables interrupt driven applications to avoid returning to empty main application. 0: Do not sleep when returning to thread mode 1: Sleep on ISR exit | RW | 0
0 | RESERVED0 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RW | 0

### TOP:CPU_SCS:CCR

Address offset | 0x0000 0D14
Physical address | 0xE000 ED14 | Instance | CPU_SCS
Description | Configuration Control Register This register is used to enable NMI, HardFault and FAULTMASK to ignore bus fault, trap divide by zero and unaligned accesses, enable user access to the Software Trigger Interrupt Register (STIR), control entry to Thread Mode.
Type | RW

Bits | Field Name | Description | Type | Reset
31:10 | RESERVED10 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RW | 0x00 0000
9 | STKALIGN | Stack alignment bit. 0: Only 4-byte alignment is guaranteed for the SP used prior to the exception on exception entry. 1: On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned and the context to restore it is saved. The SP is restored on the associated exception return. | RW | 1
8 | BFHFNMIGN | Enables handlers with priority -1 or -2 to ignore data BusFaults caused by load and store instructions. This applies to the HardFault, NMI, and FAULTMASK escalated handlers: 0: Data BusFaults caused by load and store instructions cause a lock-up 1: Data BusFaults caused by load and store instructions are ignored. Set this bit to 1 only when the handler and its data are in absolutely safe memory. The normal use of this bit is to probe system devices and bridges to detect problems. | RW | 0
7:5 | RESERVED5 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RW | 0x0
4 | DIV_0_TRP | Enables faulting or halting when the processor executes an SDIV or UDIV instruction with a divisor of 0: 0: Do not trap divide by 0. In this mode, a divide by zero returns a quotient of 0. 1: Trap divide by 0. The relevant Usage Fault Status Register bit is CFSR.DIVBYZERO. | RW | 0
3 | UNALIGN_TRP | Enables unaligned access traps: 0: Do not trap unaligned halfword and word accesses 1: Trap unaligned halfword and word accesses. The relevant Usage Fault Status Register bit is CFSR.UNALIGNED. If this bit is set to 1, an unaligned access generates a UsageFault. Unaligned LDM, STM, LDRD, and STRD instructions always fault regardless of the value in UNALIGN_TRP. | RW | 0
2 | RESERVED2 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RW | 0
1 | USERSETMPEND | Enables unprivileged software access to STIR: 0: User code is not allowed to write to the Software Trigger Interrupt register (STIR). 1: User code can write the Software Trigger Interrupt register (STIR) to trigger (pend) a Main exception, which is associated with the Main stack pointer. | RW | 0
0 | NONBASETHREDENA | Indicates how the processor enters Thread mode: 0: Processor can enter Thread mode only when no exception is active. 1: Processor can enter Thread mode from any level using the appropriate return value (EXC_RETURN). Exception returns occur when one of the following instructions loads a value of 0xFXXXXXXX into the PC while in Handler mode: - POP/LDM which includes loading the PC. - LDR with PC as a destination. - BX with any register. The value written to the PC is intercepted and is referred to as the EXC_RETURN value. | RW | 0

### TOP:CPU_SCS:SHPR1

Address offset | 0x0000 0D18
Physical address | 0xE000 ED18 | Instance | CPU_SCS
Description | System Handlers 4-7 Priority Register This register is used to prioritize the following system handlers: Memory manage, Bus fault, and Usage fault. System Handlers are a special class of exception handler that can have their priority set to any of the priority levels. Most can be masked on (enabled) or off (disabled). When disabled, the fault is always treated as a Hard Fault.
Type | RW

Bits | Field Name | Description | Type | Reset
31:24 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text) | RW | 0x00
23:16 | PRI_6 | Priority of system handler 6. UsageFault | RW | 0x00
15:8 | PRI_5 | Priority of system handler 5: BusFault | RW | 0x00
7:0 | PRI_4 | Priority of system handler 4: MemManage | RW | 0x00

### TOP:CPU_SCS:SHPR2

Address offset | 0x0000 0D1C
Physical address | 0xE000 ED1C | Instance | CPU_SCS
Description | System Handlers 8-11 Priority Register This register is used to prioritize the SVC handler. System Handlers are a special class of exception handler that can have their priority set to any of the priority levels. Most can be masked on (enabled) or off (disabled). When disabled, the fault is always treated as a Hard Fault.
Type | RW

Bits | Field Name | Description | Type | Reset
31:24 | PRI_11 | Priority of system handler 11. SVCall | RW | 0x00
23:0 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text) | RW | 0x00 0000

### TOP:CPU_SCS:SHPR3

Address offset | 0x0000 0D20
Physical address | 0xE000 ED20 | Instance | CPU_SCS
Description | System Handlers 12-15 Priority Register This register is used to prioritize the following system handlers: SysTick, PendSV and Debug Monitor. System Handlers are a special class of exception handler that can have their priority set to any of the priority levels. Most can be masked on (enabled) or off (disabled). When disabled, the fault is always treated as a Hard Fault.
Type | RW

Bits | Field Name | Description | Type | Reset
31:24 | PRI_15 | Priority of system handler 15. SysTick exception | RW | 0x00
23:16 | PRI_14 | Priority of system handler 14. Pend SV | RW | 0x00
15:8 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text) | RW | 0x00
7:0 | PRI_12 | Priority of system handler 12. Debug Monitor | RW | 0x00

### TOP:CPU_SCS:SHCSR

Address offset | 0x0000 0D24
Physical address | 0xE000 ED24 | Instance | CPU_SCS
Description | System Handler Control and State Register This register is used to enable or disable the system handlers, determine the pending status of bus fault, mem manage fault, and SVC, determine the active status of the system handlers. If a fault condition occurs while its fault handler is disabled, the fault escalates to a Hard Fault.
Type | RW

Bits | Field Name | Description | Type | Reset
31:19 | RESERVED19 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RW | 0x0000
18 | USGFAULTENA | Usage fault system handler enable
Value | ENUM name | Description
0 | DIS | Exception disabled
1 | EN | Exception enabled
| RW | 0
17 | BUSFAULTENA | Bus fault system handler enable
Value | ENUM name | Description
0 | DIS | Exception disabled
1 | EN | Exception enabled
| RW | 0
16 | MEMFAULTENA | MemManage fault system handler enable
Value | ENUM name | Description
0 | DIS | Exception disabled
1 | EN | Exception enabled
| RW | 0
15 | SVCALLPENDED | SVCall pending
Value | ENUM name | Description
0 | NOTPENDING | Exception is not active
1 | PENDING | Exception is pending.
| RO | 0
14 | BUSFAULTPENDED | BusFault pending
Value | ENUM name | Description
0 | NOTPENDING | Exception is not active
1 | PENDING | Exception is pending.
| RO | 0
13 | MEMFAULTPENDED | MemManage exception pending
Value | ENUM name | Description
0 | NOTPENDING | Exception is not active
1 | PENDING | Exception is pending.
| RO | 0
12 | USGFAULTPENDED | Usage fault pending
Value | ENUM name | Description
0 | NOTPENDING | Exception is not active
1 | PENDING | Exception is pending.
| RO | 0
11 | SYSTICKACT | SysTick active flag. 0x0: Not active 0x1: Active
Value | ENUM name | Description
0 | NOTACTIVE | Exception is not active
1 | ACTIVE | Exception is active
| RO | 0
10 | PENDSVACT | PendSV active 0x0: Not active 0x1: Active | RO | 0
9 | RESERVED9 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0
8 | MONITORACT | Debug monitor active
Value | ENUM name | Description
0 | NOTACTIVE | Exception is not active
1 | ACTIVE | Exception is active
| RO | 0
7 | SVCALLACT | SVCall active
Value | ENUM name | Description
0 | NOTACTIVE | Exception is not active
1 | ACTIVE | Exception is active
| RO | 0
6:4 | RESERVED4 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0
3 | USGFAULTACT | UsageFault exception active
Value | ENUM name | Description
0 | NOTACTIVE | Exception is not active
1 | ACTIVE | Exception is active
| RO | 0
2 | RESERVED2 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0
1 | BUSFAULTACT | BusFault exception active
Value | ENUM name | Description
0 | NOTACTIVE | Exception is not active
1 | ACTIVE | Exception is active
| RO | 0
0 | MEMFAULTACT | MemManage exception active
Value | ENUM name | Description
0 | NOTACTIVE | Exception is not active
1 | ACTIVE | Exception is active
| RO | 0

### TOP:CPU_SCS:CFSR

Address offset | 0x0000 0D28
Physical address | 0xE000 ED28 | Instance | CPU_SCS
Description | Configurable Fault Status Registers This register is used to obtain information about local faults. These registers include three subsections: The first byte is Memory Manage Fault Status Register (MMFSR). The second byte is Bus Fault Status Register (BFSR). The higher half-word is Usage Fault Status Register (UFSR). The flags in these registers indicate the causes of local faults. Multiple flags can be set if more than one fault occurs. These register are read/write-clear. This means that they can be read normally, but writing a 1 to any bit clears that bit. The CFSR is byte accessible. CFSR or its subregisters can be accessed as follows: The following accesses are possible to the CFSR register: - access the complete register with a word access to 0xE000ED28. - access the MMFSR with a byte access to 0xE000ED28 - access the MMFSR and BFSR with a halfword access to 0xE000ED28 - access the BFSR with a byte access to 0xE000ED29 - access the UFSR with a halfword access to 0xE000ED2A.
Type | RW

Bits | Field Name | Description | Type | Reset
31:26 | RESERVED26 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RW | 0x00
25 | DIVBYZERO | When CCR.DIV_0_TRP (see Configuration Control Register on page 8-26) is enabled and an SDIV or UDIV instruction is used with a divisor of 0, this fault occurs The instruction is executed and the return PC points to it. If CCR.DIV_0_TRP is not set, then the divide returns a quotient of 0. | RW | 0
24 | UNALIGNED | When CCR.UNALIGN_TRP is enabled, and there is an attempt to make an unaligned memory access, then this fault occurs. Unaligned LDM/STM/LDRD/STRD instructions always fault irrespective of the setting of CCR.UNALIGN_TRP. | RW | 0
23:20 | RESERVED20 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RW | 0x0
19 | NOCP | Attempt to use a coprocessor instruction. The processor does not support coprocessor instructions. | RW | 0
18 | INVPC | Attempt to load EXC_RETURN into PC illegally. Invalid instruction, invalid context, invalid value. The return PC points to the instruction that tried to set the PC. | RW | 0
17 | INVSTATE | Indicates an attempt to execute in an invalid EPSR state (e.g. after a BX type instruction has changed state). This includes state change after entry to or return from exception, as well as from inter-working instructions. Return PC points to faulting instruction, with the invalid state. | RW | 0
16 | UNDEFINSTR | This bit is set when the processor attempts to execute an undefined instruction. This is an instruction that the processor cannot decode. The return PC points to the undefined instruction. | RW | 0
15 | BFARVALID | This bit is set if the Bus Fault Address Register (BFAR) contains a valid address. This is true after a bus fault where the address is known. Other faults can clear this bit, such as a Mem Manage fault occurring later. If a Bus fault occurs that is escalated to a Hard Fault because of priority, the Hard Fault handler must clear this bit. This prevents problems if returning to a stacked active Bus fault handler whose BFAR value has been overwritten. | RW | 0
14:13 | RESERVED13 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RW | 0x0
12 | STKERR | Stacking from exception has caused one or more bus faults. The SP is still adjusted and the values in the context area on the stack might be incorrect. BFAR is not written. | RW | 0
11 | UNSTKERR | Unstack from exception return has caused one or more bus faults. This is chained to the handler, so that the original return stack is still present. SP is not adjusted from failing return and new save is not performed. BFAR is not written. | RW | 0
10 | IMPRECISERR | Imprecise data bus error. It is a BusFault, but the Return PC is not related to the causing instruction. This is not a synchronous fault. So, if detected when the priority of the current activation is higher than the Bus Fault, it only pends. Bus fault activates when returning to a lower priority activation. If a precise fault occurs before returning to a lower priority exception, the handler detects both IMPRECISERR set and one of the precise fault status bits set at the same time. BFAR is not written. | RW | 0
9 | PRECISERR | Precise data bus error return. | RW | 0
8 | IBUSERR | Instruction bus error flag. This flag is set by a prefetch error. The fault stops on the instruction, so if the error occurs under a branch shadow, no fault occurs. BFAR is not written. | RW | 0
7 | MMARVALID | Memory Manage Address Register (MMFAR) address valid flag. A later-arriving fault, such as a bus fault, can clear a memory manage fault.. If a MemManage fault occurs that is escalated to a Hard Fault because of priority, the Hard Fault handler must clear this bit. This prevents problems on return to a stacked active MemManage handler whose MMFAR value has been overwritten. | RW | 0
6:5 | RESERVED5 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RW | 0x0
4 | MSTKERR | Stacking from exception has caused one or more access violations. The SP is still adjusted and the values in the context area on the stack might be incorrect. MMFAR is not written. | RW | 0
3 | MUNSTKERR | Unstack from exception return has caused one or more access violations. This is chained to the handler, so that the original return stack is still present. SP is not adjusted from failing return and new save is not performed. MMFAR is not written. | RW | 0
2 | RESERVED2 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RW | 0
1 | DACCVIOL | Data access violation flag. Attempting to load or store at a location that does not permit the operation sets this flag. The return PC points to the faulting instruction. This error loads MMFAR with the address of the attempted access. | RW | 0
0 | IACCVIOL | Instruction access violation flag. Attempting to fetch an instruction from a location that does not permit execution sets this flag. This occurs on any access to an XN region, even when the MPU is disabled or not present. The return PC points to the faulting instruction. MMFAR is not written. | RW | 0

### TOP:CPU_SCS:HFSR

Address offset | 0x0000 0D2C
Physical address | 0xE000 ED2C | Instance | CPU_SCS
Description | Hard Fault Status Register This register is used to obtain information about events that activate the Hard Fault handler. This register is a write-clear register. This means that writing a 1 to a bit clears that bit.
Type | RW

Bits | Field Name | Description | Type | Reset
31 | DEBUGEVT | This bit is set if there is a fault related to debug. This is only possible when halting debug is not enabled. For monitor enabled debug, it only happens for BKPT when the current priority is higher than the monitor. When both halting and monitor debug are disabled, it only happens for debug events that are not ignored (minimally, BKPT). The Debug Fault Status Register is updated. | RW | 0
30 | FORCED | Hard Fault activated because a Configurable Fault was received and cannot activate because of priority or because the Configurable Fault is disabled. The Hard Fault handler then has to read the other fault status registers to determine cause. | RW | 0
29:2 | RESERVED2 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RW | 0x000 0000
1 | VECTTBL | This bit is set if there is a fault because of vector table read on exception processing (Bus Fault). This case is always a Hard Fault. The return PC points to the pre-empted instruction. | RW | 0
0 | RESERVED0 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RW | 0

### TOP:CPU_SCS:DFSR

Address offset | 0x0000 0D30
Physical address | 0xE000 ED30 | Instance | CPU_SCS
Description | Debug Fault Status Register This register is used to monitor external debug requests, vector catches, data watchpoint match, BKPT instruction execution, halt requests. Multiple flags in the Debug Fault Status Register can be set when multiple fault conditions occur. The register is read/write clear. This means that it can be read normally. Writing a 1 to a bit clears that bit. Note that these bits are not set unless the event is caught. This means that it causes a stop of some sort. If halting debug is enabled, these events stop the processor into debug. If debug is disabled and the debug monitor is enabled, then this becomes a debug monitor handler call, if priority permits. If debug and the monitor are both disabled, some of these events are Hard Faults, and some are ignored.
Type | RW

Bits | Field Name | Description | Type | Reset
31:5 | RESERVED5 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RW | 0x000 0000
4 | EXTERNAL | External debug request flag. The processor stops on next instruction boundary. 0x0: External debug request signal not asserted 0x1: External debug request signal asserted | RW | 0
3 | VCATCH | Vector catch flag. When this flag is set, a flag in one of the local fault status registers is also set to indicate the type of fault. 0x0: No vector catch occurred 0x1: Vector catch occurred | RW | 0
2 | DWTTRAP | Data Watchpoint and Trace (DWT) flag. The processor stops at the current instruction or at the next instruction. 0x0: No DWT match 0x1: DWT match | RW | 0
1 | BKPT | BKPT flag. The BKPT flag is set by a BKPT instruction in flash patch code, and also by normal code. Return PC points to breakpoint containing instruction. 0x0: No BKPT instruction execution 0x1: BKPT instruction execution | RW | 0
0 | HALTED | Halt request flag. The processor is halted on the next instruction. 0x0: No halt request 0x1: Halt requested by NVIC, including step | RW | 0

### TOP:CPU_SCS:MMFAR

Address offset | 0x0000 0D34
Physical address | 0xE000 ED34 | Instance | CPU_SCS
Description | Mem Manage Fault Address Register This register is used to read the address of the location that caused a Memory Manage Fault.
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | ADDRESS | Mem Manage fault address field. This field is the data address of a faulted load or store attempt. When an unaligned access faults, the address is the actual address that faulted. Because an access can be split into multiple parts, each aligned, this address can be any offset in the range of the requested size. Flags CFSR.IACCVIOL, CFSR.DACCVIOL ,CFSR.MUNSTKERR and CFSR.MSTKERR in combination with CFSR.MMARVALIDindicate the cause of the fault. | RW | 0x0000 0000

### TOP:CPU_SCS:BFAR

Address offset | 0x0000 0D38
Physical address | 0xE000 ED38 | Instance | CPU_SCS
Description | Bus Fault Address Register This register is used to read the address of the location that generated a Bus Fault.
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | ADDRESS | Bus fault address field. This field is the data address of a faulted load or store attempt. When an unaligned access faults, the address is the address requested by the instruction, even if that is not the address that faulted. Flags CFSR.IBUSERR, CFSR.PRECISERR, CFSR.IMPRECISERR, CFSR.UNSTKERR and CFSR.STKERR in combination with CFSR.BFARVALID indicate the cause of the fault. | RW | 0x0000 0000

### TOP:CPU_SCS:AFSR

Address offset | 0x0000 0D3C
Physical address | 0xE000 ED3C | Instance | CPU_SCS
Description | Auxiliary Fault Status Register This register is used to determine additional system fault information to software. Single-cycle high level on an auxiliary faults is latched as one. The bit can only be cleared by writing a one to the corresponding bit. Auxiliary fault inputs to the CPU are tied to 0.
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | IMPDEF | Implementation defined. The bits map directly onto the signal assignment to the auxiliary fault inputs. Tied to 0 | RW | 0x0000 0000

### TOP:CPU_SCS:ID_PFR0

Address offset | 0x0000 0D40
Physical address | 0xE000 ED40 | Instance | CPU_SCS
Description | Processor Feature Register 0
Type | RO

Bits | Field Name | Description | Type | Reset
31:8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 0000
7:4 | STATE1 | State1 (T-bit == 1) 0x0: N/A 0x1: N/A 0x2: Thumb-2 encoding with the 16-bit basic instructions plus 32-bit Buncond/BL but no other 32-bit basic instructions (Note non-basic 32-bit instructions can be added using the appropriate instruction attribute, but other 32-bit basic instructions cannot.) 0x3: Thumb-2 encoding with all Thumb-2 basic instructions | RO | 0x3
3:0 | STATE0 | State0 (T-bit == 0) 0x0: No ARM encoding 0x1: N/A | RO | 0x0

### TOP:CPU_SCS:ID_PFR1

Address offset | 0x0000 0D44
Physical address | 0xE000 ED44 | Instance | CPU_SCS
Description | Processor Feature Register 1
Type | RO

Bits | Field Name | Description | Type | Reset
31:12 | RESERVED12 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0 0000
11:8 | MICROCONTROLLER_PROGRAMMERS_MODEL | Microcontroller programmer's model 0x0: Not supported 0x2: Two-stack support | RO | 0x2
7:0 | RESERVED0 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00

### TOP:CPU_SCS:ID_DFR0

Address offset | 0x0000 0D48
Physical address | 0xE000 ED48 | Instance | CPU_SCS
Description | Debug Feature Register 0 This register provides a high level view of the debug system. Further details are provided in the debug infrastructure itself.
Type | RO

Bits | Field Name | Description | Type | Reset
31:24 | RESERVED24 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00
23:20 | MICROCONTROLLER_DEBUG_MODEL | Microcontroller Debug Model - memory mapped 0x0: Not supported 0x1: Microcontroller debug v1 (ITMv1 and DWTv1) | RO | 0x1
19:0 | RESERVED0 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0 0000

### TOP:CPU_SCS:ID_AFR0

Address offset | 0x0000 0D4C
Physical address | 0xE000 ED4C | Instance | CPU_SCS
Description | Auxiliary Feature Register0 This register provides some freedom for implementation defined features to be registered. Not used in Cortex-M.
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | RESERVED0 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0000 0000

### TOP:CPU_SCS:ID_MMFR0

Address offset | 0x0000 0D50
Physical address | 0xE000 ED50 | Instance | CPU_SCS
Description | Memory Model Feature Register 0 General information on the memory model and memory management support.
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | RESERVED0 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0010 0030

### TOP:CPU_SCS:ID_MMFR1

Address offset | 0x0000 0D54
Physical address | 0xE000 ED54 | Instance | CPU_SCS
Description | Memory Model Feature Register 1 General information on the memory model and memory management support.
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | RESERVED0 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0000 0000

### TOP:CPU_SCS:ID_MMFR2

Address offset | 0x0000 0D58
Physical address | 0xE000 ED58 | Instance | CPU_SCS
Description | Memory Model Feature Register 2 General information on the memory model and memory management support.
Type | RO

Bits | Field Name | Description | Type | Reset
31:25 | RESERVED28 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00
24 | WAIT_FOR_INTERRUPT_STALLING | wait for interrupt stalling 0x0: Not supported 0x1: Wait for interrupt supported | RO | 1
23:0 | RESERVED0 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 0000

### TOP:CPU_SCS:ID_MMFR3

Address offset | 0x0000 0D5C
Physical address | 0xE000 ED5C | Instance | CPU_SCS
Description | Memory Model Feature Register3 General information on the memory model and memory management support.
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | RESERVED0 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0000 0000

### TOP:CPU_SCS:ID_ISAR0

Address offset | 0x0000 0D60
Physical address | 0xE000 ED60 | Instance | CPU_SCS
Description | ISA Feature Register 0 Information on the instruction set attributes register
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | RESERVED0 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0110 1110

### TOP:CPU_SCS:ID_ISAR1

Address offset | 0x0000 0D64
Physical address | 0xE000 ED64 | Instance | CPU_SCS
Description | ISA Feature Register 1 Information on the instruction set attributes register
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | RESERVED0 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0211 1000

### TOP:CPU_SCS:ID_ISAR2

Address offset | 0x0000 0D68
Physical address | 0xE000 ED68 | Instance | CPU_SCS
Description | ISA Feature Register 2 Information on the instruction set attributes register
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | RESERVED0 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x2111 2231

### TOP:CPU_SCS:ID_ISAR3

Address offset | 0x0000 0D6C
Physical address | 0xE000 ED6C | Instance | CPU_SCS
Description | ISA Feature Register 3 Information on the instruction set attributes register
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | RESERVED0 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0111 1110

### TOP:CPU_SCS:ID_ISAR4

Address offset | 0x0000 0D70
Physical address | 0xE000 ED70 | Instance | CPU_SCS
Description | ISA Feature Register 4 Information on the instruction set attributes register
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | RESERVED0 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0131 0132

### TOP:CPU_SCS:CPACR

Address offset | 0x0000 0D88
Physical address | 0xE000 ED88 | Instance | CPU_SCS
Description | Coprocessor Access Control Register This register specifies the access privileges for coprocessors.
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | RESERVED0 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RW | 0x0000 0000

### TOP:CPU_SCS:DHCSR

Address offset | 0x0000 0DF0
Physical address | 0xE000 EDF0 | Instance | CPU_SCS
Description | Debug Halting Control and Status Register The purpose of this register is to provide status information about the state of the processor, enable core debug, halt and step the processor. For writes, 0xA05F must be written to higher half-word of this register, otherwise the write operation is ignored and no bits are written into the register. If not enabled for Halting mode, C_DEBUGEN = 1, all other fields are disabled. This register is not reset on a core reset. It is reset by a power-on reset. However, C_HALT always clears on a core reset. To halt on a reset, the following bits must be enabled: DEMCR.VC_CORERESET and C_DEBUGEN. Note that writes to this register in any size other than word are unpredictable. It is acceptable to read in any size, and it can be used to avoid or intentionally change a sticky bit. Behavior of the system when writing to this register while CPU is halted (i.e. C_DEBUGEN = 1 and S_HALT= 1): C_HALT=0, C_STEP=0, C_MASKINTS=0 Exit Debug state and start instruction execution. Exceptions activate according to the exception configuration rules. C_HALT=0, C_STEP=0, C_MASKINTS=1 Exit Debug state and start instruction execution. PendSV, SysTick and external configurable interrupts are disabled, otherwise exceptions activate according to standard configuration rules. C_HALT=0, C_STEP=1, C_MASKINTS=0 Exit Debug state, step an instruction and halt. Exceptions activate according to the exception configuration rules. C_HALT=0, C_STEP=1, C_MASKINTS=1 Exit Debug state, step an instruction and halt. PendSV, SysTick and external configurable interrupts are disabled, otherwise exceptions activate according to standard configuration rules. C_HALT=1, C_STEP=x, C_MASKINTS=x Remain in Debug state
Type | RW

Bits | Field Name | Description | Type | Reset
31:26 | RESERVED26 | Software should not rely on the value of a reserved. When writing to this register, 0x28 must be written this bit-field, otherwise the write operation is ignored and no bits are written into the register. | RW | 0x00
25 | S_RESET_ST | Indicates that the core has been reset, or is now being reset, since the last time this bit was read. This a sticky bit that clears on read. So, reading twice and getting 1 then 0 means it was reset in the past. Reading twice and getting 1 both times means that it is being reset now (held in reset still). When writing to this register, 0 must be written this bit-field, otherwise the write operation is ignored and no bits are written into the register. | RW | 0
24 | S_RETIRE_ST | Indicates that an instruction has completed since last read. This is a sticky bit that clears on read. This determines if the core is stalled on a load/store or fetch. When writing to this register, 0 must be written this bit-field, otherwise the write operation is ignored and no bits are written into the register. | RW | 0
23:20 | RESERVED20 | Software should not rely on the value of a reserved. When writing to this register, 0x5 must be written this bit-field, otherwise the write operation is ignored and no bits are written into the register. | RW | 0x0
19 | S_LOCKUP | Reads as one if the core is running (not halted) and a lockup condition is present. When writing to this register, 1 must be written this bit-field, otherwise the write operation is ignored and no bits are written into the register. | RW | 0
18 | S_SLEEP | Indicates that the core is sleeping (WFI, WFE, or SLEEP-ON-EXIT). Must use C_HALT to gain control or wait for interrupt to wake-up. When writing to this register, 1 must be written this bit-field, otherwise the write operation is ignored and no bits are written into the register. | RW | 0
17 | S_HALT | The core is in debug state when this bit is set. When writing to this register, 1 must be written this bit-field, otherwise the write operation is ignored and no bits are written into the register. | RW | 0
16 | S_REGRDY | Register Read/Write on the Debug Core Register Selector register is available. Last transfer is complete. When writing to this register, 1 must be written this bit-field, otherwise the write operation is ignored and no bits are written into the register. | RW | 0
15:6 | RESERVED6 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x000
5 | C_SNAPSTALL | If the core is stalled on a load/store operation the stall ceases and the instruction is forced to complete. This enables Halting debug to gain control of the core. It can only be set if: C_DEBUGEN = 1 and C_HALT = 1. The core reads S_RETIRE_ST as 0. This indicates that no instruction has advanced. This prevents misuse. The bus state is Unpredictable when this is used. S_RETIRE_ST can detect core stalls on load/store operations. | RW | 0
4 | RESERVED4 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RW | 0
3 | C_MASKINTS | Mask interrupts when stepping or running in halted debug. This masking does not affect NMI, fault exceptions and SVC caused by execution of the instructions. This bit must only be modified when the processor is halted (S_HALT == 1). C_MASKINTS must be set or cleared before halt is released (i.e., the writes to set or clear C_MASKINTS and to set or clear C_HALT must be separate). Modifying C_MASKINTS while the system is running with halting debug support enabled (C_DEBUGEN = 1, S_HALT = 0) may cause unpredictable behavior. | RW | 0
2 | C_STEP | Steps the core in halted debug. When C_DEBUGEN = 0, this bit has no effect. Must only be modified when the processor is halted (S_HALT == 1). Modifying C_STEP while the system is running with halting debug support enabled (C_DEBUGEN = 1, S_HALT = 0) may cause unpredictable behavior. | RW | 0
1 | C_HALT | Halts the core. This bit is set automatically when the core Halts. For example Breakpoint. This bit clears on core reset. | RW | 0
0 | C_DEBUGEN | Enables debug. This can only be written by AHB-AP and not by the core. It is ignored when written by the core, which cannot set or clear it. The core must write a 1 to it when writing C_HALT to halt itself. The values of C_HALT, C_STEP and C_MASKINTS are ignored by hardware when C_DEBUGEN = 0. The read values for C_HALT, C_STEP and C_MASKINTS fields will be unknown to software when C_DEBUGEN = 0. | RW | 0

### TOP:CPU_SCS:DCRSR

Address offset | 0x0000 0DF4
Physical address | 0xE000 EDF4 | Instance | CPU_SCS
Description | Deubg Core Register Selector Register The purpose of this register is to select the processor register to transfer data to or from. This write-only register generates a handshake to the core to transfer data to or from Debug Core Register Data Register and the selected register. Until this core transaction is complete, DHCSR.S_REGRDY is 0. Note that writes to this register in any size but word are Unpredictable. Note that PSR registers are fully accessible this way, whereas some read as 0 when using MRS instructions. Note that all bits can be written, but some combinations cause a fault when execution is resumed.
Type | WO

Bits | Field Name | Description | Type | Reset
31:17 | RESERVED17 | Software should not rely on the value of a reserved. Write 0. | WO | 0x0000
16 | REGWNR | 1: Write 0: Read | WO | 0
15:5 | RESERVED5 | Software should not rely on the value of a reserved. Write 0. | WO | 0x000
4:0 | REGSEL | Register select 0x00: R0 0x01: R1 0x02: R2 0x03: R3 0x04: R4 0x05: R5 0x06: R6 0x07: R7 0x08: R8 0x09: R9 0x0A: R10 0x0B: R11 0x0C: R12 0x0D: Current SP 0x0E: LR 0x0F: DebugReturnAddress 0x10: XPSR/flags, execution state information, and exception number 0x11: MSP (Main SP) 0x12: PSP (Process SP) 0x14: CONTROL<<24 | FAULTMASK<<16 | BASEPRI<<8 | PRIMASK | WO | 0x00

### TOP:CPU_SCS:DCRDR

Address offset | 0x0000 0DF8
Physical address | 0xE000 EDF8 | Instance | CPU_SCS
Description | Debug Core Register Data Register
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | DCRDR | This register holds data for reading and writing registers to and from the processor. This is the data value written to the register selected by DCRSR. When the processor receives a request from DCRSR, this register is read or written by the processor using a normal load-store unit operation. If core register transfers are not being performed, software-based debug monitors can use this register for communication in non-halting debug. This enables flags and bits to acknowledge state and indicate if commands have been accepted to, replied to, or accepted and replied to. | RW | 0x0000 0000

### TOP:CPU_SCS:DEMCR

Address offset | 0x0000 0DFC
Physical address | 0xE000 EDFC | Instance | CPU_SCS
Description | Debug Exception and Monitor Control Register The purpose of this register is vector catching and debug monitor control. This register manages exception behavior under debug. Vector catching is only available to halting debug. The upper halfword is for monitor controls and the lower halfword is for halting exception support. This register is not reset on a system reset. This register is reset by a power-on reset. The fields MON_EN, MON_PEND, MON_STEP and MON_REQ are always cleared on a core reset. The debug monitor is enabled by software in the reset handler or later, or by the AHB-AP port. Vector catching is semi-synchronous. When a matching event is seen, a Halt is requested. Because the processor can only halt on an instruction boundary, it must wait until the next instruction boundary. As a result, it stops on the first instruction of the exception handler. However, two special cases exist when a vector catch has triggered: 1. If a fault is taken during a vector read or stack push error the halt occurs on the corresponding fault handler for the vector error or stack push. 2. If a late arriving interrupt detected during a vector read or stack push error it is not taken. That is, an implementation that supports the late arrival optimization must suppress it in this case.
Type | RW

Bits | Field Name | Description | Type | Reset
31:25 | RESERVED25 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RW | 0x00
24 | TRCENA | This bit must be set to 1 to enable use of the trace and debug blocks: DWT, ITM, ETM and TPIU. This enables control of power usage unless tracing is required. The application can enable this, for ITM use, or use by a debugger. | RW | 0
23:20 | RESERVED20 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RW | 0x0
19 | MON_REQ | This enables the monitor to identify how it wakes up. This bit clears on a Core Reset. 0x0: Woken up by debug exception. 0x1: Woken up by MON_PEND | RW | 0
18 | MON_STEP | When MON_EN = 1, this steps the core. When MON_EN = 0, this bit is ignored. This is the equivalent to DHCSR.C_STEP. Interrupts are only stepped according to the priority of the monitor and settings of PRIMASK, FAULTMASK, or BASEPRI. | RW | 0
17 | MON_PEND | Pend the monitor to activate when priority permits. This can wake up the monitor through the AHB-AP port. It is the equivalent to DHCSR.C_HALT for Monitor debug. This register does not reset on a system reset. It is only reset by a power-on reset. Software in the reset handler or later, or by the DAP must enable the debug monitor. | RW | 0
16 | MON_EN | Enable the debug monitor. When enabled, the System handler priority register controls its priority level. If disabled, then all debug events go to Hard fault. DHCSR.C_DEBUGEN overrides this bit. Vector catching is semi-synchronous. When a matching event is seen, a Halt is requested. Because the processor can only halt on an instruction boundary, it must wait until the next instruction boundary. As a result, it stops on the first instruction of the exception handler. However, two special cases exist when a vector catch has triggered: 1. If a fault is taken during vectoring, vector read or stack push error, the halt occurs on the corresponding fault handler, for the vector error or stack push. 2. If a late arriving interrupt comes in during vectoring, it is not taken. That is, an implementation that supports the late arrival optimization must suppress it in this case. | RW | 0
15:11 | RESERVED11 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RW | 0x00
10 | VC_HARDERR | Debug trap on Hard Fault. Ignored when DHCSR.C_DEBUGEN is cleared. | RW | 0
9 | VC_INTERR | Debug trap on a fault occurring during an exception entry or return sequence. Ignored when DHCSR.C_DEBUGEN is cleared. | RW | 0
8 | VC_BUSERR | Debug Trap on normal Bus error. Ignored when DHCSR.C_DEBUGEN is cleared. | RW | 0
7 | VC_STATERR | Debug trap on Usage Fault state errors. Ignored when DHCSR.C_DEBUGEN is cleared. | RW | 0
6 | VC_CHKERR | Debug trap on Usage Fault enabled checking errors. Ignored when DHCSR.C_DEBUGEN is cleared. | RW | 0
5 | VC_NOCPERR | Debug trap on a UsageFault access to a Coprocessor. Ignored when DHCSR.C_DEBUGEN is cleared. | RW | 0
4 | VC_MMERR | Debug trap on Memory Management faults. Ignored when DHCSR.C_DEBUGEN is cleared. | RW | 0
3:1 | RESERVED1 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RW | 0x0
0 | VC_CORERESET | Reset Vector Catch. Halt running system if Core reset occurs. Ignored when DHCSR.C_DEBUGEN is cleared. | RW | 0

### TOP:CPU_SCS:STIR

Address offset | 0x0000 0F00
Physical address | 0xE000 EF00 | Instance | CPU_SCS
Description | Software Trigger Interrupt Register
Type | WO

Bits | Field Name | Description | Type | Reset
31:9 | RESERVED9 | Software should not rely on the value of a reserved. Write 0. | WO | 0x00 0000
8:0 | INTID | Interrupt ID field. Writing a value to this bit-field is the same as manually pending an interrupt by setting the corresponding interrupt bit in an Interrupt Set Pending Register in NVIC_ISPR0 or NVIC_ISPR1. | WO | 0x000