## AUX_TIMER

Instance: AUX_TIMER
Component: AUX_TIMER
Base address: 0x400c7000

AUX Timer

### TOP:AUX_TIMER Register Summary

Register Name | Type | Register Width (Bits) | Register Reset | Address Offset | Physical Address
T0CFG | RW | 32 | 0x0000 0000 | 0x0000 0000 | 0x400C 7000
T1CFG | RW | 32 | 0x0000 0000 | 0x0000 0004 | 0x400C 7004
T0CTL | RW | 32 | 0x0000 0000 | 0x0000 0008 | 0x400C 7008
T0TARGET | RW | 32 | 0x0000 0000 | 0x0000 000C | 0x400C 700C
T1TARGET | RW | 32 | 0x0000 0000 | 0x0000 0010 | 0x400C 7010
T1CTL | RW | 32 | 0x0000 0000 | 0x0000 0014 | 0x400C 7014

### TOP:AUX_TIMER Register Descriptions

### TOP:AUX_TIMER:T0CFG

Address offset | 0x0000 0000
Physical address | 0x400C 7000 | Instance | AUX_TIMER
Description | Timer 0 Configuration
Type | RW

Bits | Field Name | Description | Type | Reset
31:14 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0 0000
13 | TICK_SRC_POL | Source count polarity for timer 0
Value | ENUM name | Description
0 | RISE | Count on rising edges of TICK_SRC
1 | FALL | Count on falling edges of TICK_SRC
| RW | 0
12:8 | TICK_SRC | Selected tick source for timer 0
Value | ENUM name | Description
0x00 | RTC_CH2_EV | Selects RTC_CH2_EV
0x01 | AUX_COMPA | Selects AUX_COMPA
0x02 | AUX_COMPB | Selects AUX_COMPB
0x03 | TDC_DONE | Selects TDC_DONE
0x05 | TIMER1_EV | Selects TIMER1_EV
0x06 | SMPH_AUTOTAKE_DONE | Selects SMPH_AUTOTAKE_DONE
0x07 | ADC_DONE | Selects ADC_DONE
0x08 | RTC_4KHZ | Selects RTC_4KHZ
0x09 | OBSMUX0 | Selects OBSMUX0
0x0A | OBSMUX1 | Selects OBSMUX1
0x0B | AON_SW | Selects AON_SW
0x0C | AON_PROG_WU | Selects AON_PROG_WU
0x0D | AUXIO0 | Selects AUXIO0
0x0E | AUXIO1 | Selects AUXIO1
0x0F | AUXIO2 | Selects AUXIO2
0x10 | AUXIO3 | Selects AUXIO3
0x11 | AUXIO4 | Selects AUXIO4
0x12 | AUXIO5 | Selects AUXIO5
0x13 | AUXIO6 | Selects AUXIO6
0x14 | AUXIO7 | Selects AUXIO7
0x15 | AUXIO8 | Selects AUXIO8
0x16 | AUXIO9 | Selects AUXIO9
0x17 | AUXIO10 | Selects AUXIO10
0x18 | AUXIO11 | Selects AUXIO11
0x19 | AUXIO12 | Selects AUXIO12
0x1A | AUXIO13 | Selects AUXIO13
0x1B | AUXIO14 | Selects AUXIO14
0x1C | AUXIO15 | Selects AUXIO15
0x1D | ACLK_REF | Selects ACLK_REF
0x1E | MCU_EVENT | Selects MCU_EV
0x1F | ADC_IRQ | Selects ADC_IRQ
| RW | 0x00
7:4 | PRE | Prescaler division ratio is 2^PRE | RW | 0x0
3:2 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0
1 | MODE | Timer 0 mode
Value | ENUM name | Description
0 | CLK | Timer 0 increments on every 2^PRE edges of AUX clock
1 | TICK | Timer 0 counter increments only on edges of the event set by TICK_SRC. The events are divided by the PRE setting.
| RW | 0
0 | RELOAD | Timer 0 reload setting
Value | ENUM name | Description
0 | MAN | Timer has to be restarted manually
1 | CONT | Timer is automatically restarted when target is reached
| RW | 0

### TOP:AUX_TIMER:T1CFG

Address offset | 0x0000 0004
Physical address | 0x400C 7004 | Instance | AUX_TIMER
Description | Timer 1 Configuration
Type | RW

Bits | Field Name | Description | Type | Reset
31:14 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0 0000
13 | TICK_SRC_POL | Source count polarity for timer 1
Value | ENUM name | Description
0 | RISE | Count on rising edges of TICK_SRC
1 | FALL | Count on falling edges of TICK_SRC
| RW | 0
12:8 | TICK_SRC | Selected tick source for timer 1
Value | ENUM name | Description
0x00 | RTC_CH2_EV | Selects RTC_CH2_EV
0x01 | AUX_COMPA | Selects AUX_COMPA
0x02 | AUX_COMPB | Selects AUX_COMPB
0x03 | TDC_DONE | Selects TDC_DONE
0x04 | TIMER0_EV | Selects TIMER0_EV
0x06 | SMPH_AUTOTAKE_DONE | Selects SMPH_AUTOTAKE_DONE
0x07 | ADC_DONE | Selects ADC_DONE
0x08 | RTC_4KHZ | Selects RTC_4KHZ
0x09 | OBSMUX0 | Selects OBSMUX0
0x0A | OBSMUX1 | Selects OBSMUX1
0x0B | AON_SW | Selects AON_SW
0x0C | AON_PROG_WU | Selects AON_PROG_WU
0x0D | AUXIO0 | Selects AUXIO0
0x0E | AUXIO1 | Selects AUXIO1
0x0F | AUXIO2 | Selects AUXIO2
0x10 | AUXIO3 | Selects AUXIO3
0x11 | AUXIO4 | Selects AUXIO4
0x12 | AUXIO5 | Selects AUXIO5
0x13 | AUXIO6 | Selects AUXIO6
0x14 | AUXIO7 | Selects AUXIO7
0x15 | AUXIO8 | Selects AUXIO8
0x16 | AUXIO9 | Selects AUXIO9
0x17 | AUXIO10 | Selects AUXIO10
0x18 | AUXIO11 | Selects AUXIO11
0x19 | AUXIO12 | Selects AUXIO12
0x1A | AUXIO13 | Selects AUXIO13
0x1B | AUXIO14 | Selects AUXIO14
0x1C | AUXIO15 | Selects AUXIO15
0x1D | ACLK_REF | Selects ACLK_REF
0x1E | MCU_EVENT | Selects MCU_EV
0x1F | ADC_IRQ | Selects ADC_IRQ
| RW | 0x00
7:4 | PRE | Prescaler division ratio is 2^PRE | RW | 0x0
3:2 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0
1 | MODE | Timer 1 mode
Value | ENUM name | Description
0 | CLK | Timer 1 increments on every 2^PRE edges of AUX clock
1 | TICK | Timer 1 counter increments only on edges of the event set by TICK_SRC. The events are divided by the PRE setting.
| RW | 0
0 | RELOAD | Timer 1 reload setting
Value | ENUM name | Description
0 | MAN | Timer has to be restarted manually
1 | CONT | Timer is automatically restarted when target is reached
| RW | 0

### TOP:AUX_TIMER:T0CTL

Address offset | 0x0000 0008
Physical address | 0x400C 7008 | Instance | AUX_TIMER
Description | Timer 0 Control Run control/status for timer 0
Type | RW

Bits | Field Name | Description | Type | Reset
31:1 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0000 0000
0 | EN | Timer 0 run enable control. The counter restarts when enabling the timer. If T0CFG.RELOAD = 0, the timer is automatically disabled when reaching T0TARGET.VALUE 0: Disable timer 0 1: Enable timer 0 | RW | 0

### TOP:AUX_TIMER:T0TARGET

Address offset | 0x0000 000C
Physical address | 0x400C 700C | Instance | AUX_TIMER
Description | Timer 0 Target Target counter value for timer 0
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0000
15:0 | VALUE | Timer 0 counts from 0 to VALUE. Then gives an event and restarts if configured to do to so in the T0CFG.RELOAD setting. If VALUE is changed while timer 0 is running so that the count becomes higher than VALUE timer 0 will also restart if configured to do so. If T0CFG.MODE=0,no prescaler is used, and VALUE equals 1, the TIMER0_EV event line will be always set | RW | 0x0000

### TOP:AUX_TIMER:T1TARGET

Address offset | 0x0000 0010
Physical address | 0x400C 7010 | Instance | AUX_TIMER
Description | Timer 1 Target Target Counter Value Timer 1
Type | RW

Bits | Field Name | Description | Type | Reset
31:8 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x00 0000
7:0 | VALUE | Timer 1 counts from 0 to VALUE. Then gives an event and restarts if configured to do to so in the T1CFG.RELOAD setting. If VALUE is changed while timer 1 is running so that the count becomes higher than VALUE timer 1 will also restart if configured to do so. If T1CFG.MODE=0,no prescaler is used, and VALUE equals 1, the TIMER1_EV event line will be always set | RW | 0x00

### TOP:AUX_TIMER:T1CTL

Address offset | 0x0000 0014
Physical address | 0x400C 7014 | Instance | AUX_TIMER
Description | Timer 1 Control Run Control/Status For Timer 1
Type | RW

Bits | Field Name | Description | Type | Reset
31:1 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0000 0000
0 | EN | Timer 1 run enable control. The counter restarts when enabling the timer. If T1CFG.RELOAD = 0, the timer is automatically disabled when reaching T1TARGET.VALUE 0: Disable timer 1 1: Enable timer 1 | RW | 0