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spis.h
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1 /******************************************************************************
2 * Filename: spis.h
3 * Revised: 2015-01-14 12:12:44 +0100 (on, 14 jan 2015)
4 * Revision: 42373
5 *
6 * Description: Prototypes and macros for the SPI Slave controller
7 *
8 * Copyright (c) 2015, Texas Instruments Incorporated
9 * All rights reserved.
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions are met:
13 *
14 * 1) Redistributions of source code must retain the above copyright notice,
15 * this list of conditions and the following disclaimer.
16 *
17 * 2) Redistributions in binary form must reproduce the above copyright notice,
18 * this list of conditions and the following disclaimer in the documentation
19 * and/or other materials provided with the distribution.
20 *
21 * 3) Neither the name of the ORGANIZATION nor the names of its contributors may
22 * be used to endorse or promote products derived from this software without
23 * specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
26 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
28 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
29 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
35 * POSSIBILITY OF SUCH DAMAGE.
36 *
37 ******************************************************************************/
38
39 //*****************************************************************************
40 //
43 //
44 //*****************************************************************************
45
46 #ifndef __SPIS_H__
47 #define __SPIS_H__
48
49 //*****************************************************************************
50 //
51 // If building with a C++ compiler, make all of the definitions in this header
52 // have a C binding.
53 //
54 //*****************************************************************************
55 #ifdef __cplusplus
56 extern "C"
57 {
58 #endif
59
60 #include <stdbool.h>
61 #include <stdint.h>
62 #include <inc/hw_memmap.h>
63 #include <inc/hw_types.h>
64 #include <inc/hw_ints.h>
65 #include <inc/hw_spis.h>
66 #include <driverlib/debug.h>
67 #include <driverlib/interrupt.h>
68
69 //*****************************************************************************
70 //
71 // Support for DriverLib in ROM:
72 // This section renames all functions that are not "static inline", so that
73 // calling these functions will default to implementation in flash. At the end
74 // of this file a second renaming will change the defaults to implementation in
75 // ROM for available functions.
76 //
77 // To force use of the implementation in flash, e.g. for debugging:
78 // - Globally: Define DRIVERLIB_NOROM at project level
79 // - Per function: Use prefix "NOROM_" when calling the function
80 //
81 // Do not define DRIVERLIB_GENERATE_ROM!
82 //
83 //*****************************************************************************
84 #ifndef DRIVERLIB_GENERATE_ROM
85 #define SPISDataPut NOROM_SPISDataPut
86 #define SPISTxGetValue NOROM_SPISTxGetValue
87 #define SPISDataGet NOROM_SPISDataGet
88 #define SPISRxGetValue NOROM_SPISRxGetValue
89 #define SPISIntStatus NOROM_SPISIntStatus
90 #endif
91
92 //*****************************************************************************
93 //
94 // FIFO size
95 //
96 //*****************************************************************************
97 #define TX_FIFO_SIZE 16 // Size of the TX FIFO
98 #define RX_FIFO_SIZE 16 // Size of the RX FIFO
99
100 //*****************************************************************************
101 //
102 // SPIS configuration parameters
103 //
104 //*****************************************************************************
105 #define SPIS_POS_CLK_POL 0x00000001 // Data captured on rising edge
106 #define SPIS_NEG_CLK_POL 0x00000000 // Data captured on falling edge
107 #define SPIS_TX_BIG_ENDIAN 0x00000002 // TX FIFO is big endian
108 #define SPIS_TX_LITTLE_ENDIAN 0x00000000 // TX FIFO is little endian
109 #define SPIS_RX_BIG_ENDIAN 0x00000004 // RX FIFO is big endian
110 #define SPIS_RX_LITTLE_ENDIAN 0x00000000 // RX FIFO is little endian
111 #define SPIS_TX_DMA_SINGLE 0x00000008 // TX FIFO single DMA request
112 #define SPIS_TX_DMA_BURST 0x00000000 // TX FIFO burst DMA request
113 #define SPIS_RX_DMA_SINGLE 0x00000010 // RX FIFO single DMA request
114 #define SPIS_RX_DMA_BURST 0x00000000 // RX FIFO burst DMA request
115
116 //*****************************************************************************
117 //
118 // Event source that can be mask to generate interrupts
119 //
120 //*****************************************************************************
121 #define SPIS_TX_FULL 0x00000001 // TX FIFO is full
122 #define SPIS_TX_EMPTY 0x00000002 // TX FIFO is empty
123 #define SPIS_TX_GE_WATERMARK 0x00000004 // TX FIFO is above/equal watermark
124 #define SPIS_TX_LE_WATERMARK 0x00000008 // TX FIFO is below/equal watermark
125 #define SPIS_TX_HASDATA 0x00000010 // TX FIFO has data
126 #define SPIS_TX_UNDER_FLOW 0x00000020 // TX FIFO is out of data
127 #define SPIS_TX_OVER_FLOW 0x00000040 // TX FIFO write attempt failed
128 #define SPIS_TX_MASK 0x0000007F // TX FIFO event mask
129 #define SPIS_RX_FULL 0x00000100 // RX FIFO is full
130 #define SPIS_RX_EMPTY 0x00000200 // RX FIFO is empty
131 #define SPIS_RX_GE_WATERMARK 0x00000400 // RX FIFO is above/equal watermark
132 #define SPIS_RX_LE_WATERMARK 0x00000800 // RX FIFO is below/equal watermark
133 #define SPIS_RX_HASDATA 0x00001000 // RX FIFO has data
134 #define SPIS_RX_UNDER_FLOW 0x00002000 // RX FIFO read attempt failed
135 #define SPIS_RX_OVER_FLOW 0x00004000 // RX FIFO is full + 1
136 #define SPIS_RX_MASK 0x00007F00 // RX FIFO event mask
137 #define SPIS_CHIP_SELECT 0x00010000 // Chip select asserted
138 #define SPIS_INCOMPLETE 0x00020000 // Incomplete transfer
139 #define SPIS_PRX_OVERFLOW 0x00040000 // RX overflow
140 #define SPIS_BYTE_DONE 0x00080000 // Byte transfer complete
141 #define SPIS_DMA_DONE_TX 0x00100000 // DMA done for TX FIFO Channel
142 #define SPIS_DMA_DONE_RX 0x00200000 // DMA done for RX FIFO Channel
143 #define SPIS_GP_MASK 0x003F0000
144
145 //*****************************************************************************
146 //
147 // Values used to setup the DMA controller to listen on events from the RX/TX
148 // FIFO status registers
149 //
150 //*****************************************************************************
151 #define SPIS_TX_DMA_FULL ( SPIS_TXFEVSRC_SEL_FULL ) // TX FIFO is full
152 #define SPIS_TX_DMA_EMPTY ( SPIS_TXFEVSRC_SEL_EMPTY ) // TX FIFO is empty
153 #define SPIS_TX_DMA_GE_WMARK ( SPIS_TXFEVSRC_SEL_GE_THR ) // TX FIFO is above/equal watermark
154 #define SPIS_TX_DMA_LE_WMARK ( SPIS_TXFEVSRC_SEL_LE_THR ) // TX FIFO is below/equal watermark
155 #define SPIS_TX_DMA_HASDATA ( SPIS_TXFEVSRC_SEL_NOT_EMPTY ) // TX FIFO has data
156 #define SPIS_TX_DMA_ALWAYS ( SPIS_TXFEVSRC_SEL_ONE ) // Always '1'
157 #define SPIS_TX_DMA_NONE ( SPIS_TXFEVSRC_SEL_ZERO ) // Always '0'
158
159 #define SPIS_RX_DMA_FULL (( SPIS_RXFEVSRC_SEL_FULL ) << 8 ) // RX FIFO is full
160 #define SPIS_RX_DMA_EMPTY (( SPIS_RXFEVSRC_SEL_EMPTY ) << 8 ) // RX FIFO is empty
161 #define SPIS_RX_DMA_GE_WMARK (( SPIS_RXFEVSRC_SEL_GE_THR ) << 8 ) // RX FIFO is above/equal watermark
162 #define SPIS_RX_DMA_LE_WMARK (( SPIS_RXFEVSRC_SEL_LE_THR ) << 8 ) // RX FIFO is below/equal watermark
163 #define SPIS_RX_DMA_HASDATA (( SPIS_RXFEVSRC_SEL_NOT_EMPTY ) << 8 ) // RX FIFO has data
164 #define SPIS_RX_DMA_ALWAYS (( SPIS_RXFEVSRC_SEL_ONE ) << 8 ) // Always '1'
165 #define SPIS_RX_DMA_NONE (( SPIS_RXFEVSRC_SEL_ZERO ) << 8 ) // Always '0'
166
167 //*****************************************************************************
168 //
169 // API Functions and prototypes
170 //
171 //*****************************************************************************
172
173 //*****************************************************************************
174 //
208 //
209 //*****************************************************************************
210 __STATIC_INLINE void
211 SPISConfig(uint32_t ui32Config, uint32_t ui32RxWatermark,
212 uint32_t ui32TxWatermark)
213 {
214 //
215 // Set the master enable bit in the config register.
216 //
217 HWREG(SPIS_BASE + SPIS_O_RXFTHR) = ui32RxWatermark & SPIS_RXFTHR_CNT_M;
218
219 //
220 // Set the master enable bit in the config register.
221 //
222 HWREG(SPIS_BASE + SPIS_O_TXFTHR) = ui32TxWatermark & SPIS_TXFTHR_CNT_M;
223
224 //
225 // Configure the format and DMA operation of the SPI Slave.
226 //
227 HWREG(SPIS_BASE + SPIS_O_CFG) = ui32Config & 0x1F;
228 }
229
230 //*****************************************************************************
231 //
242 //
243 //*****************************************************************************
244 extern void SPISDataPut(uint32_t ui32Data);
245
246 //*****************************************************************************
247 //
259 //
260 //*****************************************************************************
261 __STATIC_INLINE int32_t
262 SPISDataPutNonBlocking(uint32_t ui32Data)
263 {
264 //
265 // Check for space to write.
266 //
267 if(!(HWREG(SPIS_BASE + SPIS_O_TXSTAT) & SPIS_TXSTAT_FULL))
268 {
269 HWREG(SPIS_BASE + SPIS_O_TXFPUSH) = ui32Data;
270 return(1);
271 }
272 else
273 {
274 return(0);
275 }
276 }
277
278 //*****************************************************************************
279 //
289 //
290 //*****************************************************************************
291 __STATIC_INLINE void
292 SPISTxFlush(void)
293 {
294 //
295 // Flush the transmit FIFO.
296 //
297 HWREG(SPIS_BASE + SPIS_O_TXFFLUSH) = 0x1;
298
299 //
300 // Clear The Hasdata Flag.
301 //
302 HWREG(SPIS_BASE + SPIS_O_TXFFLAGSCLRN) = ~SPIS_TXFFLAGSCLRN_NOT_EMPTY;
303 }
304
305 //*****************************************************************************
306 //
312 //
313 //*****************************************************************************
314 __STATIC_INLINE uint32_t
315 SPISTxGetNumBytes(void)
316 {
317 //
318 // Return the current number of data elements in the TX FIFO.
319 //
320 return HWREG(SPIS_BASE + SPIS_O_TXFCNT);
321 }
322
323 //*****************************************************************************
324 //
333 //
334 //*****************************************************************************
335 extern uint32_t SPISTxGetValue(uint32_t ui32Index);
336
337 //*****************************************************************************
338 //
352 //
353 //*****************************************************************************
354 extern void SPISDataGet(uint32_t *pui32Data);
355
356 //*****************************************************************************
357 //
372 //
373 //*****************************************************************************
374 __STATIC_INLINE int32_t
375 SPISDataGetNonBlocking(uint32_t *pui32Data)
376 {
377 //
378 // Check for data to read.
379 //
380 if(HWREG(SPIS_BASE + SPIS_O_RXFSTAT) & SPIS_RXFSTAT_NOT_EMPTY)
381 {
382 *pui32Data = HWREG(SPIS_BASE + SPIS_O_RXFPOP);
383 return(1);
384 }
385 else
386 {
387 return(0);
388 }
389 }
390
391 //*****************************************************************************
392 //
404 //
405 //*****************************************************************************
406 __STATIC_INLINE void
407 SPISRxFlush(void)
408 {
409 //
410 // Flush the receive FIFO.
411 //
412 HWREG(SPIS_BASE + SPIS_O_RXFFLUSH) = 0x1;
413
414 //
415 // Clear the HASDATA flag.
416 //
417 HWREG(SPIS_BASE + SPIS_O_RXFFLAGSCLRN) = ~SPIS_RXFFLAGSCLRN_NOT_EMPTY;
418 }
419
420 //*****************************************************************************
421 //
427 //
428 //*****************************************************************************
429 __STATIC_INLINE uint32_t
430 SPISRxGetNumBytes(void)
431 {
432 //
433 // Return the current number of bytes in the RX FIFO.
434 //
435 return HWREG(SPIS_BASE + SPIS_O_RXCNT);
436 }
437
438 //*****************************************************************************
439 //
448 //
449 //*****************************************************************************
450 extern uint32_t SPISRxGetValue(uint32_t ui32Index);
451
452 //*****************************************************************************
453 //
464 //
465 //*****************************************************************************
466 __STATIC_INLINE bool
467 SPISBusy(void)
468 {
469 //
470 // Determine if the SPIS is busy.
471 //
472 return((HWREG(SPIS_BASE + SPIS_O_TXSTAT) & SPIS_TXSTAT_FULL) ? true : false);
473 }
474
475 //*****************************************************************************
476 //
514 //
515 //*****************************************************************************
516 __STATIC_INLINE void
517 SPISIntEnable(uint32_t ui32IntFlags)
518 {
519 //
520 // Set the maskable TX interrupt source.
521 //
522 HWREG(SPIS_BASE + SPIS_O_TXFFLAGSMASK) = ui32IntFlags & SPIS_TX_MASK;
523
524 //
525 // Set the maskable RX interrupt source.
526 //
527 HWREG(SPIS_BASE + SPIS_O_RXFFLAGSMASK) = (ui32IntFlags & SPIS_RX_MASK) >> 8;
528
529 //
530 // Set the maskable general interrupt source.
531 //
532 HWREG(SPIS_BASE + SPIS_O_GPFLAGSMASK) = (ui32IntFlags & SPIS_GP_MASK) >> 16;
533 }
534
535 //*****************************************************************************
536 //
574 //
575 //*****************************************************************************
576 __STATIC_INLINE void
577 SPISIntDisable(uint32_t ui32IntFlags)
578 {
579 //
580 // Disable the maskable TX interrupt source.
581 //
582 HWREG(SPIS_BASE + SPIS_O_TXFFLAGSMASK) &= ~(ui32IntFlags & SPIS_TX_MASK);
583
584 //
585 // Disable the maskable RX interrupt source.
586 //
587 HWREG(SPIS_BASE + SPIS_O_RXFFLAGSMASK) &= ~((ui32IntFlags & SPIS_RX_MASK) >> 8);
588
589 //
590 // Disable the maskable general interrupt source.
591 //
592 HWREG(SPIS_BASE + SPIS_O_GPFLAGSMASK) &= ~((ui32IntFlags & SPIS_GP_MASK) >> 16);
593 }
594
595 //*****************************************************************************
596 //
641 //
642 //*****************************************************************************
643 __STATIC_INLINE void
644 SPISIntClear(uint32_t ui32IntFlags)
645 {
646 //
647 // Clear the TX interrupt source.
648 //
649 HWREG(SPIS_BASE + SPIS_O_TXFFLAGSCLRN) = ~(ui32IntFlags & SPIS_TX_MASK);
650
651 //
652 // Clear the RX interrupt source.
653 //
654 HWREG(SPIS_BASE + SPIS_O_RXFFLAGSCLRN) = ~((ui32IntFlags & SPIS_RX_MASK) >> 8);
655
656 //
657 // Clear the general interrupt source.
658 //
659 HWREG(SPIS_BASE + SPIS_O_GPFLAGS) = ~((ui32IntFlags & SPIS_GP_MASK) >> 16);
660 }
661
662 //*****************************************************************************
663 //
700 //
701 //*****************************************************************************
702 extern uint32_t SPISIntStatus(bool bMasked);
703
704 //*****************************************************************************
705 //
721 //
722 //*****************************************************************************
723 __STATIC_INLINE void
724 SPISIntRegister(void (*pfnHandler)(void))
725 {
726 //
727 // Register the interrupt handler, returning an error if an error occurs.
728 //
729 IntRegister(INT_SPIS, pfnHandler);
730
731 //
732 // Enable the synchronous serial interface interrupt.
733 //
734 IntEnable(INT_SPIS);
735 }
736
737 //*****************************************************************************
738 //
749 //
750 //*****************************************************************************
751 __STATIC_INLINE void
752 SPISIntUnregister(void)
753 {
754 //
755 // Disable the interrupt.
756 //
757 IntDisable(INT_SPIS);
758
759 //
760 // Unregister the interrupt handler.
761 //
762 IntUnregister(INT_SPIS);
763 }
764
765 //*****************************************************************************
766 //
792 //
793 //*****************************************************************************
794 __STATIC_INLINE void
795 SPISDmaEnable( uint32_t ui32DMASetting )
796 {
797 //
798 // Set the requested bits in the SPIS TX DMA control register.
799 //
800 HWREG( SPIS_BASE + SPIS_O_TXFEVSRC ) = ui32DMASetting & SPIS_TXFEVSRC_SEL_M;
801
802 //
803 // Set the requested bits in the SPIS RX DMA control register.
804 //
805 HWREG( SPIS_BASE + SPIS_O_RXFEVSRC ) = ( ui32DMASetting >> 8 ) & SPIS_RXFEVSRC_SEL_M;
806 }
807
808 //*****************************************************************************
809 //
820 //
821 //*****************************************************************************
822 __STATIC_INLINE void
823 SPISDmaDisable( void )
824 {
825 //
826 // Clear the requested bits in the SPIS TX DMA control register.
827 //
828 HWREG( SPIS_BASE + SPIS_O_TXFEVSRC ) = SPIS_TXFEVSRC_SEL_ZERO;
829
830 //
831 // Clear the requested bits in the SPIS RX DMA control register.
832 //
833 HWREG( SPIS_BASE + SPIS_O_RXFEVSRC ) = SPIS_RXFEVSRC_SEL_ZERO;
834 }
835
836 //*****************************************************************************
837 //
838 // Support for DriverLib in ROM:
839 // Redirect to implementation in ROM when available.
840 //
841 //*****************************************************************************
842 #ifndef DRIVERLIB_NOROM
843 #include <driverlib/rom.h>
844 #ifdef ROM_SPISDataPut
845 #undef SPISDataPut
846 #define SPISDataPut ROM_SPISDataPut
847 #endif
848 #ifdef ROM_SPISTxGetValue
849 #undef SPISTxGetValue
850 #define SPISTxGetValue ROM_SPISTxGetValue
851 #endif
852 #ifdef ROM_SPISDataGet
853 #undef SPISDataGet
854 #define SPISDataGet ROM_SPISDataGet
855 #endif
856 #ifdef ROM_SPISRxGetValue
857 #undef SPISRxGetValue
858 #define SPISRxGetValue ROM_SPISRxGetValue
859 #endif
860 #ifdef ROM_SPISIntStatus
861 #undef SPISIntStatus
862 #define SPISIntStatus ROM_SPISIntStatus
863 #endif
864 #endif
865
866 //*****************************************************************************
867 //
868 // Mark the end of the C bindings section for C++ compilers.
869 //
870 //*****************************************************************************
871 #ifdef __cplusplus
872 }
873 #endif
874
875 #endif // __SPIS_H__
876
877 //*****************************************************************************
878 //
881 //
882 //*****************************************************************************
SPISDmaDisable
__STATIC_INLINE void SPISDmaDisable(void)
Disable SPIS DMA operation.
Definition: spis.h:823
SPISIntUnregister
__STATIC_INLINE void SPISIntUnregister(void)
Unregisters an interrupt handler for the Serial Peripheral Interface Slave.
Definition: spis.h:752
SPISIntRegister
__STATIC_INLINE void SPISIntRegister(void(*pfnHandler)(void))
Registers an interrupt handler for the Serial Peripheral Interface Slave.
Definition: spis.h:724
SPISIntStatus
uint32_t SPISIntStatus(bool bMasked)
Gets the current interrupt status.
Definition: spis.c:198
debug.h
SPISDmaEnable
__STATIC_INLINE void SPISDmaEnable(uint32_t ui32DMASetting)
Enable SPIS DMA operation by setting event source.
Definition: spis.h:795
SPISTxGetNumBytes
__STATIC_INLINE uint32_t SPISTxGetNumBytes(void)
Get the current number of data elements in the TX FIFO.
Definition: spis.h:315
SPISDataGet
void SPISDataGet(uint32_t *pui32Data)
Gets a data element from the SPIS Rx FIFO.
Definition: spis.c:141
SPIS_TX_MASK
#define SPIS_TX_MASK
Definition: spis.h:128
SPISRxGetNumBytes
__STATIC_INLINE uint32_t SPISRxGetNumBytes(void)
Get the current number of bytes in the RX FIFO.
Definition: spis.h:430
SPISRxFlush
__STATIC_INLINE void SPISRxFlush(void)
Flush the Rx FIFO.
Definition: spis.h:407
SPISConfig
__STATIC_INLINE void SPISConfig(uint32_t ui32Config, uint32_t ui32RxWatermark, uint32_t ui32TxWatermark)
Configures the SPIS module.
Definition: spis.h:211
SPISIntClear
__STATIC_INLINE void SPISIntClear(uint32_t ui32IntFlags)
Clears SPIS interrupt sources.
Definition: spis.h:644
SPISTxFlush
__STATIC_INLINE void SPISTxFlush(void)
Flush the Tx FIFO.
Definition: spis.h:292
SPIS_RX_MASK
#define SPIS_RX_MASK
Definition: spis.h:136
SPISDataPutNonBlocking
__STATIC_INLINE int32_t SPISDataPutNonBlocking(uint32_t ui32Data)
Puts a data element into the SPIS transmit FIFO.
Definition: spis.h:262
SPIS_GP_MASK
#define SPIS_GP_MASK
Definition: spis.h:143
SPISBusy
__STATIC_INLINE bool SPISBusy(void)
Determines whether the SPIS transmitter is busy or not.
Definition: spis.h:467
interrupt.h
SPISDataPut
void SPISDataPut(uint32_t ui32Data)
Puts a data element into the SPIS transmit FIFO.
Definition: spis.c:94
IntUnregister
void IntUnregister(uint32_t ui32Interrupt)
Unregisters the function to be called when an interrupt occurs.
Definition: interrupt.c:205
SPISTxGetValue
uint32_t SPISTxGetValue(uint32_t ui32Index)
Get a specific value in the Tx FIFO.
Definition: spis.c:115
rom.h
SPISRxGetValue
uint32_t SPISRxGetValue(uint32_t ui32Index)
Get a specific value in the Rx FIFO.
Definition: spis.c:162
SPISIntDisable
__STATIC_INLINE void SPISIntDisable(uint32_t ui32IntFlags)
Disables individual SPIS interrupt sources.
Definition: spis.h:577
SPISIntEnable
__STATIC_INLINE void SPISIntEnable(uint32_t ui32IntFlags)
Enables individual SPIS interrupt sources.
Definition: spis.h:517
SPISDataGetNonBlocking
__STATIC_INLINE int32_t SPISDataGetNonBlocking(uint32_t *pui32Data)
Gets a data element in a non-blocking fashion from the SPIS receive FIFO.
Definition: spis.h:375
IntDisable
void IntDisable(uint32_t ui32Interrupt)
Disables an interrupt.
Definition: interrupt.c:383
IntRegister
void IntRegister(uint32_t ui32Interrupt, void(*pfnHandler)(void))
Registers a function to be called when an interrupt occurs.
Definition: interrupt.c:157
IntEnable
void IntEnable(uint32_t ui32Interrupt)
Enables an interrupt.
Definition: interrupt.c:323