## RFC_MDM

Instance: RFC_MDM
Component: RFC_MDM
Base address: 0x40045000

Component for mdm register bank

### TOP:RFC_MDM Register Summary

Register Name | Type | Register Width (Bits) | Register Reset | Address Offset | Physical Address
MDMENABLE | RW | 32 | 0x0000 0000 | 0x0000 0000 | 0x4004 5000
MDMINIT | RW | 32 | 0x0000 0000 | 0x0000 0004 | 0x4004 5004
MDMPDREQ | RW | 32 | 0x0000 0000 | 0x0000 0008 | 0x4004 5008
DEMENABLE0 | RW | 32 | 0x0000 0000 | 0x0000 000C | 0x4004 500C
DEMENABLE1 | RW | 32 | 0x0000 0000 | 0x0000 0010 | 0x4004 5010
DEMINIT0 | RW | 32 | 0x0000 0000 | 0x0000 0014 | 0x4004 5014
DEMINIT1 | RW | 32 | 0x0000 0000 | 0x0000 0018 | 0x4004 5018
MCESTROBES0 | RW | 32 | 0x0000 0000 | 0x0000 001C | 0x4004 501C
MCESTROBES1 | RW | 32 | 0x0000 0000 | 0x0000 0020 | 0x4004 5020
MCEEVENT0 | RO | 32 | 0x0000 0000 | 0x0000 0024 | 0x4004 5024
MCEEVENT1 | RO | 32 | 0x0000 0000 | 0x0000 0028 | 0x4004 5028
MCEEVENT2 | RO | 32 | 0x0000 0000 | 0x0000 002C | 0x4004 502C
MCEEVENTMSK0 | RW | 32 | 0x0000 0000 | 0x0000 0030 | 0x4004 5030
MCEEVENTMSK1 | RW | 32 | 0x0000 0000 | 0x0000 0034 | 0x4004 5034
MCEEVENTMSK2 | RW | 32 | 0x0000 0000 | 0x0000 0038 | 0x4004 5038
MCEEVENTCLR0 | RW | 32 | 0x0000 0000 | 0x0000 003C | 0x4004 503C
MCEEVENTCLR1 | RW | 32 | 0x0000 0000 | 0x0000 0040 | 0x4004 5040
MCEEVENTCLR2 | RW | 32 | 0x0000 0000 | 0x0000 0044 | 0x4004 5044
MCEPROGRAMSRC | RW | 32 | 0x0000 0000 | 0x0000 0048 | 0x4004 5048
MDMAPI | RW | 32 | 0x0000 0000 | 0x0000 004C | 0x4004 504C
MDMCMDPAR0 | RW | 32 | 0x0000 0000 | 0x0000 0050 | 0x4004 5050
MDMCMDPAR1 | RW | 32 | 0x0000 0000 | 0x0000 0054 | 0x4004 5054
MDMCMDPAR2 | RW | 32 | 0x0000 0000 | 0x0000 0058 | 0x4004 5058
MDMRFCHANNEL | RW | 32 | 0x0000 0000 | 0x0000 005C | 0x4004 505C
MDMSTATUS | RW | 32 | 0x0000 0000 | 0x0000 0060 | 0x4004 5060
MDMFIFOWR | RW | 32 | 0x0000 0000 | 0x0000 0064 | 0x4004 5064
MDMFIFORD | RO | 32 | 0x0000 0000 | 0x0000 0068 | 0x4004 5068
MDMFIFOWRCTRL | RW | 32 | 0x0000 0000 | 0x0000 006C | 0x4004 506C
MDMFIFORDCTRL | RW | 32 | 0x0000 0000 | 0x0000 0070 | 0x4004 5070
MDMFIFOCFG | RW | 32 | 0x0000 0000 | 0x0000 0074 | 0x4004 5074
MDMFIFOSTA | RO | 32 | 0x0000 0000 | 0x0000 0078 | 0x4004 5078
CPEFWEVENT | RW | 32 | 0x0000 0000 | 0x0000 007C | 0x4004 507C
RFESEND | RW | 32 | 0x0000 0000 | 0x0000 0080 | 0x4004 5080
RFERCEV | RO | 32 | 0x0000 0000 | 0x0000 0084 | 0x4004 5084
SMICONF | RW | 32 | 0x0000 0000 | 0x0000 0088 | 0x4004 5088
SMIDLOUTG | RW | 32 | 0x0000 0000 | 0x0000 008C | 0x4004 508C
SMICLOUTG | RW | 32 | 0x0000 0000 | 0x0000 0090 | 0x4004 5090
SMIDLINC | RO | 32 | 0x0000 0000 | 0x0000 0094 | 0x4004 5094
SMICLINC | RO | 32 | 0x0000 0000 | 0x0000 0098 | 0x4004 5098
SMISTA | RO | 32 | 0x0000 0000 | 0x0000 009C | 0x4004 509C
ADCDIGCONF | RW | 32 | 0x0000 0000 | 0x0000 00A0 | 0x4004 50A0
MODPRECTRL | RW | 32 | 0x0000 0000 | 0x0000 00A4 | 0x4004 50A4
MODSYMMAP0 | RW | 32 | 0x0000 0000 | 0x0000 00A8 | 0x4004 50A8
MODSYMMAP1 | RW | 32 | 0x0000 0000 | 0x0000 00AC | 0x4004 50AC
MODSOFTTX | RW | 32 | 0x0000 0000 | 0x0000 00B0 | 0x4004 50B0
MDMBAUD | RW | 32 | 0x0000 0000 | 0x0000 00B4 | 0x4004 50B4
MDMBAUDPRE | RW | 32 | 0x0000 0000 | 0x0000 00B8 | 0x4004 50B8
MODMAIN | RW | 32 | 0x0000 0000 | 0x0000 00BC | 0x4004 50BC
DEMMISC0 | RW | 32 | 0x0000 0000 | 0x0000 00C0 | 0x4004 50C0
DEMMISC1 | RW | 32 | 0x0000 0000 | 0x0000 00C4 | 0x4004 50C4
DEMMISC2 | RW | 32 | 0x0000 0000 | 0x0000 00C8 | 0x4004 50C8
DEMMISC3 | RW | 32 | 0x0000 0000 | 0x0000 00CC | 0x4004 50CC
DEMIQMC0 | RW | 32 | 0x0000 0000 | 0x0000 00D0 | 0x4004 50D0
DEMDSBU | RW | 32 | 0x0000 0000 | 0x0000 00D4 | 0x4004 50D4
DEMCODC0 | RW | 32 | 0x0000 0000 | 0x0000 00D8 | 0x4004 50D8
DEMFIDC0 | RW | 32 | 0x0000 0000 | 0x0000 00DC | 0x4004 50DC
DEMFEXB0 | RW | 32 | 0x0000 0000 | 0x0000 00E0 | 0x4004 50E0
DEMDSXB0 | RW | 32 | 0x0000 0000 | 0x0000 00E4 | 0x4004 50E4
DEMD2XB0 | RW | 32 | 0x0000 0000 | 0x0000 00E8 | 0x4004 50E8
DEMFIFE0 | RW | 32 | 0x0000 0000 | 0x0000 00EC | 0x4004 50EC
DEMMAFI0 | RW | 32 | 0x0000 0000 | 0x0000 00F0 | 0x4004 50F0
DEMMAFI1 | RW | 32 | 0x0000 0000 | 0x0000 00F4 | 0x4004 50F4
DEMMAFI2 | RW | 32 | 0x0000 0000 | 0x0000 00F8 | 0x4004 50F8
DEMMAFI3 | RW | 32 | 0x0000 0000 | 0x0000 00FC | 0x4004 50FC
DEMC1BE0 | RW | 32 | 0x0000 0000 | 0x0000 0100 | 0x4004 5100
DEMC1BE1 | RW | 32 | 0x0000 0000 | 0x0000 0104 | 0x4004 5104
DEMC1BE2 | RW | 32 | 0x0000 0000 | 0x0000 0108 | 0x4004 5108
MDMSYNC0 | RW | 32 | 0x0000 0000 | 0x0000 010C | 0x4004 510C
MDMSYNC1 | RW | 32 | 0x0000 0000 | 0x0000 0110 | 0x4004 5110
MDMSYNC2 | RW | 32 | 0x0000 0000 | 0x0000 0114 | 0x4004 5114
MDMSYNC3 | RW | 32 | 0x0000 0000 | 0x0000 0118 | 0x4004 5118
DEMSWQU0 | RW | 32 | 0x0000 0000 | 0x0000 011C | 0x4004 511C
MODCTRL | RW | 32 | 0x0000 0000 | 0x0000 0120 | 0x4004 5120
MODPREAMBLE | RW | 32 | 0x0000 0000 | 0x0000 0124 | 0x4004 5124
DEMFRAC0 | RW | 32 | 0x0000 0000 | 0x0000 0128 | 0x4004 5128
DEMFRAC1 | RW | 32 | 0x0000 0000 | 0x0000 012C | 0x4004 512C
DEMFRAC2 | RW | 32 | 0x0000 0000 | 0x0000 0130 | 0x4004 5130
DEMFRAC3 | RW | 32 | 0x0000 0000 | 0x0000 0134 | 0x4004 5134
DEMCODC1 | RW | 32 | 0x0000 0000 | 0x0000 0138 | 0x4004 5138
DEMCODC2 | RW | 32 | 0x0000 0000 | 0x0000 013C | 0x4004 513C
DEMFIDC1 | RW | 32 | 0x0000 0000 | 0x0000 0140 | 0x4004 5140
DEMFIDC2 | RW | 32 | 0x0000 0000 | 0x0000 0144 | 0x4004 5144
DEMFIFE1 | RW | 32 | 0x0000 0000 | 0x0000 0148 | 0x4004 5148
DEMTHRD0 | RW | 32 | 0x0000 0000 | 0x0000 014C | 0x4004 514C
DEMTHRD1 | RW | 32 | 0x0000 0000 | 0x0000 0150 | 0x4004 5150
DEMMAFC0 | RW | 32 | 0x0000 0000 | 0x0000 0154 | 0x4004 5154
DEMMAFI4 | RW | 32 | 0x0000 0000 | 0x0000 0158 | 0x4004 5158
DEMSWIMBAL | RW | 32 | 0x0000 0000 | 0x0000 015C | 0x4004 515C
DEMSOFTPDIFF | RW | 32 | 0x0000 0000 | 0x0000 0160 | 0x4004 5160
DEMDEBUG | RW | 32 | 0x0000 0000 | 0x0000 0164 | 0x4004 5164
VITCTRL | RW | 32 | 0x0000 0000 | 0x0000 0168 | 0x4004 5168
VITCOMPUTE | RW | 32 | 0x0000 0000 | 0x0000 016C | 0x4004 516C
VITAPMRDBACK | RO | 32 | 0x0000 0000 | 0x0000 0170 | 0x4004 5170
VITSTATE | RO | 32 | 0x0000 0000 | 0x0000 0174 | 0x4004 5174
VITBRMETRIC10 | RW | 32 | 0x0000 0000 | 0x0000 0178 | 0x4004 5178
VITBRMETRIC32 | RW | 32 | 0x0000 0000 | 0x0000 017C | 0x4004 517C
VITBRMETRIC54 | RW | 32 | 0x0000 0000 | 0x0000 0180 | 0x4004 5180
VITBRMETRIC76 | RW | 32 | 0x0000 0000 | 0x0000 0184 | 0x4004 5184
VITBRSEL0 | RW | 32 | 0x0000 0000 | 0x0000 0188 | 0x4004 5188
VITAPMSEL0 | RW | 32 | 0x0000 0000 | 0x0000 018C | 0x4004 518C
VITBRSEL1 | RW | 32 | 0x0000 0000 | 0x0000 0190 | 0x4004 5190
VITAPMSEL1 | RW | 32 | 0x0000 0000 | 0x0000 0194 | 0x4004 5194
VITBRSEL2 | RW | 32 | 0x0000 0000 | 0x0000 0198 | 0x4004 5198
VITAPMSEL2 | RW | 32 | 0x0000 0000 | 0x0000 019C | 0x4004 519C
VITBRSEL3 | RW | 32 | 0x0000 0000 | 0x0000 01A0 | 0x4004 51A0
VITAPMSEL3 | RW | 32 | 0x0000 0000 | 0x0000 01A4 | 0x4004 51A4
VITBRSEL4 | RW | 32 | 0x0000 0000 | 0x0000 01A8 | 0x4004 51A8
VITAPMSEL4 | RW | 32 | 0x0000 0000 | 0x0000 01AC | 0x4004 51AC
VITBRSEL5 | RW | 32 | 0x0000 0000 | 0x0000 01B0 | 0x4004 51B0
VITAPMSEL5 | RW | 32 | 0x0000 0000 | 0x0000 01B4 | 0x4004 51B4
VITBRSEL6 | RW | 32 | 0x0000 0000 | 0x0000 01B8 | 0x4004 51B8
VITAPMSEL6 | RW | 32 | 0x0000 0000 | 0x0000 01BC | 0x4004 51BC
VITBRSEL7 | RW | 32 | 0x0000 0000 | 0x0000 01C0 | 0x4004 51C0
VITAPMSEL7 | RW | 32 | 0x0000 0000 | 0x0000 01C4 | 0x4004 51C4
LOCMULTA | RW | 32 | 0x0000 0000 | 0x0000 01C8 | 0x4004 51C8
LOCMULTB | RW | 32 | 0x0000 0000 | 0x0000 01CC | 0x4004 51CC
LOCMULTC0 | RO | 32 | 0x0000 0000 | 0x0000 01D0 | 0x4004 51D0
LOCMULTC1 | RO | 32 | 0x0000 0000 | 0x0000 01D4 | 0x4004 51D4
TIMCTRL | RW | 32 | 0x0000 0000 | 0x0000 01D8 | 0x4004 51D8
TIMINC | RW | 32 | 0x0000 0000 | 0x0000 01DC | 0x4004 51DC
TIMPERIOD | RW | 32 | 0x0000 0000 | 0x0000 01E0 | 0x4004 51E0
TIMCOUNTER | RO | 32 | 0x0000 0000 | 0x0000 01E4 | 0x4004 51E4
TIMCAPT | RO | 32 | 0x0000 0000 | 0x0000 01E8 | 0x4004 51E8
TIMEBASE | RW | 32 | 0x0000 0000 | 0x0000 01EC | 0x4004 51EC
COUNT1IN | RW | 32 | 0x0000 0000 | 0x0000 01F0 | 0x4004 51F0
COUNT1RES | RO | 32 | 0x0000 0000 | 0x0000 01F4 | 0x4004 51F4
BRMACC0 | RW | 32 | 0x0000 0000 | 0x0000 01F8 | 0x4004 51F8
BRMACC1 | RO | 32 | 0x0000 0000 | 0x0000 01FC | 0x4004 51FC
BRMACC2 | RO | 32 | 0x0000 0000 | 0x0000 0200 | 0x4004 5200
VITACCCTRL | RW | 32 | 0x0000 0000 | 0x0000 0204 | 0x4004 5204
VITACCRDBIT | RO | 32 | 0x0000 0000 | 0x0000 0208 | 0x4004 5208
MCETRCSEND | RW | 32 | 0x0000 0000 | 0x0000 020C | 0x4004 520C
MCETRCBUSY | RO | 32 | 0x0000 0000 | 0x0000 0210 | 0x4004 5210
MCETRCCMD | RW | 32 | 0x0000 0000 | 0x0000 0214 | 0x4004 5214
MCETRCPAR0 | RW | 32 | 0x0000 0000 | 0x0000 0218 | 0x4004 5218
MCETRCPAR1 | RW | 32 | 0x0000 0000 | 0x0000 021C | 0x4004 521C
RDCAPT0 | RW | 32 | 0x0000 0000 | 0x0000 0220 | 0x4004 5220
DEMCODC3 | RO | 32 | 0x0000 0000 | 0x0000 0224 | 0x4004 5224
DEMCODC4 | RO | 32 | 0x0000 0000 | 0x0000 0228 | 0x4004 5228
DEMMGEX1 | RO | 32 | 0x0000 0000 | 0x0000 022C | 0x4004 522C
DEMMGEX2 | RO | 32 | 0x0000 0000 | 0x0000 0230 | 0x4004 5230
DEMFIDC3 | RO | 32 | 0x0000 0000 | 0x0000 0234 | 0x4004 5234
DEMFIDC4 | RO | 32 | 0x0000 0000 | 0x0000 0238 | 0x4004 5238
DEMCA2P0 | RO | 32 | 0x0000 0000 | 0x0000 023C | 0x4004 523C
DEMPDIF0 | RO | 32 | 0x0000 0000 | 0x0000 0240 | 0x4004 5240
DEMC1BE3 | RO | 32 | 0x0000 0000 | 0x0000 0244 | 0x4004 5244
DEMC1BE4 | RO | 32 | 0x0000 0000 | 0x0000 0248 | 0x4004 5248
DEMC1BE5 | RO | 32 | 0x0000 0000 | 0x0000 024C | 0x4004 524C
DEMFIFE2 | RO | 32 | 0x0000 0000 | 0x0000 0250 | 0x4004 5250
DEMDSBU0 | RO | 32 | 0x0000 0000 | 0x0000 0254 | 0x4004 5254
DEMDSBU1 | RO | 32 | 0x0000 0000 | 0x0000 0258 | 0x4004 5258
DEMSTIM0 | RO | 32 | 0x0000 0000 | 0x0000 025C | 0x4004 525C
DEMSTIM1 | RO | 32 | 0x0000 0000 | 0x0000 0260 | 0x4004 5260
DEMSWQU1 | RO | 32 | 0x0000 0000 | 0x0000 0264 | 0x4004 5264
DEMLQIE0 | RO | 32 | 0x0000 0000 | 0x0000 0268 | 0x4004 5268
DEMSOFD0 | RO | 32 | 0x0000 0000 | 0x0000 026C | 0x4004 526C
RDCAPT1 | RW | 32 | 0x0000 0000 | 0x0000 0270 | 0x4004 5270
DEMTHRD4 | RO | 32 | 0x0000 0000 | 0x0000 0274 | 0x4004 5274
DEMMLSEBIT | RO | 32 | 0x0000 0000 | 0x0000 0278 | 0x4004 5278
DEMBDEC0 | RO | 32 | 0x0000 0000 | 0x0000 027C | 0x4004 527C
DEMBDEC1 | RO | 32 | 0x0000 0000 | 0x0000 0280 | 0x4004 5280
DEMCHFI0 | RO | 32 | 0x0000 0000 | 0x0000 0284 | 0x4004 5284
DEMCHFI1 | RO | 32 | 0x0000 0000 | 0x0000 0288 | 0x4004 5288
DEMFRAC4 | RO | 32 | 0x0000 0000 | 0x0000 028C | 0x4004 528C
DEMFRAC5 | RO | 32 | 0x0000 0000 | 0x0000 0290 | 0x4004 5290
DEMPNSOFT | RO | 32 | 0x0000 0000 | 0x0000 0294 | 0x4004 5294
DEMC1BE6 | RO | 32 | 0x0000 0000 | 0x0000 0298 | 0x4004 5298
DEMC1BE7 | RO | 32 | 0x0000 0000 | 0x0000 029C | 0x4004 529C
DEMC1BE8 | RO | 32 | 0x0000 0000 | 0x0000 02A0 | 0x4004 52A0
DEMC1BE9 | RO | 32 | 0x0000 0000 | 0x0000 02A4 | 0x4004 52A4
DEMC1BEA | RO | 32 | 0x0000 0000 | 0x0000 02A8 | 0x4004 52A8
MDMSPAR0 | RW | 32 | 0x0000 0000 | 0x0000 02AC | 0x4004 52AC
MDMSPAR1 | RW | 32 | 0x0000 0000 | 0x0000 02B0 | 0x4004 52B0
MDMSPAR2 | RW | 32 | 0x0000 0000 | 0x0000 02B4 | 0x4004 52B4
MDMSPAR3 | RW | 32 | 0x0000 0000 | 0x0000 02B8 | 0x4004 52B8
DEMSOFD1 | RO | 32 | 0x0000 0000 | 0x0000 02BC | 0x4004 52BC
DEMSOFD2 | RO | 32 | 0x0000 0000 | 0x0000 02C0 | 0x4004 52C0
DEMSOFD3 | RO | 32 | 0x0000 0000 | 0x0000 02C4 | 0x4004 52C4
DEMSOFD4 | RO | 32 | 0x0000 0000 | 0x0000 02C8 | 0x4004 52C8

### TOP:RFC_MDM Register Descriptions

### TOP:RFC_MDM:MDMENABLE

Address offset | 0x0000 0000
Physical address | 0x4004 5000 | Instance | RFC_MDM
Description | Modem Enable Register
Type | RW

Bits | Field Name | Description | Type | Reset
31:8 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x00 0000
7 | VITACC | Enables the Viterbi Accelator | RW | 0
6 | ADCDIG | Enables the ADC Digital interface | RW | 0
5 | SMI | Enables the Serial Modem Interface | RW | 0
4 | DEMODULATOR | Enables the Demodulator | RW | 0
3 | MODULATOR | Enables the Modulator | RW | 0
2 | TIMEBASE | Enables the Modem Timebase | RW | 0
1 | TXRXFIFO | Enables the TX/RX FIFO | RW | 0
0 | TOPSM | Enables the TOPsm (MCE) | RW | 0

### TOP:RFC_MDM:MDMINIT

Address offset | 0x0000 0004
Physical address | 0x4004 5004 | Instance | RFC_MDM
Description | Modem Initialize Register
Type | RW

Bits | Field Name | Description | Type | Reset
31:8 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x00 0000
7 | VITACC | Synch reset Viterbi Accelator | RW | 0
6 | ADCDIG | Synch reset ADC Digital interface | RW | 0
5 | SMI | Synch reset Serial Modem Interface | RW | 0
4 | DEMODULATOR | Synch reset Demodulator | RW | 0
3 | MODULATOR | Synch reset Modulator | RW | 0
2 | TIMEBASE | Synch reset Modem Timebase | RW | 0
1 | TXRXFIFO | Synch reset TX/RX FIFO | RW | 0
0 | TOPSM | Synch reset TOPsm (MCE) | RW | 0

### TOP:RFC_MDM:MDMPDREQ

Address offset | 0x0000 0008
Physical address | 0x4004 5008 | Instance | RFC_MDM
Description | Modem Power Down Request Register
Type | RW

Bits | Field Name | Description | Type | Reset
31:1 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0000 0000
0 | TOPSMPDREQ | Requests power-down for TOPsm core. If the TOPsm has an ongoing memory access, the hardware will safely gate the clock after the transaction has completed. | RW | 0

### TOP:RFC_MDM:DEMENABLE0

Address offset | 0x0000 000C
Physical address | 0x4004 500C | Instance | RFC_MDM
Description | Demodulator Enable Register 0
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0000
15 | FE23 | Enables the FEC 2/3 module | RW | 0
14 | FE13 | Enables the FEC 1/3 module | RW | 0
13 | FELP | Enables the front-end low-pass filter | RW | 0
12 | THRD | Enables the threshold decision module | RW | 0
11 | FRAC | Enables the fractional resampler | RW | 0
10 | FIDC | Enables the fine DC estimator | RW | 0
9 | CHFI | Enables the channel filter | RW | 0
8 | BDEC | Enables the cascaded dec-by-2 stages (bde1 and bde2) | RW | 0
7 | IQMC | Enables the IQ mismatch compensation | RW | 0
6 | MGE2 | Enables the magnitude estimator engine #2 | RW | 0
5 | MGE1 | Enables the magnitude estimator engine #1 | RW | 0
4 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text) | RW | 0
3 | CODC | Enables the coarse DC estimator | RW | 0
2 | CMI4 | Enables the 1/4 complex mixer | RW | 0
1 | CMIX | Enables the N/1024 complex mixer | RW | 0
0 | HILB | Enables the Hilbert filter | RW | 0

### TOP:RFC_MDM:DEMENABLE1

Address offset | 0x0000 0010
Physical address | 0x4004 5010 | Instance | RFC_MDM
Description | Demodulator Enable Register 1
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0000
15 | VITE | Enables the Viterbi module | RW | 0
14 | MLSE | Enables the MLSE module | RW | 0
13 | SOFD | Enables the soft decision module | RW | 0
12 | SWQU | Enables the sync word qualifier | RW | 0
11 | MAFC | Enables the manual frequency compensation module | RW | 0
10 | MAFI | Enables the matched filter | RW | 0
9 | FIFE | Enables the fine frequency offset estimator | RW | 0
8 | PDIF | Enables the phase differentiation | RW | 0
7 | CA2P | Enables the cart 2 polar conversion | RW | 0
6 | FECP | Enables the fecp module | RW | 0
5 | FEC5 | Enables the fec5 module | RW | 0
4 | C1BE | Enables the correlation 1-bit engine | RW | 0
3 | LQIE | Enables the LQI engine | RW | 0
2 | F4BA | Enables the clock-domain crossing fifo | RW | 0
1 | STIM | Enables the symbol timing tracker | RW | 0
0 | DSBU | Enables the dynamic sample buffer | RW | 0

### TOP:RFC_MDM:DEMINIT0

Address offset | 0x0000 0014
Physical address | 0x4004 5014 | Instance | RFC_MDM
Description | Demodulator Initialize Register 0
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0000
15 | FE23 | Synch reset FEC 2/3 module | RW | 0
14 | FE13 | Synch reset FEC 1/3 module | RW | 0
13 | FELP | Synch reset front-end low-pass filter | RW | 0
12 | THRD | Synch reset threshold decision module | RW | 0
11 | FRAC | Synch reset fractional resampler | RW | 0
10 | FIDC | Synch reset fine DC estimator | RW | 0
9 | CHFI | Synch reset channel filter | RW | 0
8 | BDEC | Synch reset cascaded dec-by-2 stages (bde1 and bde2) | RW | 0
7 | IQMC | Synch reset IQ mismatch compensation | RW | 0
6 | MGE2 | Synch reset magnitude estimator engine #2 | RW | 0
5 | MGE1 | Synch reset magnitude estimator engine #1 | RW | 0
4 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text) | RW | 0
3 | CODC | Synch reset coarse DC estimator | RW | 0
2 | CMI4 | Synch reset 1/4 complex mixer | RW | 0
1 | CMIX | Synch reset N/1024 complex mixer | RW | 0
0 | HILB | Synch reset Hilbert filter | RW | 0

### TOP:RFC_MDM:DEMINIT1

Address offset | 0x0000 0018
Physical address | 0x4004 5018 | Instance | RFC_MDM
Description | Demodulator Initialize Register 1
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0000
15 | VITE | Synch reset Viterbi Module | RW | 0
14 | MLSE | Synch reset MLSE module | RW | 0
13 | SOFD | Synch reset soft decision module | RW | 0
12 | SWQU | Synch reset sync word qualifyer | RW | 0
11 | MAFC | Synch reset manual frequency compensation module | RW | 0
10 | MAFI | Synch reset matched filter | RW | 0
9 | FIFE | Synch reset fine frequency offset estimator | RW | 0
8 | PDIF | Synch reset phase differentiation | RW | 0
7 | CA2P | Synch reset cart 2 polar conversion | RW | 0
6 | FECP | Synch reset fecp module | RW | 0
5 | FEC5 | Synch reset fec5 module | RW | 0
4 | C1BE | Synch reset correlation 1-bit engine | RW | 0
3 | LQIE | Synch reset LQI engine | RW | 0
2 | F4BA | Synch reset clock-domain crossing fifo | RW | 0
1 | STIM | Synch reset symbol timing tracker | RW | 0
0 | DSBU | Synch reset dynamic sample buffer | RW | 0

### TOP:RFC_MDM:MCESTROBES0

Address offset | 0x0000 001C
Physical address | 0x4004 501C | Instance | RFC_MDM
Description | Modem Command Engine (MCE) Strobe Register 0
Type | RW

Bits | Field Name | Description | Type | Reset
31:10 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x00 0000
9 | VITACCSTART | Viterbi Accelerator Start | RW | 0
8 | MLSETERM | Terminate MLSE unit | RW | 0
7 | EVENT3 | Firmware defined RAT event and IRQ | RW | 0
6 | EVENT2 | Firmware defined RAT event and IRQ | RW | 0
5 | EVENT1 | Firmware defined RAT event and IRQ | RW | 0
4 | EVENT0 | Firmware defined RAT event and IRQ | RW | 0
3 | MCETIMBALIGN | Align the 1baud to the next 4baud event | RW | 0
2 | DSBURESTART | Restart DSBU | RW | 0
1 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text) | RW | 0
0 | CMDDONE | Signal command done to CPE | RW | 0

### TOP:RFC_MDM:MCESTROBES1

Address offset | 0x0000 0020
Physical address | 0x4004 5020 | Instance | RFC_MDM
Description | Modem Command Engine (MCE) Strobe Register 1
Type | RW

Bits | Field Name | Description | Type | Reset
31:10 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x00 0000
9 | C1BEPEAKABCMD | Restart C1BE peak A and B search | RW | 0
8 | C1BEPEAKCCMD | Restart C1BE peak C search | RW | 0
7 | C1BEPEAKBCMD | Restart C1BE peak B search | RW | 0
6 | C1BEPEAKACMD | Restart C1BE peak A search | RW | 0
5 | C1BEADVANCECMD | Speed up correlator autocopy with one sample | RW | 0
4 | C1BESTALLCMD | Slow down correlator autocopy with one sample | RW | 0
3:2 | C1BEROTCMD | Correlator rotate command to shift reg B
Value | ENUM name | Description
0x0 | ROT0 | No additional rotation (normal shift-right mode)
0x1 | ROT1R | Rotate 1 sample to the right
0x2 | ROT1L | Rotate 1 sample to the left
0x3 | ROT16R | Rotate 16 samples to the right
| RW | 0x0
1 | C1BECOPYCMD | Copy contents of shift reg A into shift reg B | RW | 0
0 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text) | RW | 0

### TOP:RFC_MDM:MCEEVENT0

Address offset | 0x0000 0024
Physical address | 0x4004 5024 | Instance | RFC_MDM
Description | MCE Event Flag Register 0
Type | RO

Bits | Field Name | Description | Type | Reset
31:16 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0000
15:0 | EVENT | Event flags for timer, timebase and fifo events | RO | 0x0000

### TOP:RFC_MDM:MCEEVENT1

Address offset | 0x0000 0028
Physical address | 0x4004 5028 | Instance | RFC_MDM
Description | MCE Event Flag Register 1
Type | RO

Bits | Field Name | Description | Type | Reset
31:16 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0000
15:0 | EVENT | Event flags for modulator events | RO | 0x0000

### TOP:RFC_MDM:MCEEVENT2

Address offset | 0x0000 002C
Physical address | 0x4004 502C | Instance | RFC_MDM
Description | MCE Event Flag Register 2
Type | RO

Bits | Field Name | Description | Type | Reset
31:16 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0000
15:0 | EVENT | Event flags for demodulator events | RO | 0x0000

### TOP:RFC_MDM:MCEEVENTMSK0

Address offset | 0x0000 0030
Physical address | 0x4004 5030 | Instance | RFC_MDM
Description | MCE Event Mask Register 0
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0000
15:0 | EVENTMSK | Event mask for timer, timebase and fifo events | RW | 0x0000

### TOP:RFC_MDM:MCEEVENTMSK1

Address offset | 0x0000 0034
Physical address | 0x4004 5034 | Instance | RFC_MDM
Description | MCE Event Mask Register 1
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0000
15:0 | EVENTMSK | Event mask for modulator events | RW | 0x0000

### TOP:RFC_MDM:MCEEVENTMSK2

Address offset | 0x0000 0038
Physical address | 0x4004 5038 | Instance | RFC_MDM
Description | MCE Event Mask Register 2
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0000
15:0 | EVENTMSK | Event mask for demodulator events | RW | 0x0000

### TOP:RFC_MDM:MCEEVENTCLR0

Address offset | 0x0000 003C
Physical address | 0x4004 503C | Instance | RFC_MDM
Description | MCE Event Clear Register 0
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0000
15:0 | EVENTCLR | Clear event flag for timer, timebase and fifo events | RW | 0x0000

### TOP:RFC_MDM:MCEEVENTCLR1

Address offset | 0x0000 0040
Physical address | 0x4004 5040 | Instance | RFC_MDM
Description | MCE Event Clear Register 1
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0000
15:0 | EVENTCLR | Clear event flag for modulator events | RW | 0x0000

### TOP:RFC_MDM:MCEEVENTCLR2

Address offset | 0x0000 0044
Physical address | 0x4004 5044 | Instance | RFC_MDM
Description | MCE Event Clear Register 2
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0000
15:0 | EVENTCLR | Clear event flag for demodulator events | RW | 0x0000

### TOP:RFC_MDM:MCEPROGRAMSRC

Address offset | 0x0000 0048
Physical address | 0x4004 5048 | Instance | RFC_MDM
Description | MCE Program Source Configuration
Type | RW

Bits | Field Name | Description | Type | Reset
31:4 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x000 0000
3:1 | ROMBANK | MCE ROM configuration
Value | ENUM name | Description
0x0 | B0 | Map access to bank 0
0x1 | B1 | Map access to bank 1
0x2 | B2 | Map access to bank 2
0x3 | B3 | Map access to bank 3
0x4 | B4 | Map access to bank 4
0x5 | B5 | Map access to bank 5
| RW | 0x0
0 | RAMROM | Map MCE RAM as ROM
Value | ENUM name | Description
0 | ROM | Execute program code from the mapped ROM bank
1 | RAM | Execute program code from RAM bank instead of ROM
| RW | 0

### TOP:RFC_MDM:MDMAPI

Address offset | 0x0000 004C
Physical address | 0x4004 504C | Instance | RFC_MDM
Description | Modem API Command Register
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0000
15:8 | PROTOCOLID | Protocol ID | RW | 0x00
7:0 | MDMCMD | Modem command | RW | 0x00

### TOP:RFC_MDM:MDMCMDPAR0

Address offset | 0x0000 0050
Physical address | 0x4004 5050 | Instance | RFC_MDM
Description | Modem API Command Parameter 0
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0000
15:0 | PAR0 | Parameter 0. Software defined function. | RW | 0x0000

### TOP:RFC_MDM:MDMCMDPAR1

Address offset | 0x0000 0054
Physical address | 0x4004 5054 | Instance | RFC_MDM
Description | Modem API Command Parameter 1
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0000
15:0 | PAR1 | Parameter 1. Software defined function. | RW | 0x0000

### TOP:RFC_MDM:MDMCMDPAR2

Address offset | 0x0000 0058
Physical address | 0x4004 5058 | Instance | RFC_MDM
Description | Modem API Command Parameter 2
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0000
15:0 | PAR | Parameter 2. Software defined function. | RW | 0x0000

### TOP:RFC_MDM:MDMRFCHANNEL

Address offset | 0x0000 005C
Physical address | 0x4004 505C | Instance | RFC_MDM
Description | Modem RF Channel Register
Type | RW

Bits | Field Name | Description | Type | Reset
31:12 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0 0000
11:0 | VALUE | RF channel in MHz (i.e. 2432). This register is only software defined for signalling RF channel. | RW | 0x000

### TOP:RFC_MDM:MDMSTATUS

Address offset | 0x0000 0060
Physical address | 0x4004 5060 | Instance | RFC_MDM
Description | Modem Command Status Register
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0000
15:0 | VALUE | Diverse status, error, report bits from MCE. Controlled by software. | RW | 0x0000

### TOP:RFC_MDM:MDMFIFOWR

Address offset | 0x0000 0064
Physical address | 0x4004 5064 | Instance | RFC_MDM
Description | Modem FIFO Write Register
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0000
15:0 | PAYLOADIN | FIFO write port. The actual port size is configurable in MDMFIFOWRCTRL.FIFOWRCTRL. | RW | 0x0000

### TOP:RFC_MDM:MDMFIFORD

Address offset | 0x0000 0068
Physical address | 0x4004 5068 | Instance | RFC_MDM
Description | Modem FIFO Read Register
Type | RO

Bits | Field Name | Description | Type | Reset
31:16 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0000
15:0 | PAYLOADOUT | FIFO read port. The actual port size is configurable in MDMFIFORDCTRL.FIFORDCTRL. | RO | 0x0000

### TOP:RFC_MDM:MDMFIFOWRCTRL

Address offset | 0x0000 006C
Physical address | 0x4004 506C | Instance | RFC_MDM
Description | Modem FIFO Write Configuration
Type | RW

Bits | Field Name | Description | Type | Reset
31:5 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x000 0000
4 | FIFOWRPORT | FIFO write port mapping
Value | ENUM name | Description
0 | MDMFIFOWR | The MDMFIFOWR register is used for write access
1 | MODEM | Modem has write access
| RW | 0
3:0 | WORDSZWR | Actual bits in every word write access
Value | ENUM name | Description
0x0 | BITS1 | 1 bit
0x1 | BITS2 | 2 bits
0x2 | BITS3 | 3 bits
0x3 | BITS4 | 4 bits
0x4 | BITS5 | 5 bits
0x5 | BITS6 | 6 bits
0x6 | BITS7 | 7 bits
0x7 | BITS8 | 8 bits
0x8 | BITS9 | 9 bits
0x9 | BITS10 | 10 bits
0xA | BITS11 | 11 bits
0xB | BITS12 | 12 bits
0xC | BITS13 | 13 bits
0xD | BITS14 | 14 bits
0xE | BITS15 | 15 bits
0xF | BITS16 | 16 bits
| RW | 0x0

### TOP:RFC_MDM:MDMFIFORDCTRL

Address offset | 0x0000 0070
Physical address | 0x4004 5070 | Instance | RFC_MDM
Description | Modem FIFO Read Configuration
Type | RW

Bits | Field Name | Description | Type | Reset
31:5 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x000 0000
4 | FIFORDPORT | FIFO read port mapping
Value | ENUM name | Description
0 | MDMFIFORD | The MDMFIFORD register is used for read access
1 | MODEM | Modem has read access
| RW | 0
3:0 | WORDSZRD | Actual bits in every word read access
Value | ENUM name | Description
0x0 | BITS1 | 1 bit
0x1 | BITS2 | 2 bits
0x2 | BITS3 | 3 bits
0x3 | BITS4 | 4 bits
0x4 | BITS5 | 5 bits
0x5 | BITS6 | 6 bits
0x6 | BITS7 | 7 bits
0x7 | BITS8 | 8 bits
0x8 | BITS9 | 9 bits
0x9 | BITS10 | 10 bits
0xA | BITS11 | 11 bits
0xB | BITS12 | 12 bits
0xC | BITS13 | 13 bits
0xD | BITS14 | 14 bits
0xE | BITS15 | 15 bits
0xF | BITS16 | 16 bits
| RW | 0x0

### TOP:RFC_MDM:MDMFIFOCFG

Address offset | 0x0000 0074
Physical address | 0x4004 5074 | Instance | RFC_MDM
Description | Modem FIFO Configuration for watermark thresholds
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0000
15:8 | AFULLTHR | Almost full threshold value in bits. This threshold affects the MDMFIFOSTA.ALMOSTFULL and MDMFIFOSTA.TXREADY status bits. The FIFO can hold up to 64 bits. | RW | 0x00
7:0 | AEMPTYTHR | Almost empty threshold in bits. This threshold affects the MDMFIFOSTA.ALMOSTEMPTY and MDMFIFOSTA.RXVALID status bits. The FIFO can hold up to 64 bits. | RW | 0x00

### TOP:RFC_MDM:MDMFIFOSTA

Address offset | 0x0000 0078
Physical address | 0x4004 5078 | Instance | RFC_MDM
Description | Modem FIFO Status Flags
Type | RO

Bits | Field Name | Description | Type | Reset
31:6 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x000 0000
5 | OVERFLOW | FIFO overflow error. If this flag is asserted the modem FIFO must be re-initialized with MDMINIT.TXRXFIFO to clear it. Note that re-initializing will flush the FIFO. | RO | 0
4 | ALMOSTFULL | FIFO is almost full. Asserts when the FIFO fill level is above the almost full threshold. | RO | 0
3 | ALMOSTEMPTY | FIFO is almost empty. Asserts when the FIFO fill level is below the almost empty threshold. | RO | 0
2 | UNDERFLOW | FIFO underflow error. If this flag is asserted the modem FIFO must be re-initialized with MDMINIT.TXRXFIFO to clear it. | RO | 0
1 | RXVALID | A full data word is valid and can be read in MDMRXFIFO register read port. | RO | 0
0 | TXREADY | The MDMTXFIFO register write port is ready to receive a data word. | RO | 0

### TOP:RFC_MDM:CPEFWEVENT

Address offset | 0x0000 007C
Physical address | 0x4004 507C | Instance | RFC_MDM
Description | CPE-to-MCE Firmware Triggered Events
Type | RW

Bits | Field Name | Description | Type | Reset
31:4 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x000 0000
3 | EVENT3 | Generic FW CPE-driven event to MCE. Software defined meaning. | RW | 0
2 | EVENT2 | Generic FW CPE-driven event to MCE. Software defined meaning. | RW | 0
1 | EVENT1 | Generic FW CPE-driven event to MCE. Software defined meaning. | RW | 0
0 | EVENT0 | Generic FW CPE-driven event to MCE. Software defined meaning. | RW | 0

### TOP:RFC_MDM:RFESEND

Address offset | 0x0000 0080
Physical address | 0x4004 5080 | Instance | RFC_MDM
Description | MCE-to-RFE Send Command Register
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0000
15:0 | MCECMD | Command to send to RFE. Writing to this register will trigger an event in the RFE, and the command value written here will be readable in RFC_RFE:MCERCEV register. | RW | 0x0000

### TOP:RFC_MDM:RFERCEV

Address offset | 0x0000 0084
Physical address | 0x4004 5084 | Instance | RFC_MDM
Description | RFE-to-MCE Receive Command Register
Type | RO

Bits | Field Name | Description | Type | Reset
31:16 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0000
15:0 | RFECMD | Command received from RFE | RO | 0x0000

### TOP:RFC_MDM:SMICONF

Address offset | 0x0000 0088
Physical address | 0x4004 5088 | Instance | RFC_MDM
Description | Serial Modem Interface Configuration
Type | RW

Bits | Field Name | Description | Type | Reset
31:9 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x00 0000
8 | SMIENABLE | Enables the SMI interface | RW | 0
7:4 | PRESCALER | Configures the SMI rate | RW | 0x0
3:0 | MLENGTH | Configures the Message Length | RW | 0x0

### TOP:RFC_MDM:SMIDLOUTG

Address offset | 0x0000 008C
Physical address | 0x4004 508C | Instance | RFC_MDM
Description | Serial Modem Interface Data Output Register
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0000
15:0 | DL | Outgoing data link message | RW | 0x0000

### TOP:RFC_MDM:SMICLOUTG

Address offset | 0x0000 0090
Physical address | 0x4004 5090 | Instance | RFC_MDM
Description | Serial Modem Interface Control Output Register
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0000
15:0 | CL | Outgoing command link message | RW | 0x0000

### TOP:RFC_MDM:SMIDLINC

Address offset | 0x0000 0094
Physical address | 0x4004 5094 | Instance | RFC_MDM
Description | Serial Modem Interface Data Input Register
Type | RO

Bits | Field Name | Description | Type | Reset
31:16 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0000
15:0 | DL | Incoming data link message | RO | 0x0000

### TOP:RFC_MDM:SMICLINC

Address offset | 0x0000 0098
Physical address | 0x4004 5098 | Instance | RFC_MDM
Description | Serial Modem Interface Control Input Register
Type | RO

Bits | Field Name | Description | Type | Reset
31:16 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0000
15:0 | CL | Incoming command link message | RO | 0x0000

### TOP:RFC_MDM:SMISTA

Address offset | 0x0000 009C
Physical address | 0x4004 509C | Instance | RFC_MDM
Description | Serial Modem Interface Status Register
Type | RO

Bits | Field Name | Description | Type | Reset
31:2 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0000 0000
1 | INCCLERROR | Incoming command link has errors | RO | 0
0 | INCDLERROR | Incoming data link has errors | RO | 0

### TOP:RFC_MDM:ADCDIGCONF

Address offset | 0x0000 00A0
Physical address | 0x4004 50A0 | Instance | RFC_MDM
Description | ADC Digital Interface Configuration
Type | RW

Bits | Field Name | Description | Type | Reset
31:2 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0000 0000
1 | QBRANCHEN | Enables Q component data branch in ADCDIG | RW | 0
0 | IBRANCHEN | Enables I component data branch in ADCDIG | RW | 0

### TOP:RFC_MDM:MODPRECTRL

Address offset | 0x0000 00A4
Physical address | 0x4004 50A4 | Instance | RFC_MDM
Description | Modulator Preamble Control
Type | RW

Bits | Field Name | Description | Type | Reset
31:8 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x00 0000
7:4 | REPS | Number of preamble repetitions of preamble pattern
Value | ENUM name | Description
0x0 | REPS1 | 1 repetition (i.e. only once)
0x1 | REPS2 | 2 repetitions
0x2 | REPS3 | 3 repetitions
0x3 | REPS4 | 4 repetitions
0x4 | REPS5 | 5 repetitions
0x5 | REPS6 | 6 repetitions
0x6 | REPS7 | 7 repetitions
0x7 | REPS8 | 8 repetitions
0x8 | REPS9 | 9 repetitions
0x9 | REPS10 | 10 repetitions
0xA | REPS11 | 11 repetitions
0xB | REPS12 | 12 repetitions
0xC | REPS13 | 13 repetitions
0xD | REPS14 | 14 repetitions
0xE | REPS15 | 15 repetitions
0xF | REPS16 | 16 repetitions
| RW | 0x0
3:0 | SIZE | Preamble pattern size in bits
Value | ENUM name | Description
0x3 | BITS4 | 4 bits
0x7 | BITS8 | 8 bits
0xF | BITS16 | 16 bits
| RW | 0x0

### TOP:RFC_MDM:MODSYMMAP0

Address offset | 0x0000 00A8
Physical address | 0x4004 50A8 | Instance | RFC_MDM
Description | Modulator Symbol Mapping Register 0
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0000
15:12 | SYM3 | Decimal value for bits '11' | RW | 0x0
11:8 | SYM2 | Decimal value for bits '01' | RW | 0x0
7:4 | SYM1 | Decimal value for bit '1' | RW | 0x0
3:0 | SYM0 | Decimal value for bit '0' | RW | 0x0

### TOP:RFC_MDM:MODSYMMAP1

Address offset | 0x0000 00AC
Physical address | 0x4004 50AC | Instance | RFC_MDM
Description | Modulator Symbol Mapping Register 1
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0000
15:12 | SYM7 | Decimal value for bits '111' | RW | 0x0
11:8 | SYM6 | Decimal value for bits '110' | RW | 0x0
7:4 | SYM5 | Decimal value for bits '101' | RW | 0x0
3:0 | SYM4 | Decimal value for bits '100' | RW | 0x0

### TOP:RFC_MDM:MODSOFTTX

Address offset | 0x0000 00B0
Physical address | 0x4004 50B0 | Instance | RFC_MDM
Description | Modulator Soft Symbol Transmit
Type | RW

Bits | Field Name | Description | Type | Reset
31:4 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x000 0000
3:0 | SOFTSYMBOL | Soft symbol {-7..+7} used when MODCTRL.SOFTTXENABLE is enabled | RW | 0x0

### TOP:RFC_MDM:MDMBAUD

Address offset | 0x0000 00B4
Physical address | 0x4004 50B4 | Instance | RFC_MDM
Description | Modem Baud Rate Control
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0000
15:0 | RATEWORD | Rate word (bits [20:5]). The 5 LSBs of the 21-bit rate word are defined in MDMBAUDPRE.EXTRATEWORD register. | RW | 0x0000

### TOP:RFC_MDM:MDMBAUDPRE

Address offset | 0x0000 00B8
Physical address | 0x4004 50B8 | Instance | RFC_MDM
Description | Modem Baud Rate Prescaler Control
Type | RW

Bits | Field Name | Description | Type | Reset
31:13 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0 0000
12:8 | EXTRATEWORD | Extended Rate Word (bits [4:0]). These are the 5 LSBs extending the 16 MSBs configured in MDMBAUD.RATEWORD to form a 21 bit rate word. | RW | 0x00
7 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text) | RW | 0
6:4 | ALIGNVALUE | Align value for timebase after sync | RW | 0x0
3:0 | PRESCALER | Prescaler value, range 1 to 15 | RW | 0x0

### TOP:RFC_MDM:MODMAIN

Address offset | 0x0000 00BC
Physical address | 0x4004 50BC | Instance | RFC_MDM
Description | Modulator Main Config Register
Type | RW

Bits | Field Name | Description | Type | Reset
31:8 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x00 0000
7:6 | SPREADFACTOR | Modem spreading factor, only used when spreading has been enabled in FECSELECT
Value | ENUM name | Description
0x0 | FACTOR2 | Factor 2
0x1 | FACTOR4 | Factor 4
0x2 | FACTOR8 | Factor 8
| RW | 0x0
5:2 | FECSELECT | Forward Error Correction Selection
Value | ENUM name | Description
0x0 | NOSEL | No FEC encoding selected
0x1 | IEEE15_4 | IEEE 802.15.4
0x2 | CC85XX | CC85xx compatible FEC
0x4 | SPREAD | Spread
0x5 | FEC13 | 1/3 repetition code
0x6 | FEC23 | 10/15 BT BR FEC 2/3 Mode
0x8 | IEEE15_4G_NOREC | IEEE 802.15.4g non-recursive code
0x9 | IEEE15_4G_REC | IEEE 802.15.4g recursive code
| RW | 0x0
1:0 | MODLEVELS | Number of modulation levels
Value | ENUM name | Description
0x0 | LVL2 | 2 levels
0x1 | LVL4 | 4 levels
0x2 | LVL8 | 8 levels
| RW | 0x0

### TOP:RFC_MDM:DEMMISC0

Address offset | 0x0000 00C0
Physical address | 0x4004 50C0 | Instance | RFC_MDM
Description | Demodulator Config Register 0
Type | RW

Bits | Field Name | Description | Type | Reset
31:13 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0 0000
12 | CMI4FMIXSIGN | Demodulator front-end complex Fs/4 mixer setting
Value | ENUM name | Description
0 | POS | Use Fmix = +Fs/4
1 | NEG | Use Fmix = -Fs/4
| RW | 0
11 | HILBREMOVEREAL | Demodulator front-end Hilbert filter setting
Value | ENUM name | Description
0 | IMAG | Remove imaginary freq part
1 | REAL | Remove real freq part
| RW | 0
10 | HILBEN | Demodulator front-end Hilbert filter control
Value | ENUM name | Description
0 | DIS | Disable filter. Data passthrough.
1 | EN | Enable Hilbert filter
| RW | 0
9:0 | CMIXN | Signed factor of mixer phasor, Fmix=n*Fs/1024 , where n in range [-512, 511] | RW | 0x000

### TOP:RFC_MDM:DEMMISC1

Address offset | 0x0000 00C4
Physical address | 0x4004 50C4 | Instance | RFC_MDM
Description | Demodulator Config Register 1
Type | RW

Bits | Field Name | Description | Type | Reset
31:4 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x000 0000
3:2 | MGE2SRCSEL | Source select second magnitude estimator
Value | ENUM name | Description
0x0 | FIDC | Output of the FIDC (x4 samples)
0x1 | FEXB1 | Output of the FEXB, as selected by DEMFEXB0.OUT2SRCSEL register
0x2 | CHFI | Output of CHFI
| RW | 0x0
1:0 | CHFIBW | Select bandwidth (cut-off frequency) of demodulator channel filter
Value | ENUM name | Description
0x0 | BW0_5 | 0.5 * Fs. Using FIR filter with taps [3 0 -9 0 20 0 -46 0 160 256 160 0 -46 0 20 0 -9 0 3].
0x1 | BW0_3333 | 0.33333 * Fs. Using FIR filter with taps [0 4 6 0 -16 -25 0 65 138 170 138 65 0 -25 -16 0 6 4 0].
0x2 | BW0_41667 | 0.41667 * Fs. Using FIR filter with taps [-1 -4 2 12 4 -25 -31 38 154 213 154 38 -31 -25 4 12 2 -4 -1].
0x3 | BW0_5SHORT | 0.5 * Fs (shorter filter). Using FIR filter with taps [-1 2 7 7 2 -1].
| RW | 0x0

### TOP:RFC_MDM:DEMMISC2

Address offset | 0x0000 00C8
Physical address | 0x4004 50C8 | Instance | RFC_MDM
Description | Demodulator Config Register 2
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0000
15:14 | LQIPERIOD | LQI measurement period
Value | ENUM name | Description
0x0 | SYM16 | 16 symbols
0x1 | SYM64 | 64 symbols
0x2 | SYM256 | 256 symbols
0x3 | SYM1024 | 1024 symbols
| RW | 0x0
13 | MLSERUN | Enable maximum likelihood sequence estimation (MLSE) desicions | RW | 0
12:11 | MAFCGAIN | Set gain in MAFC. Multiplies symbols with 2^N before symbol recovery stage | RW | 0x0
10 | STIMESTONLY | Only perform symbol timing error estimation in STIM, without doing timing correction
Value | ENUM name | Description
0 | DIS | Perform both estimation and correct timing
1 | EN | Perform estimation only (no timing correction)
| RW | 0
9:7 | STIMTEAPERIOD | Symbol timing error accumulator period (4 to 128 symbols) in STIM
Value | ENUM name | Description
0x0 | SYM4 | 4 symbols
0x1 | SYM8 | 8 symbols
0x2 | SYM16 | 16 symbols
0x3 | SYM32 | 32 symbols
0x4 | SYM64 | 64 symbols
0x5 | SYM128 | 128 symbols
| RW | 0x0
6:4 | STIMTEAGAIN | Symbol timing error accumulator gain in STIM
Value | ENUM name | Description
0x0 | DIV512 | Gain is 1/512
0x1 | DIV256 | Gain is 1/256
0x2 | DIV128 | Gain is 1/128
0x3 | DIV64 | Gain is 1/64
0x4 | DIV32 | Gain is 1/32
0x5 | DIV16 | Gain is 1/16
0x6 | DIV8 | Gain is 1/8
0x7 | DIV4 | Gain is 1/4
| RW | 0x0
3 | PDIFLINPREDEN | Enable linear predictor in PDIF at CORDIC output | RW | 0
2 | PDIFDESPECKLEREN | Enable despeckler in PDIF at CORDIC output | RW | 0
1 | PDIFIQCONJEN | Conjugate the complex I/Q signal in PDIF | RW | 0
0 | PDIFLIMITRANGE | Limit range on maximal PDIF output, i.e. instantaneous frequency sample
Value | ENUM name | Description
0 | DIS | Allow full 8-bit range, i.e. +/- 128
1 | EN | Limit the range to 7-bit, i.e. +/- 64
| RW | 0

### TOP:RFC_MDM:DEMMISC3

Address offset | 0x0000 00CC
Physical address | 0x4004 50CC | Instance | RFC_MDM
Description | Demodulator Config Register 3
Type | RW

Bits | Field Name | Description | Type | Reset
31:11 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x00 0000
10:9 | BDE1DVGA | DVGA settings for BDE1. The DVGA control for BDE1 is shared with the RFE in its RFC_RFE:GAINCTRL.BDE1DVGA register. Software should determine who uses them. Please note that if both processors attempt to control it, the resulting setting will be the two settings ORed together.
Value | ENUM name | Description
0x0 | GAIN1 | Gain 1
0x1 | GAIN2 | Gain 2
0x2 | GAIN4 | Gain 4
0x3 | GAIN8 | Gain 8
| RW | 0x0
8:7 | BDE2DVGA | DVGA settings for BDE2. The DVGA control for BDE2 is shared with the RFE in its RFC_RFE:GAINCTRL.BDE2DVGA register. Software should determine who uses them. Please note that if both processors attempt to control it, the resulting setting will be the two settings ORed together.
Value | ENUM name | Description
0x0 | GAIN1 | Gain 1
0x1 | GAIN2 | Gain 2
0x2 | GAIN4 | Gain 4
0x3 | GAIN8 | Gain 8
| RW | 0x0
6:5 | BDE1NUMSTAGES | BDE1 decimation filter setting
Value | ENUM name | Description
0x0 | DIV1 | Decimate by 1 (no decimation)
0x1 | DIV2 | Decimate by 2
0x2 | DIV4 | Decimate by 4
| RW | 0x0
4:3 | PDIFDECIM | Additional decimation in PDIF
Value | ENUM name | Description
0x0 | DIV1 | No decimation
0x1 | DIV2 | Decimate by 2
0x2 | DIV4 | Decimate by 4
| RW | 0x0
2:0 | BDECNUMSTAGES | BDE2 decimation filter setting
Value | ENUM name | Description
0x0 | DIV1 | Decimate by 1 (no decimation)
0x1 | DIV2 | Decimate by 2
0x2 | DIV4 | Decimate by 4
0x3 | DIV8 | Decimate by 8
0x4 | DIV16 | Decimate by 16
| RW | 0x0

### TOP:RFC_MDM:DEMIQMC0

Address offset | 0x0000 00D0
Physical address | 0x4004 50D0 | Instance | RFC_MDM
Description | Demodulator I/Q Mismatch Compensation Register
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0000
15:8 | GAINFACTOR | Gain factor to compensate for unequal gains between the I and Q signal paths in the analog RF front-end. The compensation is done by scaling the I path amplitude (no compensation of Q path). The gain factor is given as an unsigned number in the range [0,255] corresponding to gain factor range [0,2], where value 128 gives gain factor 1.0 (no gain). Any gain compensation is applied in a stage after the phase compensation. | RW | 0x00
7:0 | PHASEFACTOR | Phase factor to compensate for unorthogonal I and Q signals. The phase factor is given as a signed number in the range [-128,127] corresponding to phase factor range [-0.5, 0.496], where the phase factor can be calculated as phase_factor = tan(phase_error). This gives an available phase error compensation range of [-26.6, 26.4] degrees. | RW | 0x00

### TOP:RFC_MDM:DEMDSBU

Address offset | 0x0000 00D4
Physical address | 0x4004 50D4 | Instance | RFC_MDM
Description | Dynamic Sample Buffer Config Register
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0000
15:8 | DSBUAVGLENGTH | Length for moving average of the newest DSBU samples | RW | 0x00
7:0 | DSBUDELAY | Output delay from sample buffer, as offset between write and read pointers | RW | 0x00

### TOP:RFC_MDM:DEMCODC0

Address offset | 0x0000 00D8
Physical address | 0x4004 50D8 | Instance | RFC_MDM
Description | Demodulator Coarse DC Offset Estimator Register 0
Type | RW

Bits | Field Name | Description | Type | Reset
31:12 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0 0000
11 | ESTSEL | Select which estimator to show as readable output
Value | ENUM name | Description
0 | ACC | Read back latest accumulator estimate
1 | IIR | Read back latest IIR estimate
| RW | 0
10:9 | COMPSEL | Select estimator to use for coarse DC offset compensation
Value | ENUM name | Description
0x0 | MANUAL | Use manually programmable values from DEMCODC1 and DEMCODC2 registers
0x2 | ACC | Compensate with latest accumulator estimate
0x3 | IIR | Compensate with latest IIR estimate
| RW | 0x0
8 | IIRUSEINITIAL | When enabled, a configurable value is loaded to initialize IIR filter when CODC estimator is re-initialized
Value | ENUM name | Description
0 | DIS | Initialize IIR filter with value zero
1 | EN | Use the manual compensation values in DEMCODC1 and DEMCODC2 for initialization
| RW | 0
7:5 | IIRGAIN | Adjust first-order IIR filter adaptation which controls filter bandwidth
Value | ENUM name | Description
0x0 | OFF | Filter disabled
0x1 | DIV16 | Use 1/16 IIR adaptation
0x2 | DIV32 | Use 1/32 IIR adaptation
0x3 | DIV64 | Use 1/64 IIR adaptation
0x4 | DIV128 | Use 1/128 IIR adaptation
0x5 | DIV256 | Use 1/256 IIR adaptation
0x6 | DIV512 | Use 1/512 IIR adaptation
0x7 | DIV1024 | Use 1/1024 IIR adaptation
| RW | 0x0
4 | IIREN | Enable first-order IIR filter inside CODC
Value | ENUM name | Description
0 | DIS | Disable IIR estimator
1 | EN | Enable IIR estimator
| RW | 0
3 | ACCCONTMODE | Accumulator estimator mode
Value | ENUM name | Description
0 | SINGLE | Generate a single DC estimate only, then stop
1 | CONT | Generate new DC estimates continuously
| RW | 0
2:1 | ACCPERIOD | Integration period for accumulator estimator
Value | ENUM name | Description
0x0 | SMPL8 | 8 samples
0x1 | SMPL32 | 32 samples
0x2 | SMPL128 | 128 samples
0x3 | SMPL512 | 512 samples
| RW | 0x0
0 | ACCEN | Enable accumulator based estimator inside CODC
Value | ENUM name | Description
0 | DIS | Disable accumulator estimator
1 | EN | Enable accumulator estimator
| RW | 0

### TOP:RFC_MDM:DEMFIDC0

Address offset | 0x0000 00DC
Physical address | 0x4004 50DC | Instance | RFC_MDM
Description | Demodulator Fine DC Offset Estimator Register 0
Type | RW

Bits | Field Name | Description | Type | Reset
31:6 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x000 0000
5:4 | COMPSEL | Select estimator to use for fine DC offset compensation
Value | ENUM name | Description
0x0 | MANUAL | Use manually programmable values from DEMFIDC1 and DEMFIDC2 registers
0x2 | ACC | Compensate with latest accumulator estimate
| RW | 0x0
3:2 | ACCPERIOD | Integration period for accumulator estimator
Value | ENUM name | Description
0x0 | SMPL8 | 8 samples
0x1 | SMPL32 | 32 samples
0x2 | SMPL128 | 128 samples
0x3 | SMPL512 | 512 samples
| RW | 0x0
1 | ACCCONTMODE | Accumulator estimator mode
Value | ENUM name | Description
0 | SINGLE | Generate a single DC estimate only, then stop
1 | CONT | Generate new DC estimates continuously
| RW | 0
0 | ACCEN | Enable accumulator based estimator inside FIDC
Value | ENUM name | Description
0 | DIS | Disable accumulator estimator
1 | EN | Enable accumulator estimator
| RW | 0

### TOP:RFC_MDM:DEMFEXB0

Address offset | 0x0000 00E0
Physical address | 0x4004 50E0 | Instance | RFC_MDM
Description | Demodulator Front-End Crossbar Register 0
Type | RW

Bits | Field Name | Description | Type | Reset
31:14 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0 0000
13 | OUT2PASSTHROUGH | Front-end crossbar output #2 is direct passthrough of the crossbar input | RW | 0
12:11 | OUT2SRCSEL | Source select for XBAR output #2 (towards magnitude estimation engine MGE1)
Value | ENUM name | Description
0x0 | HILB | Source is Hilbert filter (HILB)
0x1 | CMIX | Source is complex N*Fs/1024 mixer (CMIX)
0x2 | CMI4 | Source is complex Fs/4 mixer (CMI4)
0x3 | CODC | Source is coarse DC remover (CODC)
| RW | 0x0
10 | OUT1PASSTHROUGH | Front-end crossbar output #1 is direct passthrough of the crossbar input | RW | 0
9:8 | OUT1SRCSEL | Source select for XBAR output #1 (main output, towards BDE2 and rest of demodulator)
Value | ENUM name | Description
0x0 | HILB | Source is Hilbert filter (HILB)
0x1 | CMIX | Source is complex N*Fs/1024 mixer (CMIX)
0x2 | CMI4 | Source is complex Fs/4 mixer (CMI4)
0x3 | CODC | Source is coarse DC remover (CODC)
| RW | 0x0
7:6 | B4SRCSEL | Source select for CODC (XBAR block #4)
Value | ENUM name | Description
0x0 | INPUT | Source is crossbar main input
0x1 | HILB | Source is Hilbert filter (HILB)
0x2 | CMIX | Source is complex N*Fs/1024 mixer (CMIX)
0x3 | CMI4 | Source is complex Fs/4 mixer (CMI4)
| RW | 0x0
5:4 | B3SRCSEL | Source select for CMI4 (XBAR block #3)
Value | ENUM name | Description
0x0 | INPUT | Source is crossbar main input
0x1 | HILB | Source is Hilbert filter (HILB)
0x2 | CMIX | Source is complex N*Fs/1024 mixer (CMIX)
0x3 | CODC | Source is coarse DC remover (CODC)
| RW | 0x0
3:2 | B2SRCSEL | Source select for CMIX (XBAR block #2)
Value | ENUM name | Description
0x0 | INPUT | Source is crossbar main input
0x1 | HILB | Source is Hilbert filter (HILB)
0x2 | CMI4 | Source is complex Fs/4 mixer (CMI4)
0x3 | CODC | Source is coarse DC remover (CODC)
| RW | 0x0
1:0 | B1SRCSEL | Source select for HILB (XBAR block #1)
Value | ENUM name | Description
0x0 | INPUT | Source is crossbar main input
0x1 | CMIX | Source is complex N*Fs/1024 mixer (CMIX)
0x2 | CMI4 | Source is complex Fs/4 mixer (CMI4)
0x3 | CODC | Source is coarse DC remover (CODC)
| RW | 0x0

### TOP:RFC_MDM:DEMDSXB0

Address offset | 0x0000 00E4
Physical address | 0x4004 50E4 | Instance | RFC_MDM
Description | Demodulator Decode Stage Crossbar Register 0
Type | RW

Bits | Field Name | Description | Type | Reset
31:14 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0 0000
13 | OUT2PASSTHROUGH | Crossbar output #2 is direct passthrough of the crossbar input | RW | 0
12 | OUT1PASSTHROUGH | Crossbar output #1 is direct passthrough of the crossbar input | RW | 0
11:10 | OUTSRCSEL2 | Source select XBAR output, branch 1 (baud branch)
Value | ENUM name | Description
0x0 | FIFE | Source is fine frequency offset estimator (FIFE)
0x1 | MAFI | Source is matched filter (MAFI)
0x2 | C1BE | Source is 1-bit correlation engine (C1BE)
| RW | 0x0
9:8 | OUTSRCSEL1 | Source select for XBAR output, branch 2 (flushed branch)
Value | ENUM name | Description
0x0 | FIFE | Source is fine frequency offset estimator (FIFE)
0x1 | MAFI | Source is matched filter (MAFI)
0x2 | C1BE | Source is 1-bit correlation engine (C1BE)
| RW | 0x0
7:6 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text) | RW | 0x0
5:4 | B3SRCSEL | Source select for C1BE (XBAR block #3)
Value | ENUM name | Description
0x0 | INPUT | Source is crossbar main input
0x1 | FIFE | Source is fine frequency offset estimator (FIFE)
0x2 | MAFI | Source is matched filter (MAFI)
| RW | 0x0
3:2 | B2SRCSEL | Source select for MAFI (XBAR block #2)
Value | ENUM name | Description
0x0 | INPUT | Source is crossbar main input
0x1 | FIFE | Source is fine frequency offset estimator (FIFE)
0x2 | C1BE | Source is 1-bit correlation engine (C1BE)
| RW | 0x0
1:0 | B1SRCSEL | Source select for FIFE (XBAR block #1)
Value | ENUM name | Description
0x0 | INPUT | Source is crossbar main input
0x1 | MAFI | Source is matched filter (MAFI)
0x2 | C1BE | Source is 1-bit correlation engine (C1BE)
| RW | 0x0

### TOP:RFC_MDM:DEMD2XB0

Address offset | 0x0000 00E8
Physical address | 0x4004 50E8 | Instance | RFC_MDM
Description | Demodulator Decode Stage Second Crossbar Register 0
Type | RW

Bits | Field Name | Description | Type | Reset
31:10 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x00 0000
9 | OUT2PASSTHROUGH | Crossbar output #2 is direct passthrough of the crossbar input | RW | 0
8 | OUT1PASSTHROUGH | Crossbar output #1 is direct passthrough of the crossbar input | RW | 0
7:6 | OUTSRCSEL2 | Source select XBAR output, branch 1 (towards MLSE)
Value | ENUM name | Description
0x0 | MAFC | Source is Manual Frequency Compensation (MAFC)
0x1 | STIM | Source is Symbol Timing (STIM)
| RW | 0x0
5:4 | OUTSRCSEL1 | Source select for XBAR output, branch 2 (towards SOFD)
Value | ENUM name | Description
0x0 | MAFC | Source is Manual Frequency Compensation (MAFC)
0x1 | STIM | Source is Symbol Timing (STIM)
| RW | 0x0
3:2 | B2SRCSEL | Source select for STIM (XBAR block #2)
Value | ENUM name | Description
0x0 | INPUT | Source is crossbar main input
0x1 | MAFC | Source is Manual Frequency Compensation (MAFC)
| RW | 0x0
1:0 | B1SRCSEL | Source select for MAFC (XBAR block #1)
Value | ENUM name | Description
0x0 | INPUT | Source is crossbar main input
0x1 | STIM | Source is Symbol Timing (STIM)
| RW | 0x0

### TOP:RFC_MDM:DEMFIFE0

Address offset | 0x0000 00EC
Physical address | 0x4004 50EC | Instance | RFC_MDM
Description | Demodulator Fine Frequency Offset Estimator Register 0
Type | RW

Bits | Field Name | Description | Type | Reset
31:12 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0 0000
11 | FINEFOESEL | Select which estimator to show as readable output
Value | ENUM name | Description
0 | IIR | Latest IIR estimate
1 | ACC | Latest accumulator estimate
| RW | 0
10:9 | FOCFFSEL | Select which estimate source to be used in feed-forward compensation point
Value | ENUM name | Description
0x0 | IIR | Compensate with latest IIR estimate
0x1 | ACC | Compensate with latest accumulator estimate
0x2 | MANUAL | Use programmable manual value from register bank
| RW | 0x0
8 | ACCCNTMODE | Accumulator estimator mode
Value | ENUM name | Description
0 | SINGLE | Generate a single frequency offset estimate only, then stop
1 | CONT | Generate new frequency offset estimates continuously
| RW | 0
7:6 | ACCPERIOD | Integration period for accumulator
Value | ENUM name | Description
0x0 | 64 | 64 samples
0x1 | 128 | 128 samples
0x2 | 256 | 256 samples
0x3 | 512 | 512 samples
| RW | 0x0
5 | ACCEN | Enable accumulator based frequency offset estimator inside FIFE
Value | ENUM name | Description
0 | DIS | Disable accumulator estimator
1 | EN | Enable accumulator estimator
| RW | 0
4 | IIRUSEINITIAL | When enabled, a configurable value is loaded to initialize IIR filter when FIFE estimator is re-initialized.
Value | ENUM name | Description
0 | DIS | Initialize IIR filter with value zero
1 | EN | Use the manual compensation value in DEMFIFE1 for initialization
| RW | 0
3:1 | IIRGAIN | Adjust first-order IIR filter adaptation which controls filter bandwidth
Value | ENUM name | Description
0x0 | OFF | Filter disabled
0x1 | DIV16 | Use 1/16 IIR adaptation
0x2 | DIV32 | Use 1/32 IIR adaptation
0x3 | DIV64 | Use 1/64 IIR adaptation
0x4 | DIV128 | Use 1/128 IIR adaptation
0x5 | DIV256 | Use 1/256 IIR adaptation
0x6 | DIV512 | Use 1/512 IIR adaptation
0x7 | DIV1024 | Use 1/1024 IIR adaptation
| RW | 0x0
0 | IIREN | Enable first-order IIR filter based freq offset estimator inside FIFE
Value | ENUM name | Description
0 | DIS | Disable IIR estimator
1 | EN | Enable IIR estimator
| RW | 0

### TOP:RFC_MDM:DEMMAFI0

Address offset | 0x0000 00F0
Physical address | 0x4004 50F0 | Instance | RFC_MDM
Description | Demodulator Matched Filter Register 0
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0000
15:8 | C1C7 | Filter coefficient c1 (and c7) | RW | 0x00
7:0 | C0C8 | Filter coefficient c0 (and c8) | RW | 0x00

### TOP:RFC_MDM:DEMMAFI1

Address offset | 0x0000 00F4
Physical address | 0x4004 50F4 | Instance | RFC_MDM
Description | Demodulator Matched Filter Register 1
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0000
15:8 | C3C5 | Filter coefficient c3 (and c5) | RW | 0x00
7:0 | C2C6 | Filter coefficient c2 (and c6) | RW | 0x00

### TOP:RFC_MDM:DEMMAFI2

Address offset | 0x0000 00F8
Physical address | 0x4004 50F8 | Instance | RFC_MDM
Description | Demodulator Matched Filter Register 2
Type | RW

Bits | Field Name | Description | Type | Reset
31:9 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x00 0000
8:0 | C4 | Filter coefficient c4. The matched filter will have unity gain when the sum of all coefficients c0 to c8 equals 512. | RW | 0x000

### TOP:RFC_MDM:DEMMAFI3

Address offset | 0x0000 00FC
Physical address | 0x4004 50FC | Instance | RFC_MDM
Description | Demodulator Matched Filter Register 3
Type | RW

Bits | Field Name | Description | Type | Reset
31:9 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x00 0000
8:0 | K | Output level adjustment. Adjusting LSB of k will adjust LSB of matched filter output accordingly. | RW | 0x000

### TOP:RFC_MDM:DEMC1BE0

Address offset | 0x0000 0100
Physical address | 0x4004 5100 | Instance | RFC_MDM
Description | Demodulator Correlator 1-bit Engine Register 0
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0000
15:11 | MASKB | Mask for correlator B to select the correlator length to use. The number specifies number of nibbles (i.e. 4-bit block, which typically corresponds to one symbol) of the correlator holding the oldest samples that will be ignored in computations. When set to zero, the full 128 sample (=32 symbol) correlator length will be used. | RW | 0x00
10:6 | MASKA | Mask for correlator A to select the correlator length to use. The number specifies number of nibbles (i.e. 4-bit block, which typically corresponds to one symbol) of the correlator holding the oldest samples that will be ignored in computations. When set to zero, the full 128 sample (=32 symbol) correlator length will be used. | RW | 0x00
5:4 | CASCCONF | Correlator cascade configuration
Value | ENUM name | Description
0x0 | SINGLE | Correlator B not used
0x1 | SERIAL | Connect correlators in series (A -> B)
0x2 | PARALLEL | Connect correlators in parallel
| RW | 0x0
3:0 | COPYCONF | Control auto copy of contents from corr A to corr B | RW | 0x0

### TOP:RFC_MDM:DEMC1BE1

Address offset | 0x0000 0104
Physical address | 0x4004 5104 | Instance | RFC_MDM
Description | Demodulator Correlator 1-bit Engine Register 1
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0000
15:8 | THRESHOLDB | Correlation threshold value for correlator B | RW | 0x00
7:0 | THRESHOLDA | Correlation threshold value for correlator A | RW | 0x00

### TOP:RFC_MDM:DEMC1BE2

Address offset | 0x0000 0108
Physical address | 0x4004 5108 | Instance | RFC_MDM
Description | Demodulator Correlator 1-bit Engine Register 2
Type | RW

Bits | Field Name | Description | Type | Reset
31:10 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x00 0000
9:8 | PEAKCONF | Configuration to control peak event generation
Value | ENUM name | Description
0x0 | THRESH | Trigger peak event on all peaks above threshold
0x1 | BEST | Trigger peak event only if peak is highest in correlator since search start
0x2 | BESTAB | Trigger peak event for combined highest peak search for corr A and B
| RW | 0x0
7:0 | THRESHOLDC | Correlation threshold value for correlator C (corr C is corr A+B combined) | RW | 0x00

### TOP:RFC_MDM:MDMSYNC0

Address offset | 0x0000 010C
Physical address | 0x4004 510C | Instance | RFC_MDM
Description | Modem Sync Word Register 0
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0000
15:0 | SWA15C0 | Sync word A bits 15:0. Sync words shorter than 32 bits must be stored as most signicant bits of sync word A. The sync word is expected to be transmitted/received in lsb to msb order. | RW | 0x0000

### TOP:RFC_MDM:MDMSYNC1

Address offset | 0x0000 0110
Physical address | 0x4004 5110 | Instance | RFC_MDM
Description | Modem Sync Word Register 1
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0000
15:0 | SWA31C16 | Sync word A bits 31:16. Sync words shorter than 32 bits must be stored as most significant bits of sync word A. The sync word is expected to be transmitted/received in lsb to msb order. | RW | 0x0000

### TOP:RFC_MDM:MDMSYNC2

Address offset | 0x0000 0114
Physical address | 0x4004 5114 | Instance | RFC_MDM
Description | Modem Sync Word Register 2
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0000
15:0 | SWB15C0 | Sync word B bits 15:0. Sync words shorter than 32 bits must be stored as most significant bits of sync word B. The sync word is expected to be transmitted/received in lsb to msb order. | RW | 0x0000

### TOP:RFC_MDM:MDMSYNC3

Address offset | 0x0000 0118
Physical address | 0x4004 5118 | Instance | RFC_MDM
Description | Modem Sync Word Register 3
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0000
15:0 | SWB31C16 | Sync word B bits 31:16. Sync words shorter than 32 bits must be stored as most significant bits of sync word B. The sync word is expected to be transmitted/received in lsb to msb order. | RW | 0x0000

### TOP:RFC_MDM:DEMSWQU0

Address offset | 0x0000 011C
Physical address | 0x4004 511C | Instance | RFC_MDM
Description | Demodulator Sync Word Qualifier Register 0
Type | RW

Bits | Field Name | Description | Type | Reset
31:7 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x000 0000
6 | AUTOMAFC | Let sync word qualifier automatically control the manual frequency offset compensation (MAFC) block when it is running
Value | ENUM name | Description
0 | DIS | Keep manual control over MAFC
1 | EN | Give control to sync word qualifier
| RW | 0
5 | RUN | Start/stop sync word qualifier | RW | 0
4:0 | REFLEN | Bit length of sync word qualifier reference vector, constituted by (reflen + 1) most significant bits of sync word A and/or B. | RW | 0x00

### TOP:RFC_MDM:MODCTRL

Address offset | 0x0000 0120
Physical address | 0x4004 5120 | Instance | RFC_MDM
Description | Dynamic Modem Control Signals from MCE
Type | RW

Bits | Field Name | Description | Type | Reset
31:10 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x00 0000
9 | PARBITQUALEN | Enable Parallel Bit Qualifier (read DEMC1BEA) | RW | 0
8:7 | STIMEARLYLATE | Controls STIM module for early/late modes
Value | ENUM name | Description
0x0 | NORMAL | Normal Mode
0x1 | LATE | STIM starts late
0x2 | EARLY | STIM starts early
| RW | 0x0
6 | EARLYLATE | Set the C1BE in special early/late mode | RW | 0
5 | SOFTPDIFFMODE | Enable Soft PDIFF mode for RX | RW | 0
4 | SOFTTXENABLE | Enable SOFT TX mode, controlled via MODSOFTTX | RW | 0
3 | FECENABLE | Global FEC modes enable | RW | 0
2 | FEC5TERMINATE | Goes into termination mode in 5Mbps TX FEC | RW | 0
1 | TONEINSERT | Inserts a tone | RW | 0
0 | PREAMBLEINSERT | Inserts preamble | RW | 0

### TOP:RFC_MDM:MODPREAMBLE

Address offset | 0x0000 0124
Physical address | 0x4004 5124 | Instance | RFC_MDM
Description | Dynamic Modulator Preamble Register
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0000
15:0 | WORD | 16 bit preamble word pattern. The LSB is transmitted first. | RW | 0x0000

### TOP:RFC_MDM:DEMFRAC0

Address offset | 0x0000 0128
Physical address | 0x4004 5128 | Instance | RFC_MDM
Description | Demodulator Fractional Resampler Register 0
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0000
15:0 | P15C0 | Downsampler P[15:0]. Sample rate of the output signal: Fs_out = Fs_in * P/Q. The hardware requires the resampling factor P/Q to be in the range [1/4, 1], i.e. only down-sampling with a factor in the range [1,4] is supported. | RW | 0x0000

### TOP:RFC_MDM:DEMFRAC1

Address offset | 0x0000 012C
Physical address | 0x4004 512C | Instance | RFC_MDM
Description | Demodulator Fractional Resampler Register 1
Type | RW

Bits | Field Name | Description | Type | Reset
31:12 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0 0000
11:0 | P27C16 | Downsampler P[27:16] | RW | 0x000

### TOP:RFC_MDM:DEMFRAC2

Address offset | 0x0000 0130
Physical address | 0x4004 5130 | Instance | RFC_MDM
Description | Demodulator Fractional Resampler Register 2
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0000
15:0 | Q15C0 | Downsampler Q[15:0]. Sample rate of the output signal: Fs_out = Fs_in * P/Q. The hardware requires the resampling factor P/Q to be in the range [1/4, 1], i.e. only down-sampling with a factor in the range [1,4] is supported. | RW | 0x0000

### TOP:RFC_MDM:DEMFRAC3

Address offset | 0x0000 0134
Physical address | 0x4004 5134 | Instance | RFC_MDM
Description | Demodulator Fractional Resampler Register 3
Type | RW

Bits | Field Name | Description | Type | Reset
31:12 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0 0000
11:0 | Q27C16 | Downsampler Q[27:16] | RW | 0x000

### TOP:RFC_MDM:DEMCODC1

Address offset | 0x0000 0138
Physical address | 0x4004 5138 | Instance | RFC_MDM
Description | Demodulator Coarse DC Offset Estimator Register 1
Type | RW

Bits | Field Name | Description | Type | Reset
31:13 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0 0000
12:0 | COMPIVAL | Compensation value, I branch | RW | 0x0000

### TOP:RFC_MDM:DEMCODC2

Address offset | 0x0000 013C
Physical address | 0x4004 513C | Instance | RFC_MDM
Description | Demodulator Coarse DC Offset Estimator Register 2
Type | RW

Bits | Field Name | Description | Type | Reset
31:13 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0 0000
12:0 | COMPQVAL | Compensation value, Q branch | RW | 0x0000

### TOP:RFC_MDM:DEMFIDC1

Address offset | 0x0000 0140
Physical address | 0x4004 5140 | Instance | RFC_MDM
Description | Demodulator Fine DC Offset Estimator Register 1
Type | RW

Bits | Field Name | Description | Type | Reset
31:13 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0 0000
12:0 | COMPIVAL | Compensation value for I path | RW | 0x0000

### TOP:RFC_MDM:DEMFIDC2

Address offset | 0x0000 0144
Physical address | 0x4004 5144 | Instance | RFC_MDM
Description | Demodulator Fine DC Offset Estimator Register 2
Type | RW

Bits | Field Name | Description | Type | Reset
31:13 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0 0000
12:0 | COMPQVAL | Compensation value for Q path | RW | 0x0000

### TOP:RFC_MDM:DEMFIFE1

Address offset | 0x0000 0148
Physical address | 0x4004 5148 | Instance | RFC_MDM
Description | Demodulator Fine Frequency Offset Estimator Register 1
Type | RW

Bits | Field Name | Description | Type | Reset
31:8 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x00 0000
7:0 | FOCFBREGVAL | Value for feed-back compensation point (signed) | RW | 0x00

### TOP:RFC_MDM:DEMTHRD0

Address offset | 0x0000 014C
Physical address | 0x4004 514C | Instance | RFC_MDM
Description | Demodulator Soft Decision Threshold Register 0
Type | RW

Bits | Field Name | Description | Type | Reset
31:15 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0 0000
14:8 | THR2 | Threshold 2 (between +3 and +5 symbols) | RW | 0x00
7 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0
6:0 | THR1 | Threshold 1 (between +1 and +3 symbols) | RW | 0x00

### TOP:RFC_MDM:DEMTHRD1

Address offset | 0x0000 0150
Physical address | 0x4004 5150 | Instance | RFC_MDM
Description | Demodulator Soft Decision Threshold Register 1
Type | RW

Bits | Field Name | Description | Type | Reset
31:7 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x000 0000
6:0 | THR3 | Threshold 3 (between +5 and +7 symbols) | RW | 0x00

### TOP:RFC_MDM:DEMMAFC0

Address offset | 0x0000 0154
Physical address | 0x4004 5154 | Instance | RFC_MDM
Description | Demodulator Manual Frequency Compensation Register 0
Type | RW

Bits | Field Name | Description | Type | Reset
31:8 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x00 0000
7:0 | COMPVAL | Value for manual compensation (signed) | RW | 0x00

### TOP:RFC_MDM:DEMMAFI4

Address offset | 0x0000 0158
Physical address | 0x4004 5158 | Instance | RFC_MDM
Description | Demodulator Matched Filter Register 4
Type | RW

Bits | Field Name | Description | Type | Reset
31:8 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x00 0000
7:0 | TERM_VAL | Input value to terminate matched filter with. Writing to this register triggers the termination. | RW | 0x00

### TOP:RFC_MDM:DEMSWIMBAL

Address offset | 0x0000 015C
Physical address | 0x4004 515C | Instance | RFC_MDM
Description | Demodulator Sync Word DC Imbalance Register
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0000
15:8 | IMBALB | DC imbalance in sync word B, applied via SWQU upon C1BE correlator A peak event | RW | 0x00
7:0 | IMBALA | DC imbalance in sync word A, applied via SWQU upon C1BE correlator B peak event | RW | 0x00

### TOP:RFC_MDM:DEMSOFTPDIFF

Address offset | 0x0000 0160
Physical address | 0x4004 5160 | Instance | RFC_MDM
Description | Demodulator Soft PDIFF Value Register
Type | RW

Bits | Field Name | Description | Type | Reset
31:8 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x00 0000
7:0 | SOFTPDIFF | Replaces PDIFF output when in Soft PDIFF Mode. Can be used for manually feeding samples (e.g. on-off-keying (OOK) samples from RFE) into the demodulator decode stage. | RW | 0x00

### TOP:RFC_MDM:DEMDEBUG

Address offset | 0x0000 0164
Physical address | 0x4004 5164 | Instance | RFC_MDM
Description | Demodulator Debug Register
Type | RW

Bits | Field Name | Description | Type | Reset
31:9 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x00 0000
8:5 | DECSTAGEDEBUG | Selects which decode stage signal source to dump for debugging via S2R module. The decode stage samples are signed 8-bit samples, packed into 32-bit words with the oldest sample as the most significant byte.
Value | ENUM name | Description
0x0 | NOSEL | No source selected
0x1 | PDIF | Dump PDIF output samples
0x2 | MAFI | Dump MAFI output samples
0x3 | STIM | Dump STIM output samples
0x4 | MAFC | Dump MAFC output samples
0x5 | C1BE | Dump C1BE correlator A value (truncated to 8 LSBs only, may overflow if correlator value is +128).
0x6 | SOFD | Dump SOFD output samples
0x8 | TRIGGER | The most significant bit is used as manual event trigger to start a new sample capture via S2R module when RFC_S2R:S2RCFG.TRIGGERMODE is set to trigger-on-event and the S2R module has been armed via RFC_S2R:S2RCFG.TRIGGER bit.
| RW | 0x0
4:1 | FRONTENDDEBUG | Selects which front-end stage signal source to dump for debugging via S2R module. The front-end stage samples are signed 16-bit samples from both I and Q signal path, packed together into 32-bit words with the I sample as the 16 MSB and Q sample as the 16 LSB.
Value | ENUM name | Description
0x0 | NOSEL | No source selected
0x1 | FELP | Dump FELP output samples
0x2 | IQMC | Dump IQMC output samples
0x3 | BDE1 | Dump BDE1 output samples
0x4 | FEXB2 | Dump FEXB output #2 samples, as selected by DEMFEXB0.OUT2SRCSEL register
0x5 | BDE2 | Dump BDE2 output samples
0x6 | CHFI | Dump CHFI output samples
0x7 | FRAC | Dump FRAC output samples
0x8 | TRIGGER | The most significant bit is used as manual event trigger to start a new sample capture via S2R module when RFC_S2R:S2RCFG.TRIGGERMODE is set to trigger-on-event and the S2R module has been armed via RFC_S2R:S2RCFG.TRIGGER bit.
| RW | 0x0
0 | LOOPBACKMODE | Enables loopback mode | RW | 0

### TOP:RFC_MDM:VITCTRL

Address offset | 0x0000 0168
Physical address | 0x4004 5168 | Instance | RFC_MDM
Description | Viterbi Control Register
Type | RW

Bits | Field Name | Description | Type | Reset
31:10 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x00 0000
9:6 | READEPTH | Depth of the REA algorithm | RW | 0x0
5:2 | APMRDBACKSEL | Selects the APM to read back via VITAPMRDBACK register
Value | ENUM name | Description
0x0 | NOSEL | No selection
0x8 | APM0 | View APM 0
0x9 | APM1 | View APM 1
0xA | APM2 | View APM 2
0xB | APM3 | View APM 3
0xC | APM4 | View APM 4
0xD | APM5 | View APM 5
0xE | APM6 | View APM 6
0xF | APM7 | View APM 7
| RW | 0x0
1 | ACSITERATIONS | Number of iterations per ACS element
Value | ENUM name | Description
0 | CODE12 | 2 iterations per ACS (2 branches, 1/2 codes)
1 | CODE23 | 4 iterations per ACS (4 branches, 2/3 codes)
| RW | 0
0 | SOFTMETRICS | Enable Soft Metrics
Value | ENUM name | Description
0 | MET5M | Use 5Mbps Metrics
1 | SOFT | Use soft Metrics (register based)
| RW | 0

### TOP:RFC_MDM:VITCOMPUTE

Address offset | 0x0000 016C
Physical address | 0x4004 516C | Instance | RFC_MDM
Description | Viterbi Compute Register
Type | RW

Bits | Field Name | Description | Type | Reset
31:1 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0000 0000
0 | COMPUTE | Initiates a compute cycle | RW | 0

### TOP:RFC_MDM:VITAPMRDBACK

Address offset | 0x0000 0170
Physical address | 0x4004 5170 | Instance | RFC_MDM
Description | Viterbi APM Readback Register
Type | RO

Bits | Field Name | Description | Type | Reset
31:10 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x00 0000
9:0 | VALUE | APM for element i (selected in VITCTRL register) | RO | 0x000

### TOP:RFC_MDM:VITSTATE

Address offset | 0x0000 0174
Physical address | 0x4004 5174 | Instance | RFC_MDM
Description | Viterbi State Register
Type | RO

Bits | Field Name | Description | Type | Reset
31:3 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0000 0000
2:0 | VALUE | Current Winning State | RO | 0x0

### TOP:RFC_MDM:VITBRMETRIC10

Address offset | 0x0000 0178
Physical address | 0x4004 5178 | Instance | RFC_MDM
Description | Viterbi Branch Metric 1 and 0 Register
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0000
15:8 | MET1 | Branch Metric 1 | RW | 0x00
7:0 | MET0 | Branch Metric 0 | RW | 0x00

### TOP:RFC_MDM:VITBRMETRIC32

Address offset | 0x0000 017C
Physical address | 0x4004 517C | Instance | RFC_MDM
Description | Viterbi Branch Metric 3 and 2 Register
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0000
15:8 | MET3 | Branch Metric 3 | RW | 0x00
7:0 | MET2 | Branch Metric 2 | RW | 0x00

### TOP:RFC_MDM:VITBRMETRIC54

Address offset | 0x0000 0180
Physical address | 0x4004 5180 | Instance | RFC_MDM
Description | Viterbi Branch Metric 5 and 4 Register
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0000
15:8 | MET5 | Branch Metric 5 | RW | 0x00
7:0 | MET4 | Branch Metric 4 | RW | 0x00

### TOP:RFC_MDM:VITBRMETRIC76

Address offset | 0x0000 0184
Physical address | 0x4004 5184 | Instance | RFC_MDM
Description | Viterbi Branch Metric 7 and 6 Register
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0000
15:8 | MET7 | Branch Metric 7 | RW | 0x00
7:0 | MET6 | Branch Metric 6 | RW | 0x00

### TOP:RFC_MDM:VITBRSEL0

Address offset | 0x0000 0188
Physical address | 0x4004 5188 | Instance | RFC_MDM
Description | Viterbi Branch Select Register 0
Type | RW

Bits | Field Name | Description | Type | Reset
31:12 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0 0000
11:9 | BR3MUX | ACS Element 0, Branch Metric Mux 3 | RW | 0x0
8:6 | BR2MUX | ACS Element 0, Branch Metric Mux 2 | RW | 0x0
5:3 | BR1MUX | ACS Element 0, Branch Metric Mux 1 | RW | 0x0
2:0 | BR0MUX | ACS Element 0, Branch Metric Mux 0 | RW | 0x0

### TOP:RFC_MDM:VITAPMSEL0

Address offset | 0x0000 018C
Physical address | 0x4004 518C | Instance | RFC_MDM
Description | Viterbi APM Select Register 0
Type | RW

Bits | Field Name | Description | Type | Reset
31:12 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0 0000
11:9 | APM3MUX | ACS Element 0, Accumulated Path Metric Mux 3 | RW | 0x0
8:6 | APM2MUX | ACS Element 0, Accumulated Path Metric Mux 2 | RW | 0x0
5:3 | APM1MUX | ACS Element 0, Accumulated Path Metric Mux 1 | RW | 0x0
2:0 | APM0MUX | ACS Element 0, Accumulated Path Metric Mux 0 | RW | 0x0

### TOP:RFC_MDM:VITBRSEL1

Address offset | 0x0000 0190
Physical address | 0x4004 5190 | Instance | RFC_MDM
Description | Viterbi Branch Select Register 1
Type | RW

Bits | Field Name | Description | Type | Reset
31:12 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0 0000
11:9 | BR3MUX | ACS Element 1, Branch Metric Mux 3 | RW | 0x0
8:6 | BR2MUX | ACS Element 1, Branch Metric Mux 2 | RW | 0x0
5:3 | BR1MUX | ACS Element 1, Branch Metric Mux 1 | RW | 0x0
2:0 | BR0MUX | ACS Element 1, Branch Metric Mux 0 | RW | 0x0

### TOP:RFC_MDM:VITAPMSEL1

Address offset | 0x0000 0194
Physical address | 0x4004 5194 | Instance | RFC_MDM
Description | Viterbi APM Select Register 1
Type | RW

Bits | Field Name | Description | Type | Reset
31:12 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0 0000
11:9 | APM3MUX | ACS Element 1, Accumulated Path Metric Mux 3 | RW | 0x0
8:6 | APM2MUX | ACS Element 1, Accumulated Path Metric Mux 2 | RW | 0x0
5:3 | APM1MUX | ACS Element 1, Accumulated Path Metric Mux 1 | RW | 0x0
2:0 | APM0MUX | ACS Element 1, Accumulated Path Metric Mux 0 | RW | 0x0

### TOP:RFC_MDM:VITBRSEL2

Address offset | 0x0000 0198
Physical address | 0x4004 5198 | Instance | RFC_MDM
Description | Viterbi Branch Select Register 2
Type | RW

Bits | Field Name | Description | Type | Reset
31:12 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0 0000
11:9 | BR3MUX | ACS Element 2, Branch Metric Mux 3 | RW | 0x0
8:6 | BR2MUX | ACS Element 2, Branch Metric Mux 2 | RW | 0x0
5:3 | BR1MUX | ACS Element 2, Branch Metric Mux 1 | RW | 0x0
2:0 | BR0MUX | ACS Element 2, Branch Metric Mux 0 | RW | 0x0

### TOP:RFC_MDM:VITAPMSEL2

Address offset | 0x0000 019C
Physical address | 0x4004 519C | Instance | RFC_MDM
Description | Viterbi APM Select Register 2
Type | RW

Bits | Field Name | Description | Type | Reset
31:12 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0 0000
11:9 | APM3MUX | ACS Element 2, Accumulated Path Metric Mux 3 | RW | 0x0
8:6 | APM2MUX | ACS Element 2, Accumulated Path Metric Mux 2 | RW | 0x0
5:3 | APM1MUX | ACS Element 2, Accumulated Path Metric Mux 1 | RW | 0x0
2:0 | APM0MUX | ACS Element 2, Accumulated Path Metric Mux 0 | RW | 0x0

### TOP:RFC_MDM:VITBRSEL3

Address offset | 0x0000 01A0
Physical address | 0x4004 51A0 | Instance | RFC_MDM
Description | Viterbi Branch Select Register 3
Type | RW

Bits | Field Name | Description | Type | Reset
31:12 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0 0000
11:9 | BR3MUX | ACS Element 3, Branch Metric Mux 3 | RW | 0x0
8:6 | BR2MUX | ACS Element 3, Branch Metric Mux 2 | RW | 0x0
5:3 | BR1MUX | ACS Element 3, Branch Metric Mux 1 | RW | 0x0
2:0 | BR0MUX | ACS Element 3, Branch Metric Mux 0 | RW | 0x0

### TOP:RFC_MDM:VITAPMSEL3

Address offset | 0x0000 01A4
Physical address | 0x4004 51A4 | Instance | RFC_MDM
Description | Viterbi APM Select Register 3
Type | RW

Bits | Field Name | Description | Type | Reset
31:12 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0 0000
11:9 | APM3MUX | ACS Element 3, Accumulated Path Metric Mux 3 | RW | 0x0
8:6 | APM2MUX | ACS Element 3, Accumulated Path Metric Mux 2 | RW | 0x0
5:3 | APM1MUX | ACS Element 3, Accumulated Path Metric Mux 1 | RW | 0x0
2:0 | APM0MUX | ACS Element 3, Accumulated Path Metric Mux 0 | RW | 0x0

### TOP:RFC_MDM:VITBRSEL4

Address offset | 0x0000 01A8
Physical address | 0x4004 51A8 | Instance | RFC_MDM
Description | Viterbi Branch Select Register 4
Type | RW

Bits | Field Name | Description | Type | Reset
31:12 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0 0000
11:9 | BR3MUX | ACS Element 4, Branch Metric Mux 3 | RW | 0x0
8:6 | BR2MUX | ACS Element 4, Branch Metric Mux 2 | RW | 0x0
5:3 | BR1MUX | ACS Element 4, Branch Metric Mux 1 | RW | 0x0
2:0 | BR0MUX | ACS Element 4, Branch Metric Mux 0 | RW | 0x0

### TOP:RFC_MDM:VITAPMSEL4

Address offset | 0x0000 01AC
Physical address | 0x4004 51AC | Instance | RFC_MDM
Description | Viterbi APM Select Register 4
Type | RW

Bits | Field Name | Description | Type | Reset
31:12 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0 0000
11:9 | APM3MUX | ACS Element 4, Accumulated Path Metric Mux 3 | RW | 0x0
8:6 | APM2MUX | ACS Element 4, Accumulated Path Metric Mux 2 | RW | 0x0
5:3 | APM1MUX | ACS Element 4, Accumulated Path Metric Mux 1 | RW | 0x0
2:0 | APM0MUX | ACS Element 4, Accumulated Path Metric Mux 0 | RW | 0x0

### TOP:RFC_MDM:VITBRSEL5

Address offset | 0x0000 01B0
Physical address | 0x4004 51B0 | Instance | RFC_MDM
Description | Viterbi Branch Select Register 5
Type | RW

Bits | Field Name | Description | Type | Reset
31:12 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0 0000
11:9 | BR3MUX | ACS Element 5, Branch Metric Mux 3 | RW | 0x0
8:6 | BR2MUX | ACS Element 5, Branch Metric Mux 2 | RW | 0x0
5:3 | BR1MUX | ACS Element 5, Branch Metric Mux 1 | RW | 0x0
2:0 | BR0MUX | ACS Element 5, Branch Metric Mux 0 | RW | 0x0

### TOP:RFC_MDM:VITAPMSEL5

Address offset | 0x0000 01B4
Physical address | 0x4004 51B4 | Instance | RFC_MDM
Description | Viterbi APM Select Register 5
Type | RW

Bits | Field Name | Description | Type | Reset
31:12 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0 0000
11:9 | APM3MUX | ACS Element 5, Accumulated Path Metric Mux 3 | RW | 0x0
8:6 | APM2MUX | ACS Element 5, Accumulated Path Metric Mux 2 | RW | 0x0
5:3 | APM1MUX | ACS Element 5, Accumulated Path Metric Mux 1 | RW | 0x0
2:0 | APM0MUX | ACS Element 5, Accumulated Path Metric Mux 0 | RW | 0x0

### TOP:RFC_MDM:VITBRSEL6

Address offset | 0x0000 01B8
Physical address | 0x4004 51B8 | Instance | RFC_MDM
Description | Viterbi Branch Select Register 6
Type | RW

Bits | Field Name | Description | Type | Reset
31:12 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0 0000
11:9 | BR3MUX | ACS Element 6, Branch Metric Mux 3 | RW | 0x0
8:6 | BR2MUX | ACS Element 6, Branch Metric Mux 2 | RW | 0x0
5:3 | BR1MUX | ACS Element 6, Branch Metric Mux 1 | RW | 0x0
2:0 | BR0MUX | ACS Element 6, Branch Metric Mux 0 | RW | 0x0

### TOP:RFC_MDM:VITAPMSEL6

Address offset | 0x0000 01BC
Physical address | 0x4004 51BC | Instance | RFC_MDM
Description | Viterbi APM Select Register 6
Type | RW

Bits | Field Name | Description | Type | Reset
31:12 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0 0000
11:9 | APM3MUX | ACS Element 6, Accumulated Path Metric Mux 3 | RW | 0x0
8:6 | APM2MUX | ACS Element 6, Accumulated Path Metric Mux 2 | RW | 0x0
5:3 | APM1MUX | ACS Element 6, Accumulated Path Metric Mux 1 | RW | 0x0
2:0 | APM0MUX | ACS Element 6, Accumulated Path Metric Mux 0 | RW | 0x0

### TOP:RFC_MDM:VITBRSEL7

Address offset | 0x0000 01C0
Physical address | 0x4004 51C0 | Instance | RFC_MDM
Description | Viterbi Branch Select Register 7
Type | RW

Bits | Field Name | Description | Type | Reset
31:12 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0 0000
11:9 | BR3MUX | ACS Element 7, Branch Metric Mux 3 | RW | 0x0
8:6 | BR2MUX | ACS Element 7, Branch Metric Mux 2 | RW | 0x0
5:3 | BR1MUX | ACS Element 7, Branch Metric Mux 1 | RW | 0x0
2:0 | BR0MUX | ACS Element 7, Branch Metric Mux 0 | RW | 0x0

### TOP:RFC_MDM:VITAPMSEL7

Address offset | 0x0000 01C4
Physical address | 0x4004 51C4 | Instance | RFC_MDM
Description | Viterbi APM Select Register 7
Type | RW

Bits | Field Name | Description | Type | Reset
31:12 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0 0000
11:9 | APM3MUX | ACS Element 7, Accumulated Path Metric Mux 3 | RW | 0x0
8:6 | APM2MUX | ACS Element 7, Accumulated Path Metric Mux 2 | RW | 0x0
5:3 | APM1MUX | ACS Element 7, Accumulated Path Metric Mux 1 | RW | 0x0
2:0 | APM0MUX | ACS Element 7, Accumulated Path Metric Mux 0 | RW | 0x0

### TOP:RFC_MDM:LOCMULTA

Address offset | 0x0000 01C8
Physical address | 0x4004 51C8 | Instance | RFC_MDM
Description | Local Serial Multiplier Factor A Input Register
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0000
15:0 | AVALUE | 16-bit A factor | RW | 0x0000

### TOP:RFC_MDM:LOCMULTB

Address offset | 0x0000 01CC
Physical address | 0x4004 51CC | Instance | RFC_MDM
Description | Local Serial Multiplier Factor B Input Register
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0000
15:0 | BVALUE | 16-bit B factor | RW | 0x0000

### TOP:RFC_MDM:LOCMULTC0

Address offset | 0x0000 01D0
Physical address | 0x4004 51D0 | Instance | RFC_MDM
Description | Local Serial Multiplier Product Output Register
Type | RO

Bits | Field Name | Description | Type | Reset
31:16 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0000
15:0 | C15C0 | C = B*A, where this register holds bits [15:0] of C. | RO | 0x0000

### TOP:RFC_MDM:LOCMULTC1

Address offset | 0x0000 01D4
Physical address | 0x4004 51D4 | Instance | RFC_MDM
Description | Local Serial Multiplier Product Output Register
Type | RO

Bits | Field Name | Description | Type | Reset
31:16 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0000
15:0 | C31C16 | C = B*A, where this register holds bits [31:16] of C. | RO | 0x0000

### TOP:RFC_MDM:TIMCTRL

Address offset | 0x0000 01D8
Physical address | 0x4004 51D8 | Instance | RFC_MDM
Description | Modem Timer and Counter Control Register
Type | RW

Bits | Field Name | Description | Type | Reset
31:14 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0 0000
13:8 | CAPTURESOURCE | Selects bit number from event bus for a counter capture. Event number in range 0 to 63. | RW | 0x00
7 | ENABLECAPTURE | Enable counter capture on event. Upon a capture event, the counter value will be captured in TIMCAPT register.
Value | ENUM name | Description
0 | DIS | Disable capture mode for counter
1 | EN | Enable capture mode for counter
| RW | 0
6:5 | COUNTERSOURCE | Select event source for counter
Value | ENUM name | Description
0x0 | CLK | Use clock
0x1 | CLKBAUD | Use baud event
0x2 | CLK4BAUD | Use 4xBaud event
0x3 | CLK4BAUDF | Use 4xBaud flushed event
| RW | 0x0
4 | CLEARCOUNTER | Clear counter value in TIMCOUNTER to zero when this bit is set to 1. | RW | 0
3 | ENABLECOUNTER | Enable 16-bit counter when set to 1. The counter will continue from its current value. | RW | 0
2:1 | TIMERSOURCE | Select timer tick source for timer
Value | ENUM name | Description
0x0 | CLK | Clock
0x1 | CLKBAUD | Baud
0x2 | CLK4BAUD | 4xBaud
0x3 | CLK4BAUDF | 4xBaud flushed
| RW | 0x0
0 | ENABLETIMER | Enable 16-bit timer. It will generate a timer interrupt after TIMPERIOD timer ticks. Note that the internal timer value is not readable from the MCE. If this is needed the counter should be used instead of the timer.
Value | ENUM name | Description
0 | DIS | Will disable timer and clear internal timer value
1 | EN | Will enable timer
| RW | 0

### TOP:RFC_MDM:TIMINC

Address offset | 0x0000 01DC
Physical address | 0x4004 51DC | Instance | RFC_MDM
Description | Modem Counter Increment Configuration
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0000
15:0 | INCUNIT | Programmable counter increment. For each counter event: TIMCOUNTER = TIMCOUNTER + (TIMINC.INCUNIT + 1). | RW | 0x0000

### TOP:RFC_MDM:TIMPERIOD

Address offset | 0x0000 01E0
Physical address | 0x4004 51E0 | Instance | RFC_MDM
Description | Modem Timer/Counter Period Configuration
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0000
15:0 | PERIOD | Configurable 16 bit period that can be used for either the timer or the counter. In timer context, when timer value reach the timer period (i.e. it expires) a TIMER_IRQ event will occur, and the timer will restart from zero (until the timer is manually disabled). In counter context, a COUNTER_IRQ event will occur when the counter is equal to or higher than the period value. | RW | 0x0000

### TOP:RFC_MDM:TIMCOUNTER

Address offset | 0x0000 01E4
Physical address | 0x4004 51E4 | Instance | RFC_MDM
Description | Modem Counter Value
Type | RO

Bits | Field Name | Description | Type | Reset
31:16 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0000
15:0 | VALUE | 16 bit counter value that can be read by the MCE. | RO | 0x0000

### TOP:RFC_MDM:TIMCAPT

Address offset | 0x0000 01E8
Physical address | 0x4004 51E8 | Instance | RFC_MDM
Description | Modem Counter Capture Value
Type | RO

Bits | Field Name | Description | Type | Reset
31:16 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0000
15:0 | VALUE | Captured value of counter | RO | 0x0000

### TOP:RFC_MDM:TIMEBASE

Address offset | 0x0000 01EC
Physical address | 0x4004 51EC | Instance | RFC_MDM
Description | Modem Timebase Control Register
Type | RW

Bits | Field Name | Description | Type | Reset
31:1 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0000 0000
0 | FLUSH | Starts a flushing process | RW | 0

### TOP:RFC_MDM:COUNT1IN

Address offset | 0x0000 01F0
Physical address | 0x4004 51F0 | Instance | RFC_MDM
Description | Local Count Ones Input Register
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0000
15:0 | VAL | Input data, which we shall find the number of 1's in | RW | 0x0000

### TOP:RFC_MDM:COUNT1RES

Address offset | 0x0000 01F4
Physical address | 0x4004 51F4 | Instance | RFC_MDM
Description | Local Count Ones Result Register
Type | RO

Bits | Field Name | Description | Type | Reset
31:5 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x000 0000
4:0 | COUNT | Number of 1's in the COUNT1IN register | RO | 0x00

### TOP:RFC_MDM:BRMACC0

Address offset | 0x0000 01F8
Physical address | 0x4004 51F8 | Instance | RFC_MDM
Description | Local Branch Metric Accelerator Register 0
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0000
15:8 | SYM1ST | Symbol 1st (first, left one). Soft input symbol for calculating branch metrics of 1/2 rate codes. A saturated value of +/- 60 will be used in the calculations if the soft symbol exceeds this range. | RW | 0x00
7:0 | SYM2ND | Symbol 2nd (last, right one). Soft input symbol for calculating branch metrics of 1/2 rate codes. A saturated value of +/- 60 will be used in the calculations if the soft symbol exceeds this range. | RW | 0x00

### TOP:RFC_MDM:BRMACC1

Address offset | 0x0000 01FC
Physical address | 0x4004 51FC | Instance | RFC_MDM
Description | Local Branch Metric Accelerator Module Register 1
Type | RO

Bits | Field Name | Description | Type | Reset
31:16 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0000
15:8 | METRIC01 | Metric to 01 (-1 +1) symbol. Immediately calculated when BRMACC0 register is written. | RO | 0x00
7:0 | METRIC00 | Metric to 00 (-1 -1) symbol. Immediately calculated when BRMACC0 register is written. | RO | 0x00

### TOP:RFC_MDM:BRMACC2

Address offset | 0x0000 0200
Physical address | 0x4004 5200 | Instance | RFC_MDM
Description | Local Branch Metric Accelerator Module Register 2
Type | RO

Bits | Field Name | Description | Type | Reset
31:16 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0000
15:8 | METRIC11 | Metric to 11 (+1 +1) symbol. Immediately calculated when BRMACC0 register is written. | RO | 0x00
7:0 | METRIC10 | Metric to 10 (+1 -1) symbol. Immediately calculated when BRMACC0 register is written. | RO | 0x00

### TOP:RFC_MDM:VITACCCTRL

Address offset | 0x0000 0204
Physical address | 0x4004 5204 | Instance | RFC_MDM
Description | Viterbi Accelerator Control Register
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0000
15:9 | POLYNOM1 | Code generator polynomial 1. The order of the polynomial should match the CODELENGTH setting. | RW | 0x00
8:2 | POLYNOM0 | Code generator polynomial 0. The order of the polynomial should match the CODELENGTH setting. | RW | 0x00
1:0 | CODELENGTH | Code length K
Value | ENUM name | Description
0x0 | K5 | Code length K=5 (16 states)
0x1 | K6 | Code length K=6 (32 states)
0x2 | K7 | Code length K=7 (64 states)
| RW | 0x0

### TOP:RFC_MDM:VITACCRDBIT

Address offset | 0x0000 0208
Physical address | 0x4004 5208 | Instance | RFC_MDM
Description | Viterbi Accelerator Read Register
Type | RO

Bits | Field Name | Description | Type | Reset
31:1 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0000 0000
0 | RXBIT | Decoded bit | RO | 0

### TOP:RFC_MDM:MCETRCSEND

Address offset | 0x0000 020C
Physical address | 0x4004 520C | Instance | RFC_MDM
Description | MCE Tracer Send Trigger Register
Type | RW

Bits | Field Name | Description | Type | Reset
31:1 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0000 0000
0 | SEND | Sends a command to the tracer | RW | 0

### TOP:RFC_MDM:MCETRCBUSY

Address offset | 0x0000 0210
Physical address | 0x4004 5210 | Instance | RFC_MDM
Description | MCE Tracer Status Register
Type | RO

Bits | Field Name | Description | Type | Reset
31:1 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0000 0000
0 | BUSY | Checks if the tracer is busy | RO | 0

### TOP:RFC_MDM:MCETRCCMD

Address offset | 0x0000 0214
Physical address | 0x4004 5214 | Instance | RFC_MDM
Description | MCE Tracer Command Register
Type | RW

Bits | Field Name | Description | Type | Reset
31:10 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x00 0000
9:8 | PARCNT | Number of parameters | RW | 0x0
7:0 | PKTHDR | Packet header | RW | 0x00

### TOP:RFC_MDM:MCETRCPAR0

Address offset | 0x0000 0218
Physical address | 0x4004 5218 | Instance | RFC_MDM
Description | MCE Tracer Command Parameter Register 0
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0000
15:0 | PAR0 | Parameter 0 | RW | 0x0000

### TOP:RFC_MDM:MCETRCPAR1

Address offset | 0x0000 021C
Physical address | 0x4004 521C | Instance | RFC_MDM
Description | MCE Tracer Command Parameter Register 1
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0000
15:0 | PAR1 | Parameter 1 | RW | 0x0000

### TOP:RFC_MDM:RDCAPT0

Address offset | 0x0000 0220
Physical address | 0x4004 5220 | Instance | RFC_MDM
Description | Modem Readback Capture Register
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0000
15 | DEMDSBU1 | Capture read value into DEMDSBU1 RC register | RW | 0
14 | DEMC1BEX | Capture read values into DEMC1BE3, DEMC1BE4, DEMC1BE5, DEMC1BE6, DEMC1BE7, DEMC1BE8, DEMC1BE9, and DEMC1BEA RC registers | RW | 0
13 | DEMSOFD0 | Capture read value into DEMSOFD0 RC register | RW | 0
12 | DEMLQIE0 | Capture read value into DEMLQIE0 RC register | RW | 0
11 | DEMSTIM1 | Capture read value into DEMSTIM1 RC register | RW | 0
10 | DEMSTIM0 | Capture read value into DEMSTIM0 RC register | RW | 0
9 | DEMFIFE2 | Capture read value into DEMFIFE2 RC register | RW | 0
8 | DEMPDIF0 | Capture read value into DEMPDIF0 RC register | RW | 0
7 | DEMCA2P0 | Capture read value into DEMCA2P0 RC register | RW | 0
6 | DEMFIDC4 | Capture read value into DEMFIDC4 RC register | RW | 0
5 | DEMFIDC3 | Capture read value into DEMFIDC3 RC register | RW | 0
4 | DEMMGEX2 | Capture read value into DEMMGEX2 RC register | RW | 0
3 | DEMMGEX1 | Capture read value into DEMMGEX1 RC register | RW | 0
2 | DEMDSBU0 | Capture read value into DEMDSBU0 RC register | RW | 0
1 | DEMCODC4 | Capture read value into DEMCODC4 RC register | RW | 0
0 | DEMCODC3 | Capture read value into DEMCODC3 RC register | RW | 0

### TOP:RFC_MDM:DEMCODC3

Address offset | 0x0000 0224
Physical address | 0x4004 5224 | Instance | RFC_MDM
Description | Demodulator Coarse DC Estimator Register 3
Type | RO

Bits | Field Name | Description | Type | Reset
31:13 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0 0000
12:0 | ESTOUTI | Readback value, I channel | RO | 0x0000

### TOP:RFC_MDM:DEMCODC4

Address offset | 0x0000 0228
Physical address | 0x4004 5228 | Instance | RFC_MDM
Description | Demodulator Coarse DC Estimator Register 4
Type | RO

Bits | Field Name | Description | Type | Reset
31:13 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0 0000
12:0 | ESTOUTQ | Readback value, Q channel | RO | 0x0000

### TOP:RFC_MDM:DEMMGEX1

Address offset | 0x0000 022C
Physical address | 0x4004 522C | Instance | RFC_MDM
Description | Demodulator Magnitude Estimator #1
Type | RO

Bits | Field Name | Description | Type | Reset
31:13 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0 0000
12:0 | MGE1ESTOUT | Magnitude estimate from estimator 1 | RO | 0x0000

### TOP:RFC_MDM:DEMMGEX2

Address offset | 0x0000 0230
Physical address | 0x4004 5230 | Instance | RFC_MDM
Description | Demodulator Magnitude Estimator #2
Type | RO

Bits | Field Name | Description | Type | Reset
31:13 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0 0000
12:0 | MGE2ESTOUT | Magnitude estimate from estimator 2 | RO | 0x0000

### TOP:RFC_MDM:DEMFIDC3

Address offset | 0x0000 0234
Physical address | 0x4004 5234 | Instance | RFC_MDM
Description | Demodulator Fine DC Estimator Register 3
Type | RO

Bits | Field Name | Description | Type | Reset
31:13 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0 0000
12:0 | ESTOUTI | Fine DC estimate I channel | RO | 0x0000

### TOP:RFC_MDM:DEMFIDC4

Address offset | 0x0000 0238
Physical address | 0x4004 5238 | Instance | RFC_MDM
Description | Demodulator Fine DC Estimator Register 4
Type | RO

Bits | Field Name | Description | Type | Reset
31:13 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0 0000
12:0 | ESTOUTQ | Fine DC estimate Q channel | RO | 0x0000

### TOP:RFC_MDM:DEMCA2P0

Address offset | 0x0000 023C
Physical address | 0x4004 523C | Instance | RFC_MDM
Description | Demodulator Cartesian To Polar Register 0
Type | RO

Bits | Field Name | Description | Type | Reset
31:9 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x00 0000
8:0 | PHASE | Phase of current sample | RO | 0x000

### TOP:RFC_MDM:DEMPDIF0

Address offset | 0x0000 0240
Physical address | 0x4004 5240 | Instance | RFC_MDM
Description | Demodulator Phase Differentiator Register 0
Type | RO

Bits | Field Name | Description | Type | Reset
31:8 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x00 0000
7:0 | PDIFF | Instfreq of current samples | RO | 0x00

### TOP:RFC_MDM:DEMC1BE3

Address offset | 0x0000 0244
Physical address | 0x4004 5244 | Instance | RFC_MDM
Description | Demodulator Correlator 1-bit Engine Register 3
Type | RO

Bits | Field Name | Description | Type | Reset
31:16 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0000
15:0 | CORRVALUEA | Correlation calue correlator A | RO | 0x0000

### TOP:RFC_MDM:DEMC1BE4

Address offset | 0x0000 0248
Physical address | 0x4004 5248 | Instance | RFC_MDM
Description | Demodulator Correlator 1-bit Engine Register 4
Type | RO

Bits | Field Name | Description | Type | Reset
31:16 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0000
15:0 | CORRVALUEB | Correlation value correlator B | RO | 0x0000

### TOP:RFC_MDM:DEMC1BE5

Address offset | 0x0000 024C
Physical address | 0x4004 524C | Instance | RFC_MDM
Description | Demodulator Correlator 1-bit Engine Register 5
Type | RO

Bits | Field Name | Description | Type | Reset
31:16 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0000
15:0 | CORRVALUEC | Correlation value combined correlator (corr C is corr A+B combined) | RO | 0x0000

### TOP:RFC_MDM:DEMFIFE2

Address offset | 0x0000 0250
Physical address | 0x4004 5250 | Instance | RFC_MDM
Description | Demodulator Fine Frequency Offset Estimator Register 2
Type | RO

Bits | Field Name | Description | Type | Reset
31:8 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x00 0000
7:0 | FINEFOCEST | Frequency offset estimate fine foc | RO | 0x00

### TOP:RFC_MDM:DEMDSBU0

Address offset | 0x0000 0254
Physical address | 0x4004 5254 | Instance | RFC_MDM
Description | Demodulator Dynamic Sample Buffer Register 0
Type | RO

Bits | Field Name | Description | Type | Reset
31:16 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0000
15:8 | WRPOUT | Current write pointer of DSBU | RO | 0x00
7:0 | RDPOUT | Current read pointer of DSBU | RO | 0x00

### TOP:RFC_MDM:DEMDSBU1

Address offset | 0x0000 0258
Physical address | 0x4004 5258 | Instance | RFC_MDM
Description | Demodulator Dynamic Sample Buffer Register 1
Type | RO

Bits | Field Name | Description | Type | Reset
31:16 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0000
15:0 | AVGVAL | Current sum of samples between write and read pointers | RO | 0x0000

### TOP:RFC_MDM:DEMSTIM0

Address offset | 0x0000 025C
Physical address | 0x4004 525C | Instance | RFC_MDM
Description | Demodulator Symbol Timing Register 0
Type | RO

Bits | Field Name | Description | Type | Reset
31:6 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x000 0000
5:0 | EVENTS | Number of stall/advance events occured | RO | 0x00

### TOP:RFC_MDM:DEMSTIM1

Address offset | 0x0000 0260
Physical address | 0x4004 5260 | Instance | RFC_MDM
Description | Demodulator Symbol Timing Register 1
Type | RO

Bits | Field Name | Description | Type | Reset
31:14 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0 0000
13:4 | GARDNERERROR | Timing error | RO | 0x000
3:0 | DELTA | Current fractional delay | RO | 0x0

### TOP:RFC_MDM:DEMSWQU1

Address offset | 0x0000 0264
Physical address | 0x4004 5264 | Instance | RFC_MDM
Description | Demodulator Sync Word Qualifier Register 1
Type | RO

Bits | Field Name | Description | Type | Reset
31:10 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x00 0000
9:2 | MAFCCOMPVAL | Frequency Offset value computed by SWQU | RO | 0x00
1 | SWSEL | Shows which sync word had a peak event and was selected for sync word qualification test. This is to tell which sync word was detected when radio operates in receive mode with dual sync word search.
Value | ENUM name | Description
0 | A | The C1BE emitted a correlator A peak event and SWQU selected sync word A for qualification test (or no SWQU sync word test has been performed yet)
1 | B | The C1BE emitted a correlator B peak event and SWQU selected sync word B for qualification test
| RO | 0
0 | SYNCED | Reads as '1' when the sync word specified by SWSEL has passed qualification, otherwise '0'. Note that the sync word qualification is only performed on MSB portion of the reference vector, as specified in DEMSWQU0.REFLEN register. | RO | 0

### TOP:RFC_MDM:DEMLQIE0

Address offset | 0x0000 0268
Physical address | 0x4004 5268 | Instance | RFC_MDM
Description | Demodulator LQI Engine Register 0
Type | RO

Bits | Field Name | Description | Type | Reset
31:8 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x00 0000
7:0 | LQI | Link Quaility Indication value | RO | 0x00

### TOP:RFC_MDM:DEMSOFD0

Address offset | 0x0000 026C
Physical address | 0x4004 526C | Instance | RFC_MDM
Description | Demodulator Soft Decision Register 0
Type | RO

Bits | Field Name | Description | Type | Reset
31:8 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x00 0000
7:0 | SOFTSYMBOL | Soft symbol value | RO | 0x00

### TOP:RFC_MDM:RDCAPT1

Address offset | 0x0000 0270
Physical address | 0x4004 5270 | Instance | RFC_MDM
Description | Modem Readback Capture Register 2
Type | RW

Bits | Field Name | Description | Type | Reset
31:9 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x00 0000
8 | DEMPNSOFT | Capture read value into DEMPNSOFT RC register | RW | 0
7 | DEMMLSEBIT | Capture read value into DEMMLSEBIT RC register | RW | 0
6 | DEMTHRD4 | Capture read value into DEMTHRD4 RC register | RW | 0
5 | DEMBDEC0 | Capture read value into DEMBDEC0 RC register | RW | 0
4 | DEMBDEC1 | Capture read value into DEMBDEC1 RC register | RW | 0
3 | DEMCHFI0 | Capture read value into DEMCHFI0 RC register | RW | 0
2 | DEMCHFI1 | Capture read value into DEMCHFI1 RC register | RW | 0
1 | DEMFRAC4 | Capture read value into DEMFRAC4 RC register | RW | 0
0 | DEMFRAC5 | Capture read value into DEMFRAC5 RC register | RW | 0

### TOP:RFC_MDM:DEMTHRD4

Address offset | 0x0000 0274
Physical address | 0x4004 5274 | Instance | RFC_MDM
Description | Demodulator Soft Decision Threshold Register 4
Type | RO

Bits | Field Name | Description | Type | Reset
31:4 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x000 0000
3:0 | DECISION | Multilevel decision | RO | 0x0

### TOP:RFC_MDM:DEMMLSEBIT

Address offset | 0x0000 0278
Physical address | 0x4004 5278 | Instance | RFC_MDM
Description | Demodulator Maximum Likelihood Sequence Estimation Register
Type | RO

Bits | Field Name | Description | Type | Reset
31:1 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0000 0000
0 | MLSEBIT | MLSE decoded output bit | RO | 0

### TOP:RFC_MDM:DEMBDEC0

Address offset | 0x0000 027C
Physical address | 0x4004 527C | Instance | RFC_MDM
Description | I signal after the BDEC module
Type | RO

Bits | Field Name | Description | Type | Reset
31:13 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0 0000
12:0 | IVAL | 13-bit I value | RO | 0x0000

### TOP:RFC_MDM:DEMBDEC1

Address offset | 0x0000 0280
Physical address | 0x4004 5280 | Instance | RFC_MDM
Description | Q signal after the BDEC module
Type | RO

Bits | Field Name | Description | Type | Reset
31:13 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0 0000
12:0 | QVAL | 13-bit Q value | RO | 0x0000

### TOP:RFC_MDM:DEMCHFI0

Address offset | 0x0000 0284
Physical address | 0x4004 5284 | Instance | RFC_MDM
Description | I signal after the CHFI module
Type | RO

Bits | Field Name | Description | Type | Reset
31:13 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0 0000
12:0 | IVAL | 13-bit I value | RO | 0x0000

### TOP:RFC_MDM:DEMCHFI1

Address offset | 0x0000 0288
Physical address | 0x4004 5288 | Instance | RFC_MDM
Description | Q signal after the CHFI module
Type | RO

Bits | Field Name | Description | Type | Reset
31:13 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0 0000
12:0 | QVAL | 13-bit Q value | RO | 0x0000

### TOP:RFC_MDM:DEMFRAC4

Address offset | 0x0000 028C
Physical address | 0x4004 528C | Instance | RFC_MDM
Description | I signal after the FRAC module
Type | RO

Bits | Field Name | Description | Type | Reset
31:13 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0 0000
12:0 | IVAL | 13-bit I value | RO | 0x0000

### TOP:RFC_MDM:DEMFRAC5

Address offset | 0x0000 0290
Physical address | 0x4004 5290 | Instance | RFC_MDM
Description | Q signal after the FRAC module
Type | RO

Bits | Field Name | Description | Type | Reset
31:13 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0 0000
12:0 | QVAL | 13-bit Q value | RO | 0x0000

### TOP:RFC_MDM:DEMPNSOFT

Address offset | 0x0000 0294
Physical address | 0x4004 5294 | Instance | RFC_MDM
Description | Soft Correlation out of PN module
Type | RO

Bits | Field Name | Description | Type | Reset
31:8 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x00 0000
7:0 | PNSOFT | 8-bit signed value | RO | 0x00

### TOP:RFC_MDM:DEMC1BE6

Address offset | 0x0000 0298
Physical address | 0x4004 5298 | Instance | RFC_MDM
Description | Demodulator Correlator 1-bit Engine Register 6
Type | RO

Bits | Field Name | Description | Type | Reset
31:8 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x00 0000
7:0 | VAL | A Correlation Peak x[n-1] Sample | RO | 0x00

### TOP:RFC_MDM:DEMC1BE7

Address offset | 0x0000 029C
Physical address | 0x4004 529C | Instance | RFC_MDM
Description | Demodulator Correlator 1-bit Engine Register 7
Type | RO

Bits | Field Name | Description | Type | Reset
31:8 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x00 0000
7:0 | VAL | A Correlation Peak x[n+1] Sample | RO | 0x00

### TOP:RFC_MDM:DEMC1BE8

Address offset | 0x0000 02A0
Physical address | 0x4004 52A0 | Instance | RFC_MDM
Description | Demodulator Correlator 1-bit Engine Register 8
Type | RO

Bits | Field Name | Description | Type | Reset
31:8 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x00 0000
7:0 | VAL | B Correlation Peak x[n-1] Sample | RO | 0x00

### TOP:RFC_MDM:DEMC1BE9

Address offset | 0x0000 02A4
Physical address | 0x4004 52A4 | Instance | RFC_MDM
Description | Demodulator Correlator 1-bit Engine Register 9
Type | RO

Bits | Field Name | Description | Type | Reset
31:8 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x00 0000
7:0 | VAL | B Correlation Peak x[n+1] Sample | RO | 0x00

### TOP:RFC_MDM:DEMC1BEA

Address offset | 0x0000 02A8
Physical address | 0x4004 52A8 | Instance | RFC_MDM
Description | Demodulator Correlator 1-bit Engine Register A
Type | RO

Bits | Field Name | Description | Type | Reset
31:12 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0 0000
11:6 | QUALB | Parallel Bit Qualifier for Correlator B | RO | 0x00
5:0 | QUALA | Parallel Bit Qualifier for Correlator A | RO | 0x00

### TOP:RFC_MDM:MDMSPAR0

Address offset | 0x0000 02AC
Physical address | 0x4004 52AC | Instance | RFC_MDM
Description | Modem Spare 0
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0000
15:0 | VAL | Spare register for use by firmware | RW | 0x0000

### TOP:RFC_MDM:MDMSPAR1

Address offset | 0x0000 02B0
Physical address | 0x4004 52B0 | Instance | RFC_MDM
Description | Modem Spare 1
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0000
15:0 | VAL | Spare register for use by firmware | RW | 0x0000

### TOP:RFC_MDM:MDMSPAR2

Address offset | 0x0000 02B4
Physical address | 0x4004 52B4 | Instance | RFC_MDM
Description | Modem Spare 2
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0000
15:0 | VAL | Spare register for use by firmware | RW | 0x0000

### TOP:RFC_MDM:MDMSPAR3

Address offset | 0x0000 02B8
Physical address | 0x4004 52B8 | Instance | RFC_MDM
Description | Modem Spare 3
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0000
15:0 | VAL | Spare register for use by firmware | RW | 0x0000

### TOP:RFC_MDM:DEMSOFD1

Address offset | 0x0000 02BC
Physical address | 0x4004 52BC | Instance | RFC_MDM
Description | Soft Decision 4x Samples
Type | RO

Bits | Field Name | Description | Type | Reset
31:8 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x00 0000
7:0 | SOFTX0 | Soft x[0] (newest sample) | RO | 0x00

### TOP:RFC_MDM:DEMSOFD2

Address offset | 0x0000 02C0
Physical address | 0x4004 52C0 | Instance | RFC_MDM
Description | Soft Decision 4x Samples
Type | RO

Bits | Field Name | Description | Type | Reset
31:8 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x00 0000
7:0 | SOFTX1 | Soft x[1] (center left sample) | RO | 0x00

### TOP:RFC_MDM:DEMSOFD3

Address offset | 0x0000 02C4
Physical address | 0x4004 52C4 | Instance | RFC_MDM
Description | Soft Decision 4x Samples
Type | RO

Bits | Field Name | Description | Type | Reset
31:8 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x00 0000
7:0 | SOFTX2 | Soft x[2] (center right sample) | RO | 0x00

### TOP:RFC_MDM:DEMSOFD4

Address offset | 0x0000 02C8
Physical address | 0x4004 52C8 | Instance | RFC_MDM
Description | Soft Decision 4x Samples
Type | RO

Bits | Field Name | Description | Type | Reset
31:8 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x00 0000
7:0 | SOFTX3 | Soft x[3] (oldest sample) | RO | 0x00