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setup.c
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1 /******************************************************************************
2 * Filename: setup.c
3 * Revised: 2015-01-16 10:44:49 +0100 (fr, 16 jan 2015)
4 * Revision: 42411
5 *
6 * Description: Setup file for CC26xx PG2 device family.
7 *
8 * Copyright (c) 2015, Texas Instruments Incorporated
9 * All rights reserved.
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions are met:
13 *
14 * 1) Redistributions of source code must retain the above copyright notice,
15 * this list of conditions and the following disclaimer.
16 *
17 * 2) Redistributions in binary form must reproduce the above copyright notice,
18 * this list of conditions and the following disclaimer in the documentation
19 * and/or other materials provided with the distribution.
20 *
21 * 3) Neither the name of the ORGANIZATION nor the names of its contributors may
22 * be used to endorse or promote products derived from this software without
23 * specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
26 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
28 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
29 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
35 * POSSIBILITY OF SUCH DAMAGE.
36 *
37 ******************************************************************************/
38
39 // Hardware headers
40 #include <inc/hw_memmap.h>
41 #include <inc/hw_types.h>
42 #include <inc/hw_adi.h>
43 #include <inc/hw_adi_0_rf.h>
44 #include <inc/hw_adi_1_synth.h>
45 #include <inc/hw_adi_2_refsys.h>
46 #include <inc/hw_adi_3_refsys.h>
47 #include <inc/hw_adi_4_aux.h>
48 #include <inc/hw_aon_ioc.h>
49 #include <inc/hw_aon_sysctl.h>
50 #include <inc/hw_aon_wuc.h>
51 #include <inc/hw_aux_wuc.h>
52 #include <inc/hw_ccfg.h>
53 #include <inc/hw_chip_def.h>
54 #include <inc/hw_ddi.h>
55 #if ( CC_GET_CHIP_OPTION == CC_CHIP_OPTION_OTP )
56 #else
57 #include <inc/hw_flash.h>
58 #endif
59 #include <inc/hw_fcfg1.h>
60 #include <inc/hw_ddi_0_osc.h>
61 #include <inc/hw_prcm.h>
62 #include <inc/hw_vims.h>
63 #include <inc/hw_aon_batmon.h>
64 #include <inc/hw_aon_rtc.h>
65 // Driverlib headers
66 #include <driverlib/adi.h>
67 #include <driverlib/cpu.h>
68 #include <driverlib/chipinfo.h>
69 #include <driverlib/ddi.h>
70 #include <driverlib/prcm.h>
71 #include <driverlib/sys_ctrl.h>
72 #include <driverlib/aon_batmon.h>
73
74 // We need intrinsic functions for IAR (if used in source code)
75 #ifdef __IAR_SYSTEMS_ICC__
76 #include <intrinsics.h>
77 #endif
78
79 // Due to a misunderstanding when probing the first wafer this VDDR trim
80 // was not written to the EFUSE registers (only in the EFUSE shadow in FCFG1)
81 // The VDDR trim is therefore not done by the boot code and must be done here.
82 // This code can be removed when chips from the first wafer is no longer supported.
83 #define INCLUDE_VDDR_TEMPORARILY 1
84
85 // Bit defines for CUSTOMER_CFG_O_MODE_CONF:SCLK_LF_OPTION
86 #define CLK_LF_RCOSC_LF 0xC00000
87 #define CLK_LF_XOSC_LF 0x800000
88 #define CLK_LF_XOSC_HF 0x000000
89
90 //*****************************************************************************
91 //
92 // Function declarations
93 //
94 //*****************************************************************************
95 void trimDevice( void );
96 static uint32_t GetTrimForAdcShModeEn( uint32_t ui32Fcfg1Revision );
97 static uint32_t GetTrimForAdcShVbufEn( uint32_t ui32Fcfg1Revision );
98 static uint32_t GetTrimForAmpcompCtrl( uint32_t ui32Fcfg1Revision );
99 static uint32_t GetTrimForAmpcompTh1( uint32_t ui32Fcfg1Revision );
100 static uint32_t GetTrimForAmpcompTh2( uint32_t ui32Fcfg1Revision );
101 static uint32_t GetTrimForAnabypassValue1( uint32_t ui32Fcfg1Revision, uint32_t ccfg_ModeConfReg );
102 static uint32_t GetTrimForDblrLoopFilterResetVoltage( uint32_t ui32Fcfg1Revision );
103 static uint32_t GetTrimForRadcExtCfg( uint32_t ui32Fcfg1Revision );
104 static uint32_t GetTrimForRcOscLfIBiasTrim( uint32_t ui32Fcfg1Revision );
105 static uint32_t GetTrimForRcOscLfRtuneCtuneTrim( uint32_t ui32Fcfg1Revision );
106 static uint32_t GetTrimForXoscHfCtl( uint32_t ui32Fcfg1Revision );
107 static uint32_t GetTrimForXoscHfFastStart( uint32_t ui32Fcfg1Revision );
108 static uint32_t GetTrimForXoscHfIbiastherm( uint32_t ui32Fcfg1Revision );
109 static uint32_t GetTrimForXoscLfRegulatorAndCmirrwrRatio( uint32_t ui32Fcfg1Revision );
110
111 #if ( INCLUDE_VDDR_TEMPORARILY )
112 static int32_t SignExtendVddrTrimValue( uint32_t ui32VddrTrimVal );
113 #endif
114 static void HapiTrimDeviceColdReset( uint32_t ui32Fcfg1Revision );
115 static void HapiTrimDeviceShutDown( uint32_t ui32Fcfg1Revision );
116 static void HapiTrimDevicePowerDown( uint32_t ui32Fcfg1Revision );
117
118
119 //*****************************************************************************
120 //
122 //
123 //*****************************************************************************
124 #define DELAY_20_USEC 0x140
125
126
127 //*****************************************************************************
128 //
129 // Defined CPU delay macro with microseconds as input
130 // Quick check shows: (Tob be further investigated)
131 // At 48 MHz RCOSC and VIMS.CONTROL.PREFETCH = 0, there is 5 cycles
132 // At 48 MHz RCOSC and VIMS.CONTROL.PREFETCH = 1, there is 4 cycles
133 // At 24 MHz RCOSC and VIMS.CONTROL.PREFETCH = 0, there is 3 cycles
134 //
135 //*****************************************************************************
136 #define CPU_DELAY_MICRO_SECONDS( x ) \
137 CPUdelay(((uint32_t)((( x ) * 48.0 ) / 5.0 )) - 1 )
138
139
140 //*****************************************************************************
141 //
147 //
148 //*****************************************************************************
149 void
150 trimDevice(void)
151 {
152 uint32_t ui32Fcfg1Revision;
153 uint32_t ui32AonSysResetctl;
154
155 //
156 // Get layout revision of the factory configuration area
157 // (Handle undefined revision as revision = 0)
158 //
159 ui32Fcfg1Revision = HWREG(FCFG1_BASE + FCFG1_O_FCFG1_REVISION);
160 if ( ui32Fcfg1Revision == 0xFFFFFFFF ) {
161 ui32Fcfg1Revision = 0;
162 }
163
164 #if defined( CHECK_AT_STARTUP_FOR_CORRECT_FAMILY_ONLY )
165 //
166 // This driverlib version and setup file is for CC26xx PG2.0 and later
167 // (Keeping this check at HwRev2.0 independent of "#else" check)
168 // Halt if violated
169 //
170 ThisCodeIsBuiltForCC26xxHwRev20AndLater_HaltIfViolated();
171 #else
172
173 //
174 // This driverlib version and setup file is for CC26xx PG2.2 and later
175 // Halt if violated
176 //
177 ThisCodeIsBuiltForCC26xxHwRev22AndLater_HaltIfViolated();
178
179 #endif
180
181 //
182 // Enable standby in flash bank
183 //
184 HWREGBITW(FLASH_BASE + FLASH_O_CFG, FLASH_CFG_DIS_STANDBY_BITN ) = 0;
185
186 //
187 // Clock must always be enabled for the semaphore module (due to ADI/DDI HW workaround)
188 //
189 HWREG( AUX_WUC_BASE + AUX_WUC_O_MODCLKEN1 ) = AUX_WUC_MODCLKEN1_SMPH;
190
191 // 1. Check for powerdown
192 // 2. Check for shutdown
193 // 3. Assume cold reset if none of the above.
194 //
195 // It is always assumed that the application will freeze the latches in
196 // AON_IOC when going to powerdown in order to retain the values on the IOs.
197 //
198 // NB. If this bit is not cleared before proceeding to powerdown, the IOs
199 // will all default to the reset configuration when restarting.
200 if(((HWREG(AON_IOC_BASE + AON_IOC_O_IOCLATCH) &
201 AON_IOC_IOCLATCH_EN_M) == AON_IOC_IOCLATCH_EN_STATIC))
202 {
203 //
204 // NB. This should be calling a ROM implementation of required trim and
205 // compensation
206 // e.g. HapiTrimDevicePowerDown()
207 HapiTrimDevicePowerDown(ui32Fcfg1Revision);
208 }
209 // Check for shutdown
210 //
211 // When device is going to shutdown the hardware will automatically clear
212 // the SLEEPDIS bit in the SLEEP register in the AON_SYSCTRL12 module.
213 // It is left for the application to assert this bit when waking back up,
214 // but not before the desired IO configuration has been re-established.
215 else if(!(HWREG(AON_SYSCTL_BASE + AON_SYSCTL_O_SLEEPCTL) &
216 AON_SYSCTL_SLEEPCTL_IO_PAD_SLEEP_DIS))
217 {
218 //
219 // NB. This should be calling a ROM implementation of required trim and
220 // compensation
221 // e.g. HapiTrimDeviceShutDown() -->
222 // HapiTrimDevicePowerDown();
223 HapiTrimDeviceShutDown(ui32Fcfg1Revision);
224 HapiTrimDevicePowerDown(ui32Fcfg1Revision);
225 }
226 else
227 {
228 // Consider adding a check for soft reset to allow debugging to skip
229 // this section!!!
230 //
231 // NB. This should be calling a ROM implementation of required trim and
232 // compensation
233 // e.g. HapiTrimDeviceColdReset() -->
234 // HapiTrimDeviceShutDown() -->
235 // HapiTrimDevicePowerDown()
236 HapiTrimDeviceColdReset(ui32Fcfg1Revision);
237 HapiTrimDeviceShutDown(ui32Fcfg1Revision);
238 HapiTrimDevicePowerDown(ui32Fcfg1Revision);
239
240 }
241
242 //
243 // Make sure to enable agressive VIMS clock gating for power optimization
244 // Only for PG2 devices.
245 //
246 HWREG(VIMS_BASE + VIMS_O_CTL) |= VIMS_CTL_DYN_CG_EN;
247
248 #if ( CC_GET_CHIP_OPTION != CC_CHIP_OPTION_OTP )
249 //
250 // Configure optimal wait time for flash FSM in cases where flash pump
251 // wakes up from sleep
252 //
253 HWREG(FLASH_BASE + FLASH_O_FPAC1) = (HWREG(FLASH_BASE + FLASH_O_FPAC1) &
254 ~FLASH_FPAC1_PSLEEPTDIS_M) |
255 (0x139<<FLASH_FPAC1_PSLEEPTDIS_S);
256 #endif
257
258 //
259 // And finally at the end of the flash boot process:
260 // SET BOOT_DET bits in AON_SYSCTL to 3 if already found to be 1
261 // Note: The BOOT_DET_x_CLR/SET bits must be maually cleared
262 //
263 if ((( HWREG( AON_SYSCTL_BASE + AON_SYSCTL_O_RESETCTL ) &
264 ( AON_SYSCTL_RESETCTL_BOOT_DET_1_M | AON_SYSCTL_RESETCTL_BOOT_DET_0_M )) >>
265 AON_SYSCTL_RESETCTL_BOOT_DET_0_S ) == 1 )
266 {
267 ui32AonSysResetctl = ( HWREG( AON_SYSCTL_BASE + AON_SYSCTL_O_RESETCTL ) &
268 ~( AON_SYSCTL_RESETCTL_BOOT_DET_1_CLR_M | AON_SYSCTL_RESETCTL_BOOT_DET_0_CLR_M |
269 AON_SYSCTL_RESETCTL_BOOT_DET_1_SET_M | AON_SYSCTL_RESETCTL_BOOT_DET_0_SET_M ));
270 HWREG( AON_SYSCTL_BASE + AON_SYSCTL_O_RESETCTL ) = ui32AonSysResetctl | AON_SYSCTL_RESETCTL_BOOT_DET_1_SET_M;
271 HWREG( AON_SYSCTL_BASE + AON_SYSCTL_O_RESETCTL ) = ui32AonSysResetctl;
272 }
273 }
274
275 static void
276 HapiTrimDevicePowerDown(uint32_t ui32Fcfg1Revision)
277 {
278 //
279 // Currently no specific trim for Powerdown
280 //
281 }
282
283 static void
284 HapiTrimDeviceShutDown(uint32_t ui32Fcfg1Revision)
285 {
286 uint32_t ui32Trim ;
287 uint32_t ccfg_ModeConfReg ;
288 uint32_t sclk_lf ;
289
290 //
291 // Force AUX on and enable clocks
292 //
293 // No need to save the current status of the power/clock registers.
294 // At this point both AUX and AON should have been reset to 0x0.
295 //
296 HWREG(AON_WUC_BASE + AON_WUC_O_AUXCTL) = AON_WUC_AUXCTL_AUX_FORCE_ON;
297
298 //
299 // Wait for power on on the AUX domain
300 //
301 while(!(HWREG(AON_WUC_BASE + AON_WUC_O_PWRSTAT) & AON_WUC_PWRSTAT_AUX_PD_ON))
302 { }
303
304 //
305 // Enable the clock
306 //
307 HWREG(AUX_WUC_BASE + AUX_WUC_O_MODCLKEN0) = AUX_WUC_MODCLKEN0_AUX_DDI0_OSC |
308 AUX_WUC_MODCLKEN0_AUX_ADI4;
309
310 //
311 // read the MODE_CONF register in CCFG
312 //
313 ccfg_ModeConfReg = HWREG( CCFG_BASE + CCFG_O_MODE_CONF );
314
315 //
316 // setup the LF clock based upon CCFG:MODE_CONF:SCLK_LF_OPTION
317 //
318 sclk_lf = ccfg_ModeConfReg & CCFG_MODE_CONF_SCLK_LF_OPTION_M;
319
320 if ( sclk_lf == CLK_LF_XOSC_LF ) OSCClockSourceSet( OSC_SRC_CLK_LF, OSC_XOSC_LF );
321 else if ( sclk_lf == CLK_LF_XOSC_HF ) OSCClockSourceSet( OSC_SRC_CLK_LF, OSC_XOSC_HF );
322 else OSCClockSourceSet( OSC_SRC_CLK_LF, OSC_RCOSC_LF );
323
324 //
325 // It's found to be optimal to override the FCFG1..DCDC_IPEAK setting as follows:
326 // if ( alternative DCDC setting in CCFG is enabled ) ADI3..IPEAK = CCFG..DCDC_IPEAK
327 // else ADI3..IPEAK = 2
328 //
329 if (( HWREG( CCFG_BASE + CCFG_O_SIZE_AND_DIS_FLAGS ) & CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING ) == 0 ) {
330 //
331 // ADI_3_REFSYS:DCDCCTL5[3] (=DITHER_EN) = CCFG_MODE_CONF_1[19] (=DCDC_DITHER_EN)
332 // ADI_3_REFSYS:DCDCCTL5[2:0](=IPEAK ) = CCFG_MODE_CONF_1[18:16](=DCDC_IPEAK )
333 // Using a single 4-bit masked write since layout is equal for both source and destination
334 //
335 HWREGB( ADI3_BASE + ADI_O_MASK4B + ( ADI_3_REFSYS_O_DCDCCTL5 * 2 )) = ( 0xF0 |
336 ( HWREG( CCFG_BASE + CCFG_O_MODE_CONF_1 ) >> CCFG_MODE_CONF_1_ALT_DCDC_IPEAK_S ));
337 } else {
338 HWREGB( ADI3_BASE + ADI_O_MASK4B + ( ADI_3_REFSYS_O_DCDCCTL5 * 2 )) = 0x72;
339 }
340
341 //
342 // set the RECHARGE source based upon CCFG:MODE_CONF:DCDC_RECHARGE
343 // Note: Inverse polarity
344 //
345 HWREGBITW( AON_SYSCTL_BASE + AON_SYSCTL_O_PWRCTL, AON_SYSCTL_PWRCTL_DCDC_EN_BITN ) =
346 ((( ccfg_ModeConfReg >> CCFG_MODE_CONF_DCDC_RECHARGE_S ) & 1 ) ^ 1 );
347
348 //
349 // set the ACTIVE source based upon CCFG:MODE_CONF:DCDC_ACTIVE
350 // Note: Inverse polarity
351 //
352 HWREGBITW( AON_SYSCTL_BASE + AON_SYSCTL_O_PWRCTL, AON_SYSCTL_PWRCTL_DCDC_ACTIVE_BITN ) =
353 ((( ccfg_ModeConfReg >> CCFG_MODE_CONF_DCDC_ACTIVE_S ) & 1 ) ^ 1 );
354
355 //
356 // Following sequence is required for using XOSCHF, if not included
357 // devices crashes when trying to switch to XOSCHF.
358 //
359 // Trim CAP settings. Get and set trim value for the ANABYPASS_VALUE1
360 // register
361 ui32Trim = GetTrimForAnabypassValue1( ui32Fcfg1Revision, ccfg_ModeConfReg );
362 DDI32RegWrite(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_ANABYPASSVAL1, ui32Trim);
363
364 // Trim RCOSC_LF. Get and set trim values for the RCOSCLF_RTUNE_TRIM and
365 // RCOSCLF_CTUNE_TRIM fields in the XOSCLF_RCOSCLF_CTRL register.
366 ui32Trim = GetTrimForRcOscLfRtuneCtuneTrim(ui32Fcfg1Revision);
367 DDI16BitfieldWrite(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_LFOSCCTL,
368 (DDI_0_OSC_LFOSCCTL_RCOSCLF_CTUNE_TRIM_M |
369 DDI_0_OSC_LFOSCCTL_RCOSCLF_RTUNE_TRIM_M),
370 DDI_0_OSC_LFOSCCTL_RCOSCLF_CTUNE_TRIM_S,
371 ui32Trim);
372
373 // Trim XOSCHF IBIAS THERM. Get and set trim value for the
374 // XOSCHF IBIAS THERM bit field in the ANABYPASS_VALUE2 register. Other
375 // register bit fields are set to 0.
376 ui32Trim = GetTrimForXoscHfIbiastherm(ui32Fcfg1Revision);
377 DDI32RegWrite(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_ANABYPASSVAL2,
378 ui32Trim<<DDI_0_OSC_ANABYPASSVAL2_XOSC_HF_IBIASTHERM_S);
379
380 // Trim AMPCOMP settings required before switch to XOSCHF
381 ui32Trim = GetTrimForAmpcompTh2(ui32Fcfg1Revision);
382 DDI32RegWrite(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_AMPCOMPTH2, ui32Trim);
383 ui32Trim = GetTrimForAmpcompTh1(ui32Fcfg1Revision);
384 DDI32RegWrite(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_AMPCOMPTH1, ui32Trim);
385 ui32Trim = GetTrimForAmpcompCtrl(ui32Fcfg1Revision);
386 DDI32RegWrite(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_AMPCOMPCTL, ui32Trim);
387
388 //
389 // Set trim for DDI_0_OSC_ADCDOUBLERNANOAMPCTL_ADC_SH_MODE_EN in acordance to FCFG1 setting
390 // This is bit[5] in the DDI_0_OSC_O_ADCDOUBLERNANOAMPCTL register
391 // Using MASK4 write + 1 => writing to bits[7:4]
392 //
393 ui32Trim = GetTrimForAdcShModeEn( ui32Fcfg1Revision );
394 HWREGB( AUX_DDI0_OSC_BASE + DDI_O_MASK4B + ( DDI_0_OSC_O_ADCDOUBLERNANOAMPCTL * 2 ) + 1 ) =
395 ( 0x20 | ( ui32Trim << 1 ));
396
397 //
398 // Set trim for DDI_0_OSC_ADCDOUBLERNANOAMPCTL_ADC_SH_VBUF_EN in acordance to FCFG1 setting
399 // This is bit[4] in the DDI_0_OSC_O_ADCDOUBLERNANOAMPCTL register
400 // Using MASK4 write + 1 => writing to bits[7:4]
401 //
402 ui32Trim = GetTrimForAdcShVbufEn( ui32Fcfg1Revision );
403 HWREGB( AUX_DDI0_OSC_BASE + DDI_O_MASK4B + ( DDI_0_OSC_O_ADCDOUBLERNANOAMPCTL * 2 ) + 1 ) =
404 ( 0x10 | ( ui32Trim ));
405
406 //
407 // Set trim for the PEAK_DET_ITRIM, HP_BUF_ITRIM and LP_BUF_ITRIM bit fields
408 // in the DDI0_OSC_O_XOSCHFCTL register in accordance to FCFG1 setting.
409 // Remaining register bit fields are set to their reset values of 0.
410 //
411 ui32Trim = GetTrimForXoscHfCtl(ui32Fcfg1Revision);
412 DDI32RegWrite(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_XOSCHFCTL, ui32Trim);
413
414 //
415 // Set trim for DBLR_LOOP_FILTER_RESET_VOLTAGE in accordance to FCFG1 setting
416 // (This is bits [18:17] in DDI_0_OSC_O_ADCDOUBLERNANOAMPCTL)
417 // (Using MASK4 write + 4 => writing to bits[19:16] => (4*4))
418 // (Assuming: DDI_0_OSC_ADCDOUBLERNANOAMPCTL_DBLR_LOOP_FILTER_RESET_VOLTAGE_S = 17 and
419 // that DDI_0_OSC_ADCDOUBLERNANOAMPCTL_DBLR_LOOP_FILTER_RESET_VOLTAGE_M = 0x00060000)
420 //
421 ui32Trim = GetTrimForDblrLoopFilterResetVoltage( ui32Fcfg1Revision );
422 HWREGB( AUX_DDI0_OSC_BASE + DDI_O_MASK4B + ( DDI_0_OSC_O_ADCDOUBLERNANOAMPCTL * 2 ) + 4 ) =
423 ( 0x60 | ( ui32Trim << 1 ));
424
425 //
426 // Update DDI_0_OSC_ATESTCTL_ATESTLF_RCOSCLF_IBIAS_TRIM with data from
427 // FCFG1_OSC_CONF_ATESTLF_RCOSCLF_IBIAS_TRIM
428 // This is DDI_0_OSC_O_ATESTCTL bit[7]
429 // ( DDI_0_OSC_O_ATESTCTL is currently hidden (but=0x00000020))
430 // Using MASK4 write + 1 => writing to bits[7:4]
431 //
432 ui32Trim = GetTrimForRcOscLfIBiasTrim( ui32Fcfg1Revision );
433 HWREGB( AUX_DDI0_OSC_BASE + DDI_O_MASK4B + ( 0x00000020 * 2 ) + 1 ) =
434 ( 0x80 | ( ui32Trim << 3 ));
435
436 //
437 // Update DDI_0_OSC_LFOSCCTL_XOSCLF_REGULATOR_TRIM and
438 // DDI_0_OSC_LFOSCCTL_XOSCLF_CMIRRWR_RATIO in one write
439 // This can be simplified since the registers are packed together in the same
440 // order both in FCFG1 and in the HW register.
441 // This spans DDI_0_OSC_O_LFOSCCTL bits[23:18]
442 // Using MASK8 write + 4 => writing to bits[23:16]
443 //
444 ui32Trim = GetTrimForXoscLfRegulatorAndCmirrwrRatio( ui32Fcfg1Revision );
445 HWREGH( AUX_DDI0_OSC_BASE + DDI_O_MASK8B + ( DDI_0_OSC_O_LFOSCCTL * 2 ) + 4 ) =
446 ( 0xFC00 | ( ui32Trim << 2 ));
447
448 //
449 // Set trim the HPM_IBIAS_WAIT_CNT, LPM_IBIAS_WAIT_CNT and IDAC_STEP bit
450 // fields in the DDI0_OSC_O_RADCEXTCFG register in accordance to FCFG1 setting.
451 // Remaining register bit fields are set to their reset values of 0.
452 //
453 ui32Trim = GetTrimForRadcExtCfg(ui32Fcfg1Revision);
454 DDI32RegWrite(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_RADCEXTCFG, ui32Trim);
455
456 // Setting FORCE_KICKSTART_EN (ref. CC26_V1_BUG00261). Should also be done for PG2
457 // (This is bit 22 in DDI_0_OSC_O_CTL0)
458 HWREGB( AUX_DDI0_OSC_BASE + DDI_O_MASK4B + ( DDI_0_OSC_O_CTL0 * 2 ) + 5 ) = 0x44;
459
460 // Set bit DDI_0_OSC_CTL0_XTAL_IS_24M (this is bit 31 in DDI_0_OSC_O_CTL0)
461 HWREGB( AUX_DDI0_OSC_BASE + DDI_O_MASK4B + ( DDI_0_OSC_O_CTL0 * 2 ) + 7 ) = 0x88;
462
463 // Setting DDI_0_OSC_CTL1_XOSC_HF_FAST_START according to value found in FCFG1
464 ui32Trim = GetTrimForXoscHfFastStart( ui32Fcfg1Revision );
465 HWREGB( AUX_DDI0_OSC_BASE + DDI_O_MASK4B + ( 0x00000004 * 2 )) = ( 0x30 | ui32Trim );
466
467 //
468 // Update ADI_4_AUX_ADCREF1_VTRIM with value from FCFG1
469 //
470 HWREGB( AUX_ADI4_BASE + ADI_4_AUX_O_ADCREF1 ) =
471 ((( HWREG( FCFG1_BASE + FCFG1_O_SOC_ADC_REF_TRIM_AND_OFFSET_EXT ) >>
472 FCFG1_SOC_ADC_REF_TRIM_AND_OFFSET_EXT_SOC_ADC_REF_VOLTAGE_TRIM_TEMP1_S ) <<
473 ADI_4_AUX_ADCREF1_VTRIM_S ) &
474 ADI_4_AUX_ADCREF1_VTRIM_M );
475
476 //
477 // Set ADI_4_AUX:ADC0.SMPL_CYCLE_EXP to it's default minimum value (=3)
478 // (Note: Using MASK8B requires that the bits to be modified must be within the same
479 // byte boundary whivh is the case for the ADI_4_AUX_ADC0_SMPL_CYCLE_EXP field)
480 //
481 HWREGH( AUX_ADI4_BASE + ADI_O_MASK8B + ( ADI_4_AUX_O_ADC0 * 2 )) =
482 ( ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_M << 8 ) | ( 3 << ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_S );
483
484 //
485 // Sync with AON
486 //
487 SysCtrlAonSync();
488
489 //
490 // Disable clock for OSC_DIG and release power on AUX
491 //
492 HWREG(AUX_WUC_BASE + AUX_WUC_O_MODCLKEN0) = 0x0;
493
494 //
495 // Release "Force AUX on"
496 //
497 // No need to save the current status of the power/clock registers.
498 // At this point both AUX and AON should have been reset to 0x0.
499 //
500 HWREG(AON_WUC_BASE + AON_WUC_O_AUXCTL) = 0;
501
502 #if ( CC_GET_CHIP_OPTION != CC_CHIP_OPTION_OTP )
503 // Disable EFUSE clock
504 HWREGBITW( FLASH_BASE + FLASH_O_CFG, FLASH_CFG_DIS_EFUSECLK_BITN ) = 1;
505 #endif
506 }
507
508 #if ( INCLUDE_VDDR_TEMPORARILY )
509 static int32_t
510 SignExtendVddrTrimValue( uint32_t ui32VddrTrimVal )
511 {
512 //
513 // The VDDR trim value is 5 bits representing the range from -10 to +21
514 // (where -10=0x16, -1=0x1F, 0=0x00, 1=0x01 and +21=0x15)
515 //
516 int32_t i32SignedVddrVal = ui32VddrTrimVal;
517 if ( i32SignedVddrVal > 0x15 ) {
518 i32SignedVddrVal -= 0x20;
519 }
520 return ( i32SignedVddrVal );
521 }
522 #endif
523
524 static void
525 HapiTrimDeviceColdReset(uint32_t ui32Fcfg1Revision)
526 {
527 #if ( INCLUDE_VDDR_TEMPORARILY )
528 int32_t i32TargetTrim ; // Target trim sign extended
529 int32_t i32CurrentTrim ; // Current trim sign extended
530 int32_t i32DeltaVal ; // Delta Value for each 1/64 loop
531
532 //
533 // Check if trim of Global LDO is required. Only required on PG1 devices
534 //
535 //
536 // PG1 device. Trim the Global LDO in staircase steps to avoid
537 // system reset while all the BOD reset sources are disabled
538 //
539 i32TargetTrim = SignExtendVddrTrimValue((
540 HWREG( FCFG1_BASE + FCFG1_O_SHDW_ANA_TRIM ) &
541 FCFG1_SHDW_ANA_TRIM_VDDR_TRIM_M ) >>
542 FCFG1_SHDW_ANA_TRIM_VDDR_TRIM_S );
543
544 i32CurrentTrim = SignExtendVddrTrimValue((
545 HWREGB( ADI3_BASE + ADI_3_REFSYS_O_DCDCCTL0 ) &
546 ADI_3_REFSYS_DCDCCTL0_VDDR_TRIM_M ) >>
547 ADI_3_REFSYS_DCDCCTL0_VDDR_TRIM_S );
548
549 if ( i32TargetTrim != i32CurrentTrim ) {
550 int32_t i32Cnt; // Counter for trim loop
551 //
552 // Disbale all BOD reset sources
553 //
554 HWREG( AON_SYSCTL_BASE + AON_SYSCTL_O_RESETCTL ) = 0x00;
555
556 i32DeltaVal = i32TargetTrim - i32CurrentTrim;
557 if ( i32DeltaVal > 0 ) {
558 i32DeltaVal -= 1;
559 i32CurrentTrim = ( i32CurrentTrim + 1 ) << 6;
560 } else { // ( i32DeltaVal < 0 ) (will never become == 0)
561 i32DeltaVal += 1;
562 i32CurrentTrim = ( i32CurrentTrim << 6 ) - 1;
563 }
564
565 for ( i32Cnt = 0 ; i32Cnt < 64 ; i32Cnt++ ) {
566 i32CurrentTrim += i32DeltaVal;
567
568 HWREGB( ADI3_BASE + ADI_O_DIR + ADI_3_REFSYS_O_DCDCCTL0 ) =
569 (( i32CurrentTrim >> 6 ) <<
570 ADI_3_REFSYS_DCDCCTL0_VDDR_TRIM_S ) &
571 ADI_3_REFSYS_DCDCCTL0_VDDR_TRIM_M;
572
573 //
574 // Delay a total of approx. 300 uS for all 64 rounds in the loop
575 //
576 CPU_DELAY_MICRO_SECONDS( 300.0 / 64.0 );
577 }
578
579 //
580 // Delay additionally 700 uS if going more than 1 step down
581 // (i32DeltaVal is less than 0 only when going more than one step down)
582 //
583 if ( i32DeltaVal < 0 ) {
584 CPU_DELAY_MICRO_SECONDS( 700.0 );
585 }
586
587 //
588 // Enable all BOD reset sources
589 //
590 HWREG( AON_SYSCTL_BASE + AON_SYSCTL_O_RESETCTL ) = (
591 AON_SYSCTL_RESETCTL_CLK_LOSS_EN |
592 AON_SYSCTL_RESETCTL_VDD_LOSS_EN |
593 AON_SYSCTL_RESETCTL_VDDR_LOSS_EN |
594 AON_SYSCTL_RESETCTL_VDDS_LOSS_EN );
595 }
596 #endif
597 }
598
599 //*****************************************************************************
600 //
603 //
604 //*****************************************************************************
605 static uint32_t
606 GetTrimForAnabypassValue1( uint32_t ui32Fcfg1Revision, uint32_t ccfg_ModeConfReg )
607 {
608 uint32_t ui32Fcfg1Value ;
609 uint32_t ui32XoscHfRow ;
610 uint32_t ui32XoscHfCol ;
611 int32_t i32CustomerDeltaAdjust ;
612 uint32_t ui32TrimValue ;
613
614 if ( ui32Fcfg1Revision == 0 ) {
615 // Set hardcoded trim values for all bit fields in the
616 // ANABYPASS_VALUE1 register
617 ui32TrimValue = 0x000F0FFF;
618 } else {
619 // Use device specific trim values located in factory configuration
620 // area for the XOSC_HF_COLUMN_Q12 and XOSC_HF_ROW_Q12 bit fields in
621 // the ANABYPASS_VALUE1 register. Value for the other bit fields
622 // are set to 0.
623
624 ui32Fcfg1Value = HWREG(FCFG1_BASE + FCFG1_O_CONFIG_OSC_TOP);
625 ui32XoscHfRow = (( ui32Fcfg1Value &
626 FCFG1_CONFIG_OSC_TOP_XOSC_HF_ROW_Q12_M ) >>
627 FCFG1_CONFIG_OSC_TOP_XOSC_HF_ROW_Q12_S );
628 ui32XoscHfCol = (( ui32Fcfg1Value &
629 FCFG1_CONFIG_OSC_TOP_XOSC_HF_COLUMN_Q12_M ) >>
630 FCFG1_CONFIG_OSC_TOP_XOSC_HF_COLUMN_Q12_S );
631
632 i32CustomerDeltaAdjust = 0;
633 if (( ccfg_ModeConfReg & CCFG_MODE_CONF_XOSC_CAP_MOD ) == 0 ) {
634 // XOSC_CAP_MOD = 0 means: CAP_ARRAY_DELTA is in use -> Apply compensation
635 // XOSC_CAPARRAY_DELTA is located in bit[15:8] of ccfg_ModeConfReg
636 // Note: HW_REV_DEPENDENT_IMPLEMENTATION. Field width is not given by
637 // a define and sign extention must therefore be hardcoded.
638 // ( A small testprogram is created vrifying the code lines below:
639 // Ref.: ..\test\small_standalone_test_programs\CapArrayDeltaAdjust_test.c)
640 i32CustomerDeltaAdjust = ((int32_t)ccfg_ModeConfReg << 16 ) >> 24;
641
642 while ( i32CustomerDeltaAdjust < 0 ) {
643 ui32XoscHfCol >>= 1; // COL 1 step down
644 if ( ui32XoscHfCol == 0 ) { // if COL below minimum
645 ui32XoscHfCol = 0xFFFF; // Set COL to maximum
646 ui32XoscHfRow >>= 1; // ROW 1 step down
647 if ( ui32XoscHfRow == 0 ) { // if ROW below minimum
648 ui32XoscHfRow = 1; // Set both ROW and COL
649 ui32XoscHfCol = 1; // to minimum
650 }
651 }
652 i32CustomerDeltaAdjust++;
653 }
654 while ( i32CustomerDeltaAdjust > 0 ) {
655 ui32XoscHfCol = ( ui32XoscHfCol << 1 ) | 1; // COL 1 step up
656 if ( ui32XoscHfCol > 0xFFFF ) { // if COL abowe maximum
657 ui32XoscHfCol = 1; // Set COL to minimum
658 ui32XoscHfRow = ( ui32XoscHfRow << 1 ) | 1; // ROW 1 step up
659 if ( ui32XoscHfRow > 0xF ) { // if ROW abowe maximum
660 ui32XoscHfRow = 0xF; // Set both ROW and COL
661 ui32XoscHfCol = 0xFFFF; // to maximum
662 }
663 }
664 i32CustomerDeltaAdjust--;
665 }
666 }
667
668 ui32TrimValue = (( ui32XoscHfRow << DDI_0_OSC_ANABYPASSVAL1_XOSC_HF_ROW_Q12_S ) |
669 ( ui32XoscHfCol << DDI_0_OSC_ANABYPASSVAL1_XOSC_HF_COLUMN_Q12_S ) );
670 }
671
672 return (ui32TrimValue);
673 }
674
675 //*****************************************************************************
676 //
679 //
680 //*****************************************************************************
681 static uint32_t
682 GetTrimForRcOscLfRtuneCtuneTrim(uint32_t ui32Fcfg1Revision)
683 {
684 uint32_t ui32TrimValue;
685
686 if ( ui32Fcfg1Revision == 0 ) {
687 // Use hardcoded trim value
688 ui32TrimValue = 0x00D8;
689 } else {
690 // Use device specific trim values located in factory configuration
691 // area
692 ui32TrimValue =
693 ((HWREG(FCFG1_BASE + FCFG1_O_CONFIG_OSC_TOP) &
694 FCFG1_CONFIG_OSC_TOP_RCOSCLF_CTUNE_TRIM_M)>>
695 FCFG1_CONFIG_OSC_TOP_RCOSCLF_CTUNE_TRIM_S)<<
696 DDI_0_OSC_LFOSCCTL_RCOSCLF_CTUNE_TRIM_S;
697
698 ui32TrimValue |=
699 ((HWREG(FCFG1_BASE + FCFG1_O_CONFIG_OSC_TOP) &
700 FCFG1_CONFIG_OSC_TOP_RCOSCLF_RTUNE_TRIM_M)>>
701 FCFG1_CONFIG_OSC_TOP_RCOSCLF_RTUNE_TRIM_S)<<
702 DDI_0_OSC_LFOSCCTL_RCOSCLF_RTUNE_TRIM_S;
703 }
704
705 return(ui32TrimValue);
706 }
707
708 //*****************************************************************************
709 //
712 //
713 //*****************************************************************************
714 static uint32_t
715 GetTrimForXoscHfIbiastherm(uint32_t ui32Fcfg1Revision)
716 {
717 uint32_t ui32TrimValue;
718
719 if ( ui32Fcfg1Revision == 0 ) {
720 // Use hardcoded trim value
721 ui32TrimValue = 0x03FF;
722 } else {
723 // Use device specific trim value located in factory configuration
724 // area
725 ui32TrimValue =
726 (HWREG(FCFG1_BASE + FCFG1_O_ANABYPASS_VALUE2) &
727 FCFG1_ANABYPASS_VALUE2_XOSC_HF_IBIASTHERM_M)>>
728 FCFG1_ANABYPASS_VALUE2_XOSC_HF_IBIASTHERM_S;
729 }
730
731 return(ui32TrimValue);
732 }
733
734 //*****************************************************************************
735 //
737 //
738 //*****************************************************************************
739 static uint32_t
740 GetTrimForAmpcompTh2(uint32_t ui32Fcfg1Revision)
741 {
742 uint32_t ui32TrimValue;
743 uint32_t ui32Fcfg1Value;
744
745 if ( ui32Fcfg1Revision == 0 ) {
746 // Use hardcoded trim values
747 ui32TrimValue = 0x68880000;
748 } else {
749 // Use device specific trim value located in factory configuration
750 // area. All defined register bit fields have corresponding trim
751 // value in the factory configuration area
752 ui32Fcfg1Value = HWREG(FCFG1_BASE + FCFG1_O_AMPCOMP_TH2);
753 ui32TrimValue = ((ui32Fcfg1Value &
754 FCFG1_AMPCOMP_TH2_LPMUPDATE_LTH_M)>>
755 FCFG1_AMPCOMP_TH2_LPMUPDATE_LTH_S)<<
756 DDI_0_OSC_AMPCOMPTH2_LPMUPDATE_LTH_S;
757 ui32TrimValue |= (((ui32Fcfg1Value &
758 FCFG1_AMPCOMP_TH2_LPMUPDATE_HTM_M)>>
759 FCFG1_AMPCOMP_TH2_LPMUPDATE_HTM_S)<<
760 DDI_0_OSC_AMPCOMPTH2_LPMUPDATE_HTH_S);
761 ui32TrimValue |= (((ui32Fcfg1Value &
762 FCFG1_AMPCOMP_TH2_ADC_COMP_AMPTH_LPM_M)>>
763 FCFG1_AMPCOMP_TH2_ADC_COMP_AMPTH_LPM_S)<<
764 DDI_0_OSC_AMPCOMPTH2_ADC_COMP_AMPTH_LPM_S);
765 ui32TrimValue |= (((ui32Fcfg1Value &
766 FCFG1_AMPCOMP_TH2_ADC_COMP_AMPTH_HPM_M)>>
767 FCFG1_AMPCOMP_TH2_ADC_COMP_AMPTH_HPM_S)<<
768 DDI_0_OSC_AMPCOMPTH2_ADC_COMP_AMPTH_HPM_S);
769 }
770
771 return(ui32TrimValue);
772 }
773
774 //*****************************************************************************
775 //
777 //
778 //*****************************************************************************
779 static uint32_t
780 GetTrimForAmpcompTh1(uint32_t ui32Fcfg1Revision)
781 {
782 uint32_t ui32TrimValue;
783 uint32_t ui32Fcfg1Value;
784
785 if ( ui32Fcfg1Revision == 0 ) {
786 // Use hardcoded trim values
787 ui32TrimValue = 0x0068768A;
788 } else {
789 // Use device specific trim values located in factory configuration
790 // area. All defined register bit fields have a corresponding trim
791 // value in the factory configuration area
792 ui32Fcfg1Value = HWREG(FCFG1_BASE + FCFG1_O_AMPCOMP_TH1);
793 ui32TrimValue = (((ui32Fcfg1Value &
794 FCFG1_AMPCOMP_TH1_HPMRAMP3_LTH_M)>>
795 FCFG1_AMPCOMP_TH1_HPMRAMP3_LTH_S)<<
796 DDI_0_OSC_AMPCOMPTH1_HPMRAMP3_LTH_S);
797 ui32TrimValue |= (((ui32Fcfg1Value &
798 FCFG1_AMPCOMP_TH1_HPMRAMP3_HTH_M)>>
799 FCFG1_AMPCOMP_TH1_HPMRAMP3_HTH_S)<<
800 DDI_0_OSC_AMPCOMPTH1_HPMRAMP3_HTH_S);
801 ui32TrimValue |= (((ui32Fcfg1Value &
802 FCFG1_AMPCOMP_TH1_IBIASCAP_LPTOHP_OL_CNT_M)>>
803 FCFG1_AMPCOMP_TH1_IBIASCAP_LPTOHP_OL_CNT_S)<<
804 DDI_0_OSC_AMPCOMPTH1_IBIASCAP_LPTOHP_OL_CNT_S);
805 ui32TrimValue |= (((ui32Fcfg1Value &
806 FCFG1_AMPCOMP_TH1_HPMRAMP1_TH_M)>>
807 FCFG1_AMPCOMP_TH1_HPMRAMP1_TH_S)<<
808 DDI_0_OSC_AMPCOMPTH1_HPMRAMP1_TH_S);
809 }
810
811 return(ui32TrimValue);
812 }
813
814 //*****************************************************************************
815 //
817 //
818 //*****************************************************************************
819 static uint32_t
820 GetTrimForAmpcompCtrl(uint32_t ui32Fcfg1Revision)
821 {
822 uint32_t ui32TrimValue ;
823 uint32_t ui32Fcfg1Value ;
824 uint32_t ibiasOffset ;
825 uint32_t ibiasInit ;
826 uint32_t modeConf1 ;
827 int32_t deltaAdjust ;
828
829 if ( ui32Fcfg1Revision == 0 ) {
830 // Use hardcoded trim values
831 ui32TrimValue = 0x00713F27;
832 } else {
833 // Use device specific trim valuse loacted in factory configuration
834 // area. Register bit fields without trim values in the factory
835 // configuration area will be set to the value of 0.
836 ui32Fcfg1Value = HWREG( FCFG1_BASE + FCFG1_O_AMPCOMP_CTRL1 );
837
838 ibiasOffset = ( ui32Fcfg1Value &
839 FCFG1_AMPCOMP_CTRL1_IBIAS_OFFSET_M ) >>
840 FCFG1_AMPCOMP_CTRL1_IBIAS_OFFSET_S ;
841 ibiasInit = ( ui32Fcfg1Value &
842 FCFG1_AMPCOMP_CTRL1_IBIAS_INIT_M ) >>
843 FCFG1_AMPCOMP_CTRL1_IBIAS_INIT_S ;
844
845 if (( HWREG( CCFG_BASE + CCFG_O_SIZE_AND_DIS_FLAGS ) & CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR_M ) == 0 ) {
846 // Adjust with DELTA_IBIAS_OFFSET and DELTA_IBIAS_INIT from CCFG
847 modeConf1 = HWREG( CCFG_BASE + CCFG_O_MODE_CONF_1 );
848
849 // Both fields are signed 4-bit values. This is an assumption when doing the sign extention.
850 deltaAdjust = (int32_t)modeConf1 << ( 32 - CCFG_MODE_CONF_1_DELTA_IBIAS_OFFSET_S - 4 ) >> 28;
851 deltaAdjust += (int32_t)ibiasOffset;
852 if ( deltaAdjust < 0 ) {
853 deltaAdjust = 0;
854 }
855 if ( deltaAdjust > ( DDI_0_OSC_AMPCOMPCTL_IBIAS_OFFSET_M >> DDI_0_OSC_AMPCOMPCTL_IBIAS_OFFSET_S )) {
856 deltaAdjust = ( DDI_0_OSC_AMPCOMPCTL_IBIAS_OFFSET_M >> DDI_0_OSC_AMPCOMPCTL_IBIAS_OFFSET_S );
857 }
858 ibiasOffset = (uint32_t)deltaAdjust;
859
860 deltaAdjust = (int32_t)modeConf1 << ( 32 - CCFG_MODE_CONF_1_DELTA_IBIAS_INIT_S - 4 ) >> 28;
861 deltaAdjust += (int32_t)ibiasInit;
862 if ( deltaAdjust < 0 ) {
863 deltaAdjust = 0;
864 }
865 if ( deltaAdjust > ( DDI_0_OSC_AMPCOMPCTL_IBIAS_INIT_M >> DDI_0_OSC_AMPCOMPCTL_IBIAS_INIT_S )) {
866 deltaAdjust = ( DDI_0_OSC_AMPCOMPCTL_IBIAS_INIT_M >> DDI_0_OSC_AMPCOMPCTL_IBIAS_INIT_S );
867 }
868 ibiasInit = (uint32_t)deltaAdjust;
869 }
870 ui32TrimValue = ( ibiasOffset << DDI_0_OSC_AMPCOMPCTL_IBIAS_OFFSET_S ) |
871 ( ibiasInit << DDI_0_OSC_AMPCOMPCTL_IBIAS_INIT_S ) ;
872
873 ui32TrimValue |= (((ui32Fcfg1Value &
874 FCFG1_AMPCOMP_CTRL1_LPM_IBIAS_WAIT_CNT_FINAL_M)>>
875 FCFG1_AMPCOMP_CTRL1_LPM_IBIAS_WAIT_CNT_FINAL_S)<<
876 DDI_0_OSC_AMPCOMPCTL_LPM_IBIAS_WAIT_CNT_FINAL_S);
877 ui32TrimValue |= (((ui32Fcfg1Value &
878 FCFG1_AMPCOMP_CTRL1_CAP_STEP_M)>>
879 FCFG1_AMPCOMP_CTRL1_CAP_STEP_S)<<
880 DDI_0_OSC_AMPCOMPCTL_CAP_STEP_S);
881 ui32TrimValue |= (((ui32Fcfg1Value &
882 FCFG1_AMPCOMP_CTRL1_IBIASCAP_HPTOLP_OL_CNT_M)>>
883 FCFG1_AMPCOMP_CTRL1_IBIASCAP_HPTOLP_OL_CNT_S)<<
884 DDI_0_OSC_AMPCOMPCTL_IBIASCAP_HPTOLP_OL_CNT_S);
885
886 if ( ui32Fcfg1Revision >= 0x00000022 ) {
887 ui32TrimValue |= ((( ui32Fcfg1Value &
888 FCFG1_AMPCOMP_CTRL1_AMPCOMP_REQ_MODE_M ) >>
889 FCFG1_AMPCOMP_CTRL1_AMPCOMP_REQ_MODE_S ) <<
890 DDI_0_OSC_AMPCOMPCTL_AMPCOMP_REQ_MODE_S );
891 }
892 }
893
894 return(ui32TrimValue);
895 }
896
897 //*****************************************************************************
898 //
900 //
901 //*****************************************************************************
902 static uint32_t
903 GetTrimForDblrLoopFilterResetVoltage( uint32_t ui32Fcfg1Revision )
904 {
905 uint32_t dblrLoopFilterResetVoltageValue = 0; // Reset value
906
907 if ( ui32Fcfg1Revision >= 0x00000020 ) {
908 dblrLoopFilterResetVoltageValue = ( HWREG( FCFG1_BASE + FCFG1_O_MISC_OTP_DATA_1 ) &
909 FCFG1_MISC_OTP_DATA_1_DBLR_LOOP_FILTER_RESET_VOLTAGE_M ) >>
910 FCFG1_MISC_OTP_DATA_1_DBLR_LOOP_FILTER_RESET_VOLTAGE_S;
911 }
912
913 return ( dblrLoopFilterResetVoltageValue );
914 }
915
916 //*****************************************************************************
917 //
919 //
920 //*****************************************************************************
921 static uint32_t
922 GetTrimForAdcShModeEn( uint32_t ui32Fcfg1Revision )
923 {
924 uint32_t getTrimForAdcShModeEnValue = 1; // Recommanded default setting
925
926 if ( ui32Fcfg1Revision >= 0x00000022 ) {
927 getTrimForAdcShModeEnValue = ( HWREG( FCFG1_BASE + FCFG1_O_OSC_CONF ) &
928 FCFG1_OSC_CONF_ADC_SH_MODE_EN_M ) >>
929 FCFG1_OSC_CONF_ADC_SH_MODE_EN_S;
930 }
931
932 return ( getTrimForAdcShModeEnValue );
933 }
934
935 //*****************************************************************************
936 //
938 //
939 //*****************************************************************************
940 static uint32_t
941 GetTrimForAdcShVbufEn( uint32_t ui32Fcfg1Revision )
942 {
943 uint32_t getTrimForAdcShVbufEnValue = 1; // Recommanded default setting
944
945 if ( ui32Fcfg1Revision >= 0x00000022 ) {
946 getTrimForAdcShVbufEnValue = ( HWREG( FCFG1_BASE + FCFG1_O_OSC_CONF ) &
947 FCFG1_OSC_CONF_ADC_SH_VBUF_EN_M ) >>
948 FCFG1_OSC_CONF_ADC_SH_VBUF_EN_S;
949 }
950
951 return ( getTrimForAdcShVbufEnValue );
952 }
953
954 //*****************************************************************************
955 //
957 //
958 //*****************************************************************************
959 static uint32_t
960 GetTrimForXoscHfCtl( uint32_t ui32Fcfg1Revision )
961 {
962 uint32_t getTrimForXoschfCtlValue = 0; // Recommanded default setting
963 uint32_t fcfg1Data;
964
965 if ( ui32Fcfg1Revision >= 0x00000020 ) {
966 fcfg1Data = HWREG( FCFG1_BASE + FCFG1_O_MISC_OTP_DATA_1 );
967 getTrimForXoschfCtlValue =
968 ( ( ( fcfg1Data & FCFG1_MISC_OTP_DATA_1_PEAK_DET_ITRIM_M ) >>
969 FCFG1_MISC_OTP_DATA_1_PEAK_DET_ITRIM_S ) <<
970 DDI_0_OSC_XOSCHFCTL_PEAK_DET_ITRIM_S);
971
972 getTrimForXoschfCtlValue |=
973 ( ( ( fcfg1Data & FCFG1_MISC_OTP_DATA_1_HP_BUF_ITRIM_M ) >>
974 FCFG1_MISC_OTP_DATA_1_HP_BUF_ITRIM_S ) <<
975 DDI_0_OSC_XOSCHFCTL_HP_BUF_ITRIM_S);
976
977 getTrimForXoschfCtlValue |=
978 ( ( ( fcfg1Data & FCFG1_MISC_OTP_DATA_1_LP_BUF_ITRIM_M ) >>
979 FCFG1_MISC_OTP_DATA_1_LP_BUF_ITRIM_S ) <<
980 DDI_0_OSC_XOSCHFCTL_LP_BUF_ITRIM_S);
981 }
982
983 return ( getTrimForXoschfCtlValue );
984 }
985
986 //*****************************************************************************
987 //
989 //
990 //*****************************************************************************
991 static uint32_t
992 GetTrimForXoscHfFastStart( uint32_t ui32Fcfg1Revision )
993 {
994 uint32_t ui32XoscHfFastStartValue ;
995
996 if ( ui32Fcfg1Revision == 0 ) {
997 // Use reset value
998 ui32XoscHfFastStartValue = 0;
999 } else {
1000 // Get value from FCFG1
1001 ui32XoscHfFastStartValue = ( HWREG( FCFG1_BASE + FCFG1_O_OSC_CONF ) &
1002 FCFG1_OSC_CONF_XOSC_HF_FAST_START_M ) >>
1003 FCFG1_OSC_CONF_XOSC_HF_FAST_START_S;
1004 }
1005
1006 return ( ui32XoscHfFastStartValue );
1007 }
1008
1009 //*****************************************************************************
1010 //
1012 //
1013 //*****************************************************************************
1014 static uint32_t
1015 GetTrimForRadcExtCfg( uint32_t ui32Fcfg1Revision )
1016 {
1017 uint32_t getTrimForRadcExtCfgValue = 0x403F8000; // Recommanded default setting
1018 uint32_t fcfg1Data;
1019
1020 if ( ui32Fcfg1Revision >= 0x00000020 ) {
1021 fcfg1Data = HWREG( FCFG1_BASE + FCFG1_O_MISC_OTP_DATA_1 );
1022 getTrimForRadcExtCfgValue =
1023 ( ( ( fcfg1Data & FCFG1_MISC_OTP_DATA_1_HPM_IBIAS_WAIT_CNT_M ) >>
1024 FCFG1_MISC_OTP_DATA_1_HPM_IBIAS_WAIT_CNT_S ) <<
1025 DDI_0_OSC_RADCEXTCFG_HPM_IBIAS_WAIT_CNT_S);
1026
1027 getTrimForRadcExtCfgValue |=
1028 ( ( ( fcfg1Data & FCFG1_MISC_OTP_DATA_1_LPM_IBIAS_WAIT_CNT_M ) >>
1029 FCFG1_MISC_OTP_DATA_1_LPM_IBIAS_WAIT_CNT_S ) <<
1030 DDI_0_OSC_RADCEXTCFG_LPM_IBIAS_WAIT_CNT_S);
1031
1032 getTrimForRadcExtCfgValue |=
1033 ( ( ( fcfg1Data & FCFG1_MISC_OTP_DATA_1_IDAC_STEP_M ) >>
1034 FCFG1_MISC_OTP_DATA_1_IDAC_STEP_S ) <<
1035 DDI_0_OSC_RADCEXTCFG_IDAC_STEP_S);
1036 }
1037
1038 return ( getTrimForRadcExtCfgValue );
1039 }
1040
1041 //*****************************************************************************
1042 //
1043 // Returns the FCFG1_OSC_CONF_ATESTLF_RCOSCLF_IBIAS_TRIM
1044 //
1045 //*****************************************************************************
1046 static uint32_t
1047 GetTrimForRcOscLfIBiasTrim( uint32_t ui32Fcfg1Revision )
1048 {
1049 uint32_t trimForRcOscLfIBiasTrimValue = 0; // Default value
1050
1051 if ( ui32Fcfg1Revision >= 0x00000022 ) {
1052 trimForRcOscLfIBiasTrimValue = ( HWREG( FCFG1_BASE + FCFG1_O_OSC_CONF ) &
1053 FCFG1_OSC_CONF_ATESTLF_RCOSCLF_IBIAS_TRIM_M ) >>
1054 FCFG1_OSC_CONF_ATESTLF_RCOSCLF_IBIAS_TRIM_S ;
1055 }
1056
1057 return ( trimForRcOscLfIBiasTrimValue );
1058 }
1059
1060 //*****************************************************************************
1061 //
1062 // Returns XOSCLF_REGULATOR_TRIM and XOSCLF_CMIRRWR_RATIO as one packet
1063 // spanning bits [5:0] in the returned value.
1064 //
1065 //*****************************************************************************
1066 static uint32_t
1067 GetTrimForXoscLfRegulatorAndCmirrwrRatio( uint32_t ui32Fcfg1Revision )
1068 {
1069 uint32_t trimForXoscLfRegulatorAndCmirrwrRatioValue = 0; // Default value for both fields
1070
1071 if ( ui32Fcfg1Revision >= 0x00000022 ) {
1072 trimForXoscLfRegulatorAndCmirrwrRatioValue = ( HWREG( FCFG1_BASE + FCFG1_O_OSC_CONF ) &
1073 ( FCFG1_OSC_CONF_XOSCLF_REGULATOR_TRIM_M |
1074 FCFG1_OSC_CONF_XOSCLF_CMIRRWR_RATIO_M )) >>
1075 FCFG1_OSC_CONF_XOSCLF_CMIRRWR_RATIO_S ;
1076 }
1077
1078 return ( trimForXoscLfRegulatorAndCmirrwrRatioValue );
1079 }
prcm.h
CPU_DELAY_MICRO_SECONDS
#define CPU_DELAY_MICRO_SECONDS(x)
Definition: setup.c:136
DDI32RegWrite
__STATIC_INLINE void DDI32RegWrite(uint32_t ui32Base, uint32_t ui32Reg, uint32_t ui32Val)
Write a 32 bit value to a register in the DDI slave.
Definition: ddi.h:418
sys_ctrl.h
trimDevice
void trimDevice(void)
Definition: setup.c:150
CLK_LF_XOSC_LF
#define CLK_LF_XOSC_LF
Definition: setup.c:87
CLK_LF_XOSC_HF
#define CLK_LF_XOSC_HF
Definition: setup.c:88
DDI16BitfieldWrite
void DDI16BitfieldWrite(uint32_t ui32Base, uint32_t ui32Reg, uint32_t ui32Mask, uint32_t ui32Shift, uint16_t ui32Data)
Write a bitfield via the DDI using 16-bit maskable write.
Definition: ddi.c:108
ThisCodeIsBuiltForCC26xxHwRev22AndLater_HaltIfViolated
void ThisCodeIsBuiltForCC26xxHwRev22AndLater_HaltIfViolated(void)
Verifies that current chip is built for CC26xx HwRev 2.2 or later and never returns if violated...
Definition: chipinfo.c:161
adi.h
OSC_XOSC_HF
#define OSC_XOSC_HF
Definition: osc.h:111
OSC_SRC_CLK_LF
#define OSC_SRC_CLK_LF
Definition: osc.h:108
ddi.h
chipinfo.h
OSC_RCOSC_LF
#define OSC_RCOSC_LF
Definition: osc.h:112
cpu.h
aon_batmon.h
SysCtrlAonSync
__STATIC_INLINE void SysCtrlAonSync(void)
Sync all accesses to the AON register interface.
Definition: sys_ctrl.h:248
OSCClockSourceSet
void OSCClockSourceSet(uint32_t ui32SrcClk, uint32_t ui32Osc)
Configure the oscillator input to the a source clock.
Definition: osc.c:85
OSC_XOSC_LF
#define OSC_XOSC_LF
Definition: osc.h:113