## WDT

Instance: WDT
Component: WDT
Base address: 0x40080000

Watchdog Timer

### TOP:WDT Register Summary

Register Name | Type | Register Width (Bits) | Register Reset | Address Offset | Physical Address
LOAD | RW | 32 | 0xFFFF FFFF | 0x0000 0000 | 0x4008 0000
VALUE | RO | 32 | 0xFFFF FFFF | 0x0000 0004 | 0x4008 0004
CTL | RW | 32 | 0x0000 0000 | 0x0000 0008 | 0x4008 0008
ICR | WO | 32 | 0x0000 0000 | 0x0000 000C | 0x4008 000C
RIS | RO | 32 | 0x0000 0000 | 0x0000 0010 | 0x4008 0010
MIS | RO | 32 | 0x0000 0000 | 0x0000 0014 | 0x4008 0014
TEST | RW | 32 | 0x0000 0000 | 0x0000 0418 | 0x4008 0418
INT_CAUS | RO | 32 | 0x0000 0000 | 0x0000 041C | 0x4008 041C
LOCK | RW | 32 | 0x0000 0000 | 0x0000 0C00 | 0x4008 0C00
PERIPHID4 | RO | 32 | 0x0000 0000 | 0x0000 0FD0 | 0x4008 0FD0
PERIPHID5 | RO | 32 | 0x0000 0000 | 0x0000 0FD4 | 0x4008 0FD4
PERIPHID6 | RO | 32 | 0x0000 0000 | 0x0000 0FD8 | 0x4008 0FD8
PERIPHID7 | RO | 32 | 0x0000 0000 | 0x0000 0FDC | 0x4008 0FDC
PERIPHID0 | RO | 32 | 0x0000 0005 | 0x0000 0FE0 | 0x4008 0FE0
PERIPHID1 | RO | 32 | 0x0000 0018 | 0x0000 0FE4 | 0x4008 0FE4
PERIPHID2 | RO | 32 | 0x0000 0018 | 0x0000 0FE8 | 0x4008 0FE8
PERIPHID3 | RO | 32 | 0x0000 0001 | 0x0000 0FEC | 0x4008 0FEC
PCELLD0 | RO | 32 | 0x0000 000D | 0x0000 0FF0 | 0x4008 0FF0
PCELLD1 | RO | 32 | 0x0000 00F0 | 0x0000 0FF4 | 0x4008 0FF4
PCELLD2 | RO | 32 | 0x0000 0006 | 0x0000 0FF8 | 0x4008 0FF8
PCELLD3 | RO | 32 | 0x0000 00B1 | 0x0000 0FFC | 0x4008 0FFC

### TOP:WDT Register Descriptions

### TOP:WDT:LOAD

Address offset | 0x0000 0000
Physical address | 0x4008 0000 | Instance | WDT
Description | WDT Configuration
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | WDTLOAD | This register is the 32-bit interval value used by the 32-bit counter. When this register is written, the value is immediately loaded and the counter is restarted to count down from the new value. If this register is loaded with 0x0000.0000, an interrupt is immediately generated. | RW | 0xFFFF FFFF

### TOP:WDT:VALUE

Address offset | 0x0000 0004
Physical address | 0x4008 0004 | Instance | WDT
Description | WDT Current Count Value
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | WDTVALUE | This register contains the current count value of the timer. | RO | 0xFFFF FFFF

### TOP:WDT:CTL

Address offset | 0x0000 0008
Physical address | 0x4008 0008 | Instance | WDT
Description | WDT Control
Type | RW

Bits | Field Name | Description | Type | Reset
31:3 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0000 0000
2 | INTTYPE | WDT Interrupt Type 0: WDT interrupt is a standard interrupt. 1: WDT interrupt is a non-maskable interrupt.
Value | ENUM name | Description
0 | MASKABLE | Maskable interrupt
1 | NONMASKABLE | Non-maskable interrupt
| RW | 0
1 | RESEN | WDT Reset Enable. Defines the function of the WDT reset source (see PRCM:WARMRESET.WDT_STAT if enabled) 0: Disabled. 1: Enable the Watchdog reset output.
Value | ENUM name | Description
0 | DIS | Reset output Disabled
1 | EN | Reset output Enabled
| RW | 0
0 | INTEN | WDT Interrupt Enable 0: Interrupt event disabled. 1: Interrupt event enabled. Once set, this bit can only be cleared by a hardware reset.
Value | ENUM name | Description
0 | DIS | Interrupt Disabled
1 | EN | Interrupt Enabled
| RW | 0

### TOP:WDT:ICR

Address offset | 0x0000 000C
Physical address | 0x4008 000C | Instance | WDT
Description | WDT Interrupt Clear
Type | WO

Bits | Field Name | Description | Type | Reset
31:0 | WDTICR | This register is the interrupt clear register. A write of any value to this register clears the WDT interrupt and reloads the 32-bit counter from the LOAD register. | WO | 0x0000 0000

### TOP:WDT:RIS

Address offset | 0x0000 0010
Physical address | 0x4008 0010 | Instance | WDT
Description | WDT Raw Interrupt Status
Type | RO

Bits | Field Name | Description | Type | Reset
31:1 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0000 0000
0 | WDTRIS | This register is the raw interrupt status register. WDT interrupt events can be monitored via this register if the controller interrupt is masked. Value Description 0: The WDT has not timed out 1: A WDT time-out event has occurred | RO | 0

### TOP:WDT:MIS

Address offset | 0x0000 0014
Physical address | 0x4008 0014 | Instance | WDT
Description | WDT Masked Interrupt Status
Type | RO

Bits | Field Name | Description | Type | Reset
31:1 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0000 0000
0 | WDTMIS | This register is the masked interrupt status register. The value of this register is the logical AND of the raw interrupt bit and the WDT interrupt enable bit CTL.INTEN. Value Description 0: The WDT has not timed out or is masked. 1: An unmasked WDT time-out event has occurred. | RO | 0

### TOP:WDT:TEST

Address offset | 0x0000 0418
Physical address | 0x4008 0418 | Instance | WDT
Description | WDT Test Mode
Type | RW

Bits | Field Name | Description | Type | Reset
31:9 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x00 0000
8 | STALL | WDT Stall Enable 0: The WDT timer continues counting if the CPU is stopped with a debugger. 1: If the CPU is stopped with a debugger, the WDT stops counting. Once the CPU is restarted, the WDT resumes counting.
Value | ENUM name | Description
0 | DIS | Disable STALL
1 | EN | Enable STALL
| RW | 0
7:1 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x00
0 | TEST_EN | The test enable bit 0: Enable external reset 1: Disables the generation of an external reset. Instead bit 1 of the INT_CAUS register is set and an interrupt is generated
Value | ENUM name | Description
0 | DIS | Test mode Disabled
1 | EN | Test mode Enabled
| RW | 0

### TOP:WDT:INT_CAUS

Address offset | 0x0000 041C
Physical address | 0x4008 041C | Instance | WDT
Description | WDT Interrupt Cause Test Mode ITERNAL_NOTE: This register shows the status of Reset and Interrupt when test mode is enabled, TEST.TEST_EN
Type | RO

Bits | Field Name | Description | Type | Reset
31:2 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0000 0000
1 | CAUSE_RESET | Indicates that the cause of an interrupt was a reset generated but blocked due to TEST.TEST_EN (only possible when TEST.TEST_EN is set). | RO | 0
0 | CAUSE_INTR | Replica of RIS.WDTRIS | RO | 0

### TOP:WDT:LOCK

Address offset | 0x0000 0C00
Physical address | 0x4008 0C00 | Instance | WDT
Description | WDT Lock Register
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | WDTLOCK | WDT Lock: A write of the value 0x1ACC.E551 unlocks the watchdog registers for write access. A write of any other value reapplies the lock, preventing any register updates (NOTE: TEST.TEST_EN bit is not lockable). A read of this register returns the following values: 0x0000.0000: Unlocked 0x0000.0001: Locked | RW | 0x0000 0000

### TOP:WDT:PERIPHID4

Address offset | 0x0000 0FD0
Physical address | 0x4008 0FD0 | Instance | WDT
Description | WDT Identity
Type | RO

Bits | Field Name | Description | Type | Reset
31:8 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x00 0000
7:0 | PID4 | WDT Peripheral ID Register [39:32] | RO | 0x00

### TOP:WDT:PERIPHID5

Address offset | 0x0000 0FD4
Physical address | 0x4008 0FD4 | Instance | WDT
Description | WDT Identity
Type | RO

Bits | Field Name | Description | Type | Reset
31:8 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x00 0000
7:0 | PID5 | WDT Peripheral ID Register [47:40] | RO | 0x00

### TOP:WDT:PERIPHID6

Address offset | 0x0000 0FD8
Physical address | 0x4008 0FD8 | Instance | WDT
Description | WDT Identity
Type | RO

Bits | Field Name | Description | Type | Reset
31:8 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x00 0000
7:0 | PID6 | WDT Peripheral ID Register [55:48] | RO | 0x00

### TOP:WDT:PERIPHID7

Address offset | 0x0000 0FDC
Physical address | 0x4008 0FDC | Instance | WDT
Description | WDT Identity
Type | RO

Bits | Field Name | Description | Type | Reset
31:8 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x00 0000
7:0 | PID7 | WDT Peripheral ID Register [63:58] | RO | 0x00

### TOP:WDT:PERIPHID0

Address offset | 0x0000 0FE0
Physical address | 0x4008 0FE0 | Instance | WDT
Description | WDT Identity
Type | RO

Bits | Field Name | Description | Type | Reset
31:8 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x00 0000
7:0 | PID0 | WDT Peripheral ID Register [7:0] | RO | 0x05

### TOP:WDT:PERIPHID1

Address offset | 0x0000 0FE4
Physical address | 0x4008 0FE4 | Instance | WDT
Description | WDT Identity
Type | RO

Bits | Field Name | Description | Type | Reset
31:8 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x00 0000
7:0 | PID1 | WDT Peripheral ID Register [15:8] | RO | 0x18

### TOP:WDT:PERIPHID2

Address offset | 0x0000 0FE8
Physical address | 0x4008 0FE8 | Instance | WDT
Description | WDT Identity
Type | RO

Bits | Field Name | Description | Type | Reset
31:8 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x00 0000
7:0 | PID2 | WDT Peripheral ID Register [23:16] | RO | 0x18

### TOP:WDT:PERIPHID3

Address offset | 0x0000 0FEC
Physical address | 0x4008 0FEC | Instance | WDT
Description | WDT Identity
Type | RO

Bits | Field Name | Description | Type | Reset
31:8 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x00 0000
7:0 | PID3 | WDT Peripheral ID Register [31:24] | RO | 0x01

### TOP:WDT:PCELLD0

Address offset | 0x0000 0FF0
Physical address | 0x4008 0FF0 | Instance | WDT
Description | WDT Cell Identity
Type | RO

Bits | Field Name | Description | Type | Reset
31:8 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x00 0000
7:0 | CID0 | WDT PrimeCell ID Register [7:0] | RO | 0x0D

### TOP:WDT:PCELLD1

Address offset | 0x0000 0FF4
Physical address | 0x4008 0FF4 | Instance | WDT
Description | WDT Cell Identity
Type | RO

Bits | Field Name | Description | Type | Reset
31:8 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x00 0000
7:0 | CID1 | WDT PrimeCell ID Register [15:8] | RO | 0xF0

### TOP:WDT:PCELLD2

Address offset | 0x0000 0FF8
Physical address | 0x4008 0FF8 | Instance | WDT
Description | WDT Cell Identity
Type | RO

Bits | Field Name | Description | Type | Reset
31:8 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x00 0000
7:0 | CID2 | WDT PrimeCell ID Register [23:16] | RO | 0x06

### TOP:WDT:PCELLD3

Address offset | 0x0000 0FFC
Physical address | 0x4008 0FFC | Instance | WDT
Description | WDT Cell Identity
Type | RO

Bits | Field Name | Description | Type | Reset
31:8 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x00 0000
7:0 | CID3 | WDT PrimeCell ID Register [31:24] | RO | 0xB1