## AUX_WUC

Instance: AUX_WUC
Component: AUX_WUC
Base address: 0x400c6000

AUX Wake-up controller

### TOP:AUX_WUC Register Summary

Register Name | Type | Register Width (Bits) | Register Reset | Address Offset | Physical Address
MODCLKEN0 | RW | 32 | 0x0000 0000 | 0x0000 0000 | 0x400C 6000
PWROFFREQ | RW | 32 | 0x0000 0000 | 0x0000 0004 | 0x400C 6004
PWRDWNREQ | RW | 32 | 0x0000 0000 | 0x0000 0008 | 0x400C 6008
PWRDWNACK | RO | 32 | 0x0000 0000 | 0x0000 000C | 0x400C 600C
CLKLFREQ | RW | 32 | 0x0000 0000 | 0x0000 0010 | 0x400C 6010
CLKLFACK | RO | 32 | 0x0000 0000 | 0x0000 0014 | 0x400C 6014
BGAPREQ | RW | 32 | 0x0000 0000 | 0x0000 0020 | 0x400C 6020
BGAPACK | RO | 32 | 0x0000 0000 | 0x0000 0024 | 0x400C 6024
WUEVFLAGS | RO | 32 | 0x0000 0000 | 0x0000 0028 | 0x400C 6028
WUEVCLR | RW | 32 | 0x0000 0000 | 0x0000 002C | 0x400C 602C
ADCCLKCTL | RW | 32 | 0x0000 0000 | 0x0000 0030 | 0x400C 6030
TDCCLKCTL | RW | 32 | 0x0000 0000 | 0x0000 0034 | 0x400C 6034
REFCLKCTL | RW | 32 | 0x0000 0000 | 0x0000 0038 | 0x400C 6038
RTCSUBSECINC0 | RW | 32 | 0x0000 0000 | 0x0000 003C | 0x400C 603C
RTCSUBSECINC1 | RW | 32 | 0x0000 0000 | 0x0000 0040 | 0x400C 6040
RTCSUBSECINCCTL | RW | 32 | 0x0000 0000 | 0x0000 0044 | 0x400C 6044
MCUBUSCTL | RW | 32 | 0x0000 0000 | 0x0000 0048 | 0x400C 6048
MCUBUSSTAT | RO | 32 | 0x0000 0000 | 0x0000 004C | 0x400C 604C
AONCTLSTAT | RO | 32 | 0x0000 0000 | 0x0000 0050 | 0x400C 6050
AUXIOLATCH | RW | 32 | 0x0000 0000 | 0x0000 0054 | 0x400C 6054
MODCLKEN1 | RW | 32 | 0x0000 0000 | 0x0000 005C | 0x400C 605C

### TOP:AUX_WUC Register Descriptions

### TOP:AUX_WUC:MODCLKEN0

Address offset | 0x0000 0000
Physical address | 0x400C 6000 | Instance | AUX_WUC
Description | Module Clock Enable Clock enable for each module in the AUX domain For use by the system CPU The settings in this register are OR'ed with the corresponding settings in MODCLKEN1. This allows the system CPU and AUX_SCE to request clocks independently. Settings take effect immediately.
Type | RW

Bits | Field Name | Description | Type | Reset
31:8 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x00 0000
7 | AUX_ADI4 | Enables (1) or disables (0) clock for AUX_ADI4.
Value | ENUM name | Description
0 | DIS | System CPU has not requested clock for AUX_ADI4
1 | EN | System CPU has requested clock for AUX_ADI4
| RW | 0
6 | AUX_DDI0_OSC | Enables (1) or disables (0) clock for AUX_DDI0_OSC.
Value | ENUM name | Description
0 | DIS | System CPU has not requested clock for AUX_DDI0_OSC
1 | EN | System CPU has requested clock for AUX_DDI0_OSC
| RW | 0
5 | TDC | Enables (1) or disables (0) clock for AUX_TDCIF. Note that the TDC counter and reference clock sources must be requested separately using TDCCLKCTL and REFCLKCTL, respectively.
Value | ENUM name | Description
0 | DIS | System CPU has not requested clock for TDC
1 | EN | System CPU has requested clock for TDC
| RW | 0
4 | SOC | Enables (1) or disables (0) clock for AUX_SOC. Note that the ADC internal clock must be requested separately using ADCCLKCTL.
Value | ENUM name | Description
0 | DIS | System CPU has not requested clock for SOC
1 | EN | System CPU has requested clock for SOC
| RW | 0
3 | TIMER | Enables (1) or disables (0) clock for AUX_TIMER.
Value | ENUM name | Description
0 | DIS | System CPU has not requested clock for TIMER
1 | EN | System CPU has requested clock for TIMER
| RW | 0
2 | AIODIO1 | Enables (1) or disables (0) clock for AUX_AIODIO1.
Value | ENUM name | Description
0 | DIS | System CPU has not requested clock for AIODIO1
1 | EN | System CPU has requested clock for AIODIO1
| RW | 0
1 | AIODIO0 | Enables (1) or disables (0) clock for AUX_AIODIO0.
Value | ENUM name | Description
0 | DIS | System CPU has not requested clock for AIODIO0
1 | EN | System CPU has requested clock for AIODIO0
| RW | 0
0 | SMPH | Enables (1) or disables (0) clock for AUX_SMPH.
Value | ENUM name | Description
0 | DIS | System CPU has not requested clock for SMPH
1 | EN | System CPU has requested clock for SMPH
| RW | 0

### TOP:AUX_WUC:PWROFFREQ

Address offset | 0x0000 0004
Physical address | 0x400C 6004 | Instance | AUX_WUC
Description | Power Off Request Requests power off request for the AUX domain. When powered of the power supply and clock is disabled. This may only be used when taking the entire device into shutdown mode (i.e. with full device reset when resuming operation). Power off is prevented if AON_WUC:AUXCTL.AUX_FORCE_ON has been set, or if MCUBUSCTL.DISCONNECT_REQ has been cleared.
Type | RW

Bits | Field Name | Description | Type | Reset
31:1 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0000 0000
0 | REQ | Power off request 0: No action 1: Request to power down AUX. Once set, this bit shall not be cleared. The bit will be reset again when AUX is powered up again. The request will only happen if AONCTLSTAT.AUX_FORCE_ON = 0 and MCUBUSSTAT.DISCONNECTED=1. | RW | 0

### TOP:AUX_WUC:PWRDWNREQ

Address offset | 0x0000 0008
Physical address | 0x400C 6008 | Instance | AUX_WUC
Description | Power Down Request Request from AUX for system to enter power down. When system is in power down there is limited current supply available and the clock source is set by AON_WUC:AUXCLK.PWR_DWN_SRC
Type | RW

Bits | Field Name | Description | Type | Reset
31:1 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0000 0000
0 | REQ | Power down request 0: Request for system to be in active mode 1: Request for system to be in power down mode When REQ is 1 one shall assume that the system is in power down, and that current supply is limited. When setting REQ = 0, one shall assume that the system is in power down until PWRDWNACK.ACK = 0 | RW | 0

### TOP:AUX_WUC:PWRDWNACK

Address offset | 0x0000 000C
Physical address | 0x400C 600C | Instance | AUX_WUC
Description | Power Down Acknowledgment
Type | RO

Bits | Field Name | Description | Type | Reset
31:1 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0000 0000
0 | ACK | Power down acknowledgment. Indicates whether the power down request given by PWRDWNREQ.REQ is captured by the AON domain or not 0: AUX can assume that the system is in active mode 1: The request for power down is acknowledged and the AUX must act like the system is in power down mode and power supply is limited The system CPU cannot use this bit since the bus bridge between MCU domain and AUX domain is always disconnected when this bit is set. For AUX_SCE use only | RO | 0

### TOP:AUX_WUC:CLKLFREQ

Address offset | 0x0000 0010
Physical address | 0x400C 6010 | Instance | AUX_WUC
Description | Low Frequency Clock Request
Type | RW

Bits | Field Name | Description | Type | Reset
31:1 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0000 0000
0 | REQ | Low frequency request 0: Request clock frequency to be controlled by AON_WUC:AUXCLK and the system state 1: Request low frequency clock SCLK_LF as the clock source for AUX This bit must not be modified unless CLKLFACK.ACK matches the current value | RW | 0

### TOP:AUX_WUC:CLKLFACK

Address offset | 0x0000 0014
Physical address | 0x400C 6014 | Instance | AUX_WUC
Description | Low Frequency Clock Acknowledgment
Type | RO

Bits | Field Name | Description | Type | Reset
31:1 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0000 0000
0 | ACK | Acknowledgment of CLKLFREQ.REQ 0: Acknowledgement that clock frequency is controlled by AON_WUC:AUXCLK and the system state 1: Acknowledgement that the low frequency clock SCLK_LF is the clock source for AUX | RO | 0

### TOP:AUX_WUC:BGAPREQ

Address offset | 0x0000 0020
Physical address | 0x400C 6020 | Instance | AUX_WUC
Description | Band Gap Request
Type | RW

Bits | Field Name | Description | Type | Reset
31:1 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0000 0000
0 | REQ | AUX_SCE request for band gap reference. 0: AUX_SCE does not need band gap enabled 1: AUX_SCE needs band gap to be enabled This bit must not be modified unless GBIASACK.ACK matches the current value | RW | 0

### TOP:AUX_WUC:BGAPACK

Address offset | 0x0000 0024
Physical address | 0x400C 6024 | Instance | AUX_WUC
Description | Band Gap Acknowledgment
Type | RO

Bits | Field Name | Description | Type | Reset
31:1 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0000 0000
0 | ACK | Acknowledgment of AUX_SCE band gap reference request. 0: Band gap request given in BGAPREQ.REQ is not captured by AON domain. State of band gap is given by system state 1: Band gap request given in BGAPREQ.REQ is captured by AON domain. Band gap is enabled | RO | 0

### TOP:AUX_WUC:WUEVFLAGS

Address offset | 0x0000 0028
Physical address | 0x400C 6028 | Instance | AUX_WUC
Description | Wake-up Event Flags Status of wake-up events from the AON domain The event flags are cleared by setting the corresponding bits in WUEVCLR
Type | RO

Bits | Field Name | Description | Type | Reset
31:3 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0000 0000
2 | AON_RTC_CH2 | Indicates pending event from AON_RTC_CH2 compare. Note that this flag will be set whenever the AON_RTC_CH2 event happens, but that does not mean that this event is a wake-up event. To make the AON_RTC_CH2 a wake-up event for the AUX domain configure it as a wake-up event in AON_EVENT:AUXWUSEL.WU0_EV, AON_EVENT:AUXWUSEL.WU1_EV or AON_EVENT:AUXWUSEL.WU2_EV. | RO | 0
1 | AON_SW | Indicates pending event triggered by system CPU writing a 1 to AON_WUC:AUXCTL.SWEV. | RO | 0
0 | AON_PROG_WU | Indicates pending event triggered by the sources selected in AON_EVENT:AUXWUSEL.WU0_EV, AON_EVENT:AUXWUSEL.WU1_EV and AON_EVENT:AUXWUSEL.WU2_EV. | RO | 0

### TOP:AUX_WUC:WUEVCLR

Address offset | 0x0000 002C
Physical address | 0x400C 602C | Instance | AUX_WUC
Description | Wake-up Event Clear Clears wake-up events from the AON domain
Type | RW

Bits | Field Name | Description | Type | Reset
31:3 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0000 0000
2 | AON_RTC_CH2 | Set to clear the WUEVFLAGS.AON_RTC_CH2 wake-up event. Note that if RTC channel 2 is also set as source for AON_PROG_WU this field can also clear WUEVFLAGS.AON_PROG_WU This bit must remain set until WUEVFLAGS.AON_RTC_CH2 returns to 0. | RW | 0
1 | AON_SW | Set to clear the WUEVFLAGS.AON_SW wake-up event. This bit must remain set until WUEVFLAGS.AON_SW returns to 0. | RW | 0
0 | AON_PROG_WU | Set to clear the WUEVFLAGS.AON_PROG_WU wake-up event. Note only if an IO event is selected as wake-up event, is it possible to use this field to clear the source. Other sources cannot be cleared using this field. The IO pin needs to be assigned to AUX in the IOC and the input enable for the pin needs to be set in AIODIO0 or AIODIO1 for this clearing to take effect. This bit must remain set until WUEVFLAGS.AON_PROG_WU returns to 0. | RW | 0

### TOP:AUX_WUC:ADCCLKCTL

Address offset | 0x0000 0030
Physical address | 0x400C 6030 | Instance | AUX_WUC
Description | ADC Clock Control Controls the ADC internal clock Note that the ADC command and data interface requires MODCLKEN0.SOC or MODCLKEN1.SOC also to be set
Type | RW

Bits | Field Name | Description | Type | Reset
31:2 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0000 0000
1 | ACK | Acknowledges the last value written to REQ. | RO | 0
0 | REQ | Enables(1) or disables (0) the ADC internal clock. This bit must not be modified unless ACK matches the current value. | RW | 0

### TOP:AUX_WUC:TDCCLKCTL

Address offset | 0x0000 0034
Physical address | 0x400C 6034 | Instance | AUX_WUC
Description | TDC Clock Control Controls the TDC counter clock source, which steps the TDC counter value The source of this clock is controlled by OSC_DIG:CTL0.ACLK_TDC_SRC_SEL.
Type | RW

Bits | Field Name | Description | Type | Reset
31:2 | RESERVED | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0000 0000
1 | ACK | Acknowledges the last value written to REQ. | RO | 0
0 | REQ | Enables(1) or disables (0) the TDC counter clock source. This bit must not be modified unless ACK matches the current value. | RW | 0

### TOP:AUX_WUC:REFCLKCTL

Address offset | 0x0000 0038
Physical address | 0x400C 6038 | Instance | AUX_WUC
Description | Reference Clock Control Controls the TDC reference clock source, which is to be compared against the TDC counter clock. The source of this clock is controlled by OSC_DIG:CTL0.ACLK_REF_SRC_SEL.
Type | RW

Bits | Field Name | Description | Type | Reset
31:2 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0000 0000
1 | ACK | Acknowledges the last value written to REQ. | RO | 0
0 | REQ | Enables(1) or disables (0) the TDC reference clock source. This bit must not be modified unless ACK matches the current value. | RW | 0

### TOP:AUX_WUC:RTCSUBSECINC0

Address offset | 0x0000 003C
Physical address | 0x400C 603C | Instance | AUX_WUC
Description | Real Time Counter Sub Second Increment 0 New value for the real-time counter (AON_RTC) sub-second increment value, part corresponding to AON_RTC:SUBSECINC bits 15:0. After setting INC15_0 and RTCSUBSECINC1.INC23_16, the value is loaded into AON_RTC:SUBSECINC.VALUEINC by setting RTCSUBSECINCCTL.UPD_REQ.
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0000
15:0 | INC15_0 | Bits 15:0 of the RTC sub-second increment value. | RW | 0x0000

### TOP:AUX_WUC:RTCSUBSECINC1

Address offset | 0x0000 0040
Physical address | 0x400C 6040 | Instance | AUX_WUC
Description | Real Time Counter Sub Second Increment 1 New value for the real-time counter (AON_RTC) sub-second increment value, part corresponding to AON_RTC:SUBSECINC bits 23:16. After setting RTCSUBSECINC0.INC15_0 and INC23_16, the value is loaded into AON_RTC:SUBSECINC.VALUEINC by setting RTCSUBSECINCCTL.UPD_REQ.
Type | RW

Bits | Field Name | Description | Type | Reset
31:8 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x00 0000
7:0 | INC23_16 | Bits 23:16 of the RTC sub-second increment value. | RW | 0x00

### TOP:AUX_WUC:RTCSUBSECINCCTL

Address offset | 0x0000 0044
Physical address | 0x400C 6044 | Instance | AUX_WUC
Description | Real Time Counter Sub Second Increment Control
Type | RW

Bits | Field Name | Description | Type | Reset
31:2 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0000 0000
1 | UPD_ACK | Acknowledgment of the UPD_REQ. | RO | 0
0 | UPD_REQ | Signal that a new real time counter sub second increment value is available 0: New sub second increment is not available 1: New sub second increment is available This bit must not be modified unless UPD_ACK matches the current value. | RW | 0

### TOP:AUX_WUC:MCUBUSCTL

Address offset | 0x0000 0048
Physical address | 0x400C 6048 | Instance | AUX_WUC
Description | MCU Bus Control Controls the connection between the AUX domain bus and the MCU domain bus. The buses must be disconnected to allow power-down or power-off of the AUX domain.
Type | RW

Bits | Field Name | Description | Type | Reset
31:1 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0000 0000
0 | DISCONNECT_REQ | Requests the AUX domain bus to be disconnected from the MCU domain bus. The request has no effect when AON_WUC:AUX_CTL.AUX_FORCE_ON is set. The disconnection status can be monitored through MCUBUSSTAT. Note however that this register cannot be read by the system CPU while disconnected. It is recommended that this bit is set and remains set after initial power-up, and that the system CPU uses AON_WUC:AUX_CTL.AUX_FORCE_ON to connect/disconnect the bus. | RW | 0

### TOP:AUX_WUC:MCUBUSSTAT

Address offset | 0x0000 004C
Physical address | 0x400C 604C | Instance | AUX_WUC
Description | MCU Bus Status Indicates the connection state of the AUX domain and MCU domain buses. Note that this register cannot be read from the MCU domain while disconnected, and is therefore only useful for the AUX_SCE.
Type | RO

Bits | Field Name | Description | Type | Reset
31:2 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0000 0000
1 | DISCONNECTED | Indicates whether the AUX domain and MCU domain buses are currently disconnected (1) or connected (0). | RO | 0
0 | DISCONNECT_ACK | Acknowledges reception of the bus disconnection request, by matching the value of MCUBUSCTL.DISCONNECT_REQ. Note that if AON_WUC:AUXCTL.AUX_FORCE_ON = 1 a reconnect to the MCU domain bus will be made regardless of the state of MCUBUSCTL.DISCONNECT_REQ | RO | 0

### TOP:AUX_WUC:AONCTLSTAT

Address offset | 0x0000 0050
Physical address | 0x400C 6050 | Instance | AUX_WUC
Description | AON Domain Control Status Status of AUX domain control from AON_WUC.
Type | RO

Bits | Field Name | Description | Type | Reset
31:2 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0000 0000
1 | AUX_FORCE_ON | Status of AON_WUC:AUX_CTL.AUX_FORCE_ON. | RO | 0
0 | SCE_RUN_EN | Status of AON_WUC:AUX_CTL.SCE_RUN_EN. | RO | 0

### TOP:AUX_WUC:AUXIOLATCH

Address offset | 0x0000 0054
Physical address | 0x400C 6054 | Instance | AUX_WUC
Description | AUX Input Output Latch Controls latching of signals between AUX_AIODIO0/AUX_AIODIO1 and AON_IOC.
Type | RW

Bits | Field Name | Description | Type | Reset
31:1 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0000 0000
0 | EN | Opens (1) or closes (0) the AUX_AIODIO0/AUX_AIODIO1 signal latching. At startup, set EN = TRANSP before configuring AUX_AIODIO0/AUX_AIODIO1 and subsequently selecting AUX mode in the AON_IOC. When powering off the AUX domain (using PWROFFREQ.REQ), set EN = STATIC in advance preserve the current state (mode and output value) of the I/O pins.
Value | ENUM name | Description
0 | STATIC | Latches are static ( closed )
1 | TRANSP | Latches are transparent ( open )
| RW | 0

### TOP:AUX_WUC:MODCLKEN1

Address offset | 0x0000 005C
Physical address | 0x400C 605C | Instance | AUX_WUC
Description | Module Clock Enable 1 Clock enable for each module in the AUX domain, for use by the AUX_SCE. Settings take effect immediately. The settings in this register are OR'ed with the corresponding settings in MODCLKEN0. This allows system CPU and AUX_SCE to request clocks independently.
Type | RW

Bits | Field Name | Description | Type | Reset
31:8 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x00 0000
7 | AUX_ADI4 | Enables (1) or disables (0) clock for AUX_ADI4.
Value | ENUM name | Description
0 | DIS | AUX_SCE has not requested clock for AUX_ADI4
1 | EN | AUX_SCE has requested clock for AUX_ADI4
| RW | 0
6 | AUX_DDI0_OSC | Enables (1) or disables (0) clock for AUX_DDI0_OSC.
Value | ENUM name | Description
0 | DIS | AUX_SCE has not requested clock for AUX_DDI0_OSC
1 | EN | AUX_SCE has requested clock for AUX_DDI0_OSC
| RW | 0
5 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text) | RW | 0
4 | SOC | Enables (1) or disables (0) clock for AUX_SOC.
Value | ENUM name | Description
0 | DIS | AUX_SCE has not requested clock for SOC
1 | EN | AUX_SCE has requested clock for SOC
| RW | 0
3 | TIMER | Enables (1) or disables (0) clock for AUX_TIMER.
Value | ENUM name | Description
0 | DIS | AUX_SCE has not requested clock for TIMER
1 | EN | AUX_SCE has requested clock for TIMER
| RW | 0
2 | AIODIO1 | Enables (1) or disables (0) clock for AUX_AIODIO1.
Value | ENUM name | Description
0 | DIS | AUX_SCE has not requested clock for AIODIO1
1 | EN | AUX_SCE has requested clock for AIODIO1
| RW | 0
1 | AIODIO0 | Enables (1) or disables (0) clock for AUX_AIODIO0.
Value | ENUM name | Description
0 | DIS | AUX_SCE has not requested clock for AIODIO0
1 | EN | AUX_SCE has requested clock for AIODIO0
| RW | 0
0 | SMPH | Enables (1) or disables (0) clock for AUX_SMPH.
Value | ENUM name | Description
0 | DIS | AUX_SCE has not requested clock for SMPH
1 | EN | AUX_SCE has requested clock for SMPH
| RW | 0