## CPU_DWT

Instance: CPU_DWT
Component: CPU_DWT
Base address: 0xe0001000

Cortex-M's Data watchpoint and Trace (DWT)

### TOP:CPU_DWT Register Summary

Register Name | Type | Register Width (Bits) | Register Reset | Address Offset | Physical Address
CTRL | RW | 32 | 0x4000 0000 | 0x0000 0000 | 0xE000 1000
CYCCNT | RW | 32 | 0x0000 0000 | 0x0000 0004 | 0xE000 1004
CPICNT | RW | 32 | 0x0000 0000 | 0x0000 0008 | 0xE000 1008
EXCCNT | RW | 32 | 0x0000 0000 | 0x0000 000C | 0xE000 100C
SLEEPCNT | RW | 32 | 0x0000 0000 | 0x0000 0010 | 0xE000 1010
LSUCNT | RW | 32 | 0x0000 0000 | 0x0000 0014 | 0xE000 1014
FOLDCNT | RW | 32 | 0x0000 0000 | 0x0000 0018 | 0xE000 1018
PCSR | RO | 32 | 0x0000 0000 | 0x0000 001C | 0xE000 101C
COMP0 | RW | 32 | 0x0000 0000 | 0x0000 0020 | 0xE000 1020
MASK0 | RW | 32 | 0x0000 0000 | 0x0000 0024 | 0xE000 1024
FUNCTION0 | RW | 32 | 0x0000 0000 | 0x0000 0028 | 0xE000 1028
COMP1 | RW | 32 | 0x0000 0000 | 0x0000 0030 | 0xE000 1030
MASK1 | RW | 32 | 0x0000 0000 | 0x0000 0034 | 0xE000 1034
FUNCTION1 | RW | 32 | 0x0000 0200 | 0x0000 0038 | 0xE000 1038
COMP2 | RW | 32 | 0x0000 0000 | 0x0000 0040 | 0xE000 1040
MASK2 | RW | 32 | 0x0000 0000 | 0x0000 0044 | 0xE000 1044
FUNCTION2 | RW | 32 | 0x0000 0000 | 0x0000 0048 | 0xE000 1048
COMP3 | RW | 32 | 0x0000 0000 | 0x0000 0050 | 0xE000 1050
MASK3 | RW | 32 | 0x0000 0000 | 0x0000 0054 | 0xE000 1054
FUNCTION3 | RW | 32 | 0x0000 0000 | 0x0000 0058 | 0xE000 1058

### TOP:CPU_DWT Register Descriptions

### TOP:CPU_DWT:CTRL

Address offset | 0x0000 0000
Physical address | 0xE000 1000 | Instance | CPU_DWT
Description | DWT Control Register Use the DWT Control Register to enable the DWT unit.
Type | RW

Bits | Field Name | Description | Type | Reset
31:26 | RESERVED26 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RW | 0x10
25 | NOCYCCNT | When set, CYCCNT is not supported. | RW | 0
24 | NOPRFCNT | When set, FOLDCNT, LSUCNT, SLEEPCNT, EXCCNT, and CPICNT are not supported. | RW | 0
23 | RESERVED23 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RW | 0
22 | CYCEVTENA | Enables Cycle count event. Emits an event when the POSTCNT counter triggers it. See CYCTAP and POSTPRESET for details. This event is only emitted if PCSAMPLEENA is disabled. PCSAMPLEENA overrides the setting of this bit. 0: Cycle count events disabled 1: Cycle count events enabled | RW | 0
21 | FOLDEVTENA | Enables Folded instruction count event. Emits an event when FOLDCNT overflows (every 256 cycles of folded instructions). A folded instruction is one that does not incur even one cycle to execute. For example, an IT instruction is folded away and so does not use up one cycle. 0: Folded instruction count events disabled. 1: Folded instruction count events enabled. | RW | 0
20 | LSUEVTENA | Enables LSU count event. Emits an event when LSUCNT overflows (every 256 cycles of LSU operation). LSU counts include all LSU costs after the initial cycle for the instruction. 0: LSU count events disabled. 1: LSU count events enabled. | RW | 0
19 | SLEEPEVTENA | Enables Sleep count event. Emits an event when SLEEPCNT overflows (every 256 cycles that the processor is sleeping). 0: Sleep count events disabled. 1: Sleep count events enabled. | RW | 0
18 | EXCEVTENA | Enables Interrupt overhead event. Emits an event when EXCCNT overflows (every 256 cycles of interrupt overhead). 0x0: Interrupt overhead event disabled. 0x1: Interrupt overhead event enabled. | RW | 0
17 | CPIEVTENA | Enables CPI count event. Emits an event when CPICNT overflows (every 256 cycles of multi-cycle instructions). 0: CPI counter events disabled. 1: CPI counter events enabled. | RW | 0
16 | EXCTRCENA | Enables Interrupt event tracing. 0: Interrupt event trace disabled. 1: Interrupt event trace enabled. | RW | 0
15:13 | RESERVED13 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RW | 0x0
12 | PCSAMPLEENA | Enables PC Sampling event. A PC sample event is emitted when the POSTCNT counter triggers it. See CYCTAP and POSTPRESET for details. Enabling this bit overrides CYCEVTENA. 0: PC Sampling event disabled. 1: Sampling event enabled. | RW | 0
11:10 | SYNCTAP | Selects a synchronization packet rate. CYCCNTENA and CPU_ITM:TCR.SYNCENA must also be enabled for this feature. Synchronization packets (if enabled) are generated on tap transitions (0 to1 or 1 to 0).
Value | ENUM name | Description
0x0 | DIS | Disabled. No synchronization packets
0x1 | BIT24 | Tap at bit 24 of CYCCNT
0x2 | BIT26 | Tap at bit 26 of CYCCNT
0x3 | BIT28 | Tap at bit 28 of CYCCNT
| RW | 0x0
9 | CYCTAP | Selects a tap on CYCCNT. These are spaced at bits [6] and [10]. When the selected bit in CYCCNT changes from 0 to 1 or 1 to 0, it emits into the POSTCNT, post-scalar counter. That counter then counts down. On a bit change when post-scalar is 0, it triggers an event for PC sampling or cycle count event (see details in CYCEVTENA).
Value | ENUM name | Description
0 | BIT6 | Selects bit [6] to tap
1 | BIT10 | Selects bit [10] to tap
| RW | 0
8:5 | POSTCNT | Post-scalar counter for CYCTAP. When the selected tapped bit changes from 0 to 1 or 1 to 0, the post scalar counter is down-counted when not 0. If 0, it triggers an event for PCSAMPLEENA or CYCEVTENA use. It also reloads with the value from POSTPRESET. | RW | 0x0
4:1 | POSTPRESET | Reload value for post-scalar counter POSTCNT. When 0, events are triggered on each tap change (a power of 2). If this field has a non-0 value, it forms a count-down value, to be reloaded into POSTCNT each time it reaches 0. For example, a value 1 in this register means an event is formed every other tap change. | RW | 0x0
0 | CYCCNTENA | Enable CYCCNT, allowing it to increment and generate synchronization and count events. If NOCYCCNT = 1, this bit reads zero and ignore writes. | RW | 0

### TOP:CPU_DWT:CYCCNT

Address offset | 0x0000 0004
Physical address | 0xE000 1004 | Instance | CPU_DWT
Description | DWT Current PC Sampler Cycle Count Register This register is used to count the number of core cycles. This counter can measure elapsed execution time. This is a free-running counter (this counter will not advance in power modes where free-running clock to CPU stops). The counter has three functions: 1: When CTRL.PCSAMPLEENA = 1, the PC is sampled and emitted when the selected tapped bit changes value (0 to 1 or 1 to 0) and any post-scalar value counts to 0. 2: When CTRL.CYCEVTENA = 1 , (and CTRL.PCSAMPLEENA = 0), an event is emitted when the selected tapped bit changes value (0 to 1 or 1 to 0) and any post-scalar value counts to 0. 3: Applications and debuggers can use the counter to measure elapsed execution time. By subtracting a start and an end time, an application can measure time between in-core clocks (other than when Halted in debug). This is valid to 2^32 core clock cycles (for example, almost 89.5 seconds at 48MHz).
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | CYCCNT | Current PC Sampler Cycle Counter count value. When enabled, this counter counts the number of core cycles, except when the core is halted. The cycle counter is a free running counter, counting upwards (this counter will not advance in power modes where free-running clock to CPU stops). It wraps around to 0 on overflow. The debugger must initialize this to 0 when first enabling. | RW | 0x0000 0000

### TOP:CPU_DWT:CPICNT

Address offset | 0x0000 0008
Physical address | 0xE000 1008 | Instance | CPU_DWT
Description | DWT CPI Count Register This register is used to count the total number of instruction cycles beyond the first cycle.
Type | RW

Bits | Field Name | Description | Type | Reset
31:8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RW | 0x00 0000
7:0 | CPICNT | Current CPI counter value. Increments on the additional cycles (the first cycle is not counted) required to execute all instructions except those recorded by LSUCNT. This counter also increments on all instruction fetch stalls. If CTRL.CPIEVTENA is set, an event is emitted when the counter overflows. This counter initializes to 0 when it is enabled using CTRL.CPIEVTENA. | RW | 0x00

### TOP:CPU_DWT:EXCCNT

Address offset | 0x0000 000C
Physical address | 0xE000 100C | Instance | CPU_DWT
Description | DWT Exception Overhead Count Register This register is used to count the total cycles spent in interrupt processing.
Type | RW

Bits | Field Name | Description | Type | Reset
31:8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RW | 0x00 0000
7:0 | EXCCNT | Current interrupt overhead counter value. Counts the total cycles spent in interrupt processing (for example entry stacking, return unstacking, pre-emption). An event is emitted on counter overflow (every 256 cycles). This counter initializes to 0 when it is enabled using CTRL.EXCEVTENA. | RW | 0x00

### TOP:CPU_DWT:SLEEPCNT

Address offset | 0x0000 0010
Physical address | 0xE000 1010 | Instance | CPU_DWT
Description | DWT Sleep Count Register This register is used to count the total number of cycles during which the processor is sleeping.
Type | RW

Bits | Field Name | Description | Type | Reset
31:8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RW | 0x00 0000
7:0 | SLEEPCNT | Sleep counter. Counts the number of cycles during which the processor is sleeping. An event is emitted on counter overflow (every 256 cycles). This counter initializes to 0 when it is enabled using CTRL.SLEEPEVTENA. Note that the sleep counter is clocked using CPU's free-running clock. In some power modes the free-running clock to CPU is gated to minimize power consumption. This means that the sleep counter will be invalid in these power modes. | RW | 0x00

### TOP:CPU_DWT:LSUCNT

Address offset | 0x0000 0014
Physical address | 0xE000 1014 | Instance | CPU_DWT
Description | DWT LSU Count Register This register is used to count the total number of cycles during which the processor is processing an LSU operation beyond the first cycle.
Type | RW

Bits | Field Name | Description | Type | Reset
31:8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RW | 0x00 0000
7:0 | LSUCNT | LSU counter. This counts the total number of cycles that the processor is processing an LSU operation. The initial execution cost of the instruction is not counted. For example, an LDR that takes two cycles to complete increments this counter one cycle. Equivalently, an LDR that stalls for two cycles (i.e. takes four cycles to execute), increments this counter three times. An event is emitted on counter overflow (every 256 cycles). This counter initializes to 0 when it is enabled using CTRL.LSUEVTENA. | RW | 0x00

### TOP:CPU_DWT:FOLDCNT

Address offset | 0x0000 0018
Physical address | 0xE000 1018 | Instance | CPU_DWT
Description | DWT Fold Count Register This register is used to count the total number of folded instructions. The counter increments on each instruction which takes 0 cycles.
Type | RW

Bits | Field Name | Description | Type | Reset
31:8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RW | 0x00 0000
7:0 | FOLDCNT | This counts the total number folded instructions. This counter initializes to 0 when it is enabled using CTRL.FOLDEVTENA. | RW | 0x00

### TOP:CPU_DWT:PCSR

Address offset | 0x0000 001C
Physical address | 0xE000 101C | Instance | CPU_DWT
Description | DWT Program Counter Sample Register This register is used to enable coarse-grained software profiling using a debug agent, without changing the currently executing code. If the core is not in debug state, the value returned is the instruction address of a recently executed instruction. If the core is in debug state, the value returned is 0xFFFFFFFF.
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | EIASAMPLE | Execution instruction address sample, or 0xFFFFFFFF if the core is halted. | RO | 0x0000 0000

### TOP:CPU_DWT:COMP0

Address offset | 0x0000 0020
Physical address | 0xE000 1020 | Instance | CPU_DWT
Description | DWT Comparator Register 0 This register is used to write the reference value for comparator 0.
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | COMP | Reference value to compare against PC or the data address as given by FUNCTION0. Comparator 0 can also compare against the value of the PC Sampler Counter (CYCCNT). | RW | 0x0000 0000

### TOP:CPU_DWT:MASK0

Address offset | 0x0000 0024
Physical address | 0xE000 1024 | Instance | CPU_DWT
Description | DWT Mask Register 0 Use the DWT Mask Registers 0 to apply a mask to data addresses when matching against COMP0.
Type | RW

Bits | Field Name | Description | Type | Reset
31:4 | RESERVED4 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RW | 0x000 0000
3:0 | MASK | Mask on data address when matching against COMP0. This is the size of the ignore mask. That is, DWT matching is performed as:(ADDR ANDed with (0xFFFF left bit-shifted by MASK)) == COMP0. However, the actual comparison is slightly more complex to enable matching an address wherever it appears on a bus. So, if COMP0 is 3, this matches a word access of 0, because 3 would be within the word. | RW | 0x0

### TOP:CPU_DWT:FUNCTION0

Address offset | 0x0000 0028
Physical address | 0xE000 1028 | Instance | CPU_DWT
Description | DWT Function Register 0 Use the DWT Function Registers 0 to control the operation of the comparator 0. This comparator can: 1. Match against either the PC or the data address. This is controlled by CYCMATCH. This function is only available for comparator 0 (COMP0). 2. Emit data or PC couples, trigger the ETM, or generate a watchpoint depending on the operation defined by FUNCTION.
Type | RW

Bits | Field Name | Description | Type | Reset
31:25 | RESERVED25 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00
24 | MATCHED | This bit is set when the comparator matches, and indicates that the operation defined by FUNCTION has occurred since this bit was last read. This bit is cleared on read. | RW | 0
23:8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0000
7 | CYCMATCH | This bit is only available in comparator 0. When set, COMP0 will compare against the cycle counter (CYCCNT). | RW | 0
6 | RESERVED6 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0
5 | EMITRANGE | Emit range field. This bit permits emitting offset when range match occurs. PC sampling is not supported when emit range is enabled. This field only applies for: FUNCTION = 1, 2, 3, 12, 13, 14, and 15. | RW | 0
4 | RESERVED4 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0
3:0 | FUNCTION | Function settings. 0x0: Disabled 0x1: EMITRANGE = 0, sample and emit PC through ITM. EMITRANGE = 1, emit address offset through ITM 0x2: EMITRANGE = 0, emit data through ITM on read and write. EMITRANGE = 1, emit data and address offset through ITM on read or write. 0x3: EMITRANGE = 0, sample PC and data value through ITM on read or write. EMITRANGE = 1, emit address offset and data value through ITM on read or write. 0x4: Watchpoint on PC match. 0x5: Watchpoint on read. 0x6: Watchpoint on write. 0x7: Watchpoint on read or write. 0x8: ETM trigger on PC match 0x9: ETM trigger on read 0xA: ETM trigger on write 0xB: ETM trigger on read or write 0xC: EMITRANGE = 0, sample data for read transfers. EMITRANGE = 1, sample Daddr (lower 16 bits) for read transfers 0xD: EMITRANGE = 0, sample data for write transfers. EMITRANGE = 1, sample Daddr (lower 16 bits) for write transfers 0xE: EMITRANGE = 0, sample PC + data for read transfers. EMITRANGE = 1, sample Daddr (lower 16 bits) + data for read transfers 0xF: EMITRANGE = 0, sample PC + data for write transfers. EMITRANGE = 1, sample Daddr (lower 16 bits) + data for write transfers Note 1: If the ETM is not fitted, then ETM trigger is not possible. Note 2: Data value is only sampled for accesses that do not fault (MPU or bus fault). The PC is sampled irrespective of any faults. The PC is only sampled for the first address of a burst. Note 3: PC match is not recommended for watchpoints because it stops after the instruction. It mainly guards and triggers the ETM. | RW | 0x0

### TOP:CPU_DWT:COMP1

Address offset | 0x0000 0030
Physical address | 0xE000 1030 | Instance | CPU_DWT
Description | DWT Comparator Register 1 This register is used to write the reference value for comparator 1.
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | COMP | Reference value to compare against PC or the data address as given by FUNCTION1. Comparator 1 can also compare data values. So this register can contain reference values for data matching. | RW | 0x0000 0000

### TOP:CPU_DWT:MASK1

Address offset | 0x0000 0034
Physical address | 0xE000 1034 | Instance | CPU_DWT
Description | DWT Mask Register 1 Use the DWT Mask Registers 1 to apply a mask to data addresses when matching against COMP1.
Type | RW

Bits | Field Name | Description | Type | Reset
31:4 | RESERVED4 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RW | 0x000 0000
3:0 | MASK | Mask on data address when matching against COMP1. This is the size of the ignore mask. That is, DWT matching is performed as:(ADDR ANDed with (0xFFFF left bit-shifted by MASK)) == COMP1. However, the actual comparison is slightly more complex to enable matching an address wherever it appears on a bus. So, if COMP1 is 3, this matches a word access of 0, because 3 would be within the word. | RW | 0x0

### TOP:CPU_DWT:FUNCTION1

Address offset | 0x0000 0038
Physical address | 0xE000 1038 | Instance | CPU_DWT
Description | DWT Function Register 1 Use the DWT Function Registers 1 to control the operation of the comparator 1. This comparator can: 1. Perform data value comparisons if associated address comparators have performed an address match. This function is only available for comparator 1 (COMP1). 2. Emit data or PC couples, trigger the ETM, or generate a watchpoint depending on the operation defined by FUNCTION.
Type | RW

Bits | Field Name | Description | Type | Reset
31:25 | RESERVED25 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00
24 | MATCHED | This bit is set when the comparator matches, and indicates that the operation defined by FUNCTION has occurred since this bit was last read. This bit is cleared on read. | RW | 0
23:20 | RESERVED20 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0
19:16 | DATAVADDR1 | Identity of a second linked address comparator for data value matching when DATAVMATCH == 1 and LNK1ENA == 1. | RW | 0x0
15:12 | DATAVADDR0 | Identity of a linked address comparator for data value matching when DATAVMATCH == 1. | RW | 0x0
11:10 | DATAVSIZE | Defines the size of the data in the COMP1 register that is to be matched: 0x0: Byte 0x1: Halfword 0x2: Word 0x3: Unpredictable. | RW | 0x0
9 | LNK1ENA | Read only bit-field only supported in comparator 1. 0: DATAVADDR1 not supported 1: DATAVADDR1 supported (enabled) | RO | 1
8 | DATAVMATCH | Data match feature: 0: Perform address comparison 1: Perform data value compare. The comparators given by DATAVADDR0 and DATAVADDR1 provide the address for the data comparison. The FUNCTION setting for the comparators given by DATAVADDR0 and DATAVADDR1 are overridden and those comparators only provide the address match for the data comparison. This bit is only available in comparator 1. | RW | 0
7:6 | RESERVED6 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0
5 | EMITRANGE | Emit range field. This bit permits emitting offset when range match occurs. PC sampling is not supported when emit range is enabled. This field only applies for: FUNCTION = 1, 2, 3, 12, 13, 14, and 15. | RW | 0
4 | RESERVED4 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0
3:0 | FUNCTION | Function settings: 0x0: Disabled 0x1: EMITRANGE = 0, sample and emit PC through ITM. EMITRANGE = 1, emit address offset through ITM 0x2: EMITRANGE = 0, emit data through ITM on read and write. EMITRANGE = 1, emit data and address offset through ITM on read or write. 0x3: EMITRANGE = 0, sample PC and data value through ITM on read or write. EMITRANGE = 1, emit address offset and data value through ITM on read or write. 0x4: Watchpoint on PC match. 0x5: Watchpoint on read. 0x6: Watchpoint on write. 0x7: Watchpoint on read or write. 0x8: ETM trigger on PC match 0x9: ETM trigger on read 0xA: ETM trigger on write 0xB: ETM trigger on read or write 0xC: EMITRANGE = 0, sample data for read transfers. EMITRANGE = 1, sample Daddr (lower 16 bits) for read transfers 0xD: EMITRANGE = 0, sample data for write transfers. EMITRANGE = 1, sample Daddr (lower 16 bits) for write transfers 0xE: EMITRANGE = 0, sample PC + data for read transfers. EMITRANGE = 1, sample Daddr (lower 16 bits) + data for read transfers 0xF: EMITRANGE = 0, sample PC + data for write transfers. EMITRANGE = 1, sample Daddr (lower 16 bits) + data for write transfers Note 1: If the ETM is not fitted, then ETM trigger is not possible. Note 2: Data value is only sampled for accesses that do not fault (MPU or bus fault). The PC is sampled irrespective of any faults. The PC is only sampled for the first address of a burst. Note 3: FUNCTION is overridden for comparators given by DATAVADDR0 and DATAVADDR1 if DATAVMATCH is also set. The comparators given by DATAVADDR0 and DATAVADDR1 can then only perform address comparator matches for comparator 1 data matches. Note 4: If the data matching functionality is not included during implementation it is not possible to set DATAVADDR0, DATAVADDR1, or DATAVMATCH. This means that the data matching functionality is not available in the implementation. Test the availability of data matching by writing and reading DATAVMATCH. If it is not settable then data matching is unavailable. Note 5: PC match is not recommended for watchpoints because it stops after the instruction. It mainly guards and triggers the ETM. | RW | 0x0

### TOP:CPU_DWT:COMP2

Address offset | 0x0000 0040
Physical address | 0xE000 1040 | Instance | CPU_DWT
Description | DWT Comparator Register 2 This register is used to write the reference value for comparator 2.
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | COMP | Reference value to compare against PC or the data address as given by FUNCTION2. | RW | 0x0000 0000

### TOP:CPU_DWT:MASK2

Address offset | 0x0000 0044
Physical address | 0xE000 1044 | Instance | CPU_DWT
Description | DWT Mask Register 2 Use the DWT Mask Registers 2 to apply a mask to data addresses when matching against COMP2.
Type | RW

Bits | Field Name | Description | Type | Reset
31:4 | RESERVED4 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RW | 0x000 0000
3:0 | MASK | Mask on data address when matching against COMP2. This is the size of the ignore mask. That is, DWT matching is performed as:(ADDR ANDed with (0xFFFF left bit-shifted by MASK)) == COMP2. However, the actual comparison is slightly more complex to enable matching an address wherever it appears on a bus. So, if COMP2 is 3, this matches a word access of 0, because 3 would be within the word. | RW | 0x0

### TOP:CPU_DWT:FUNCTION2

Address offset | 0x0000 0048
Physical address | 0xE000 1048 | Instance | CPU_DWT
Description | DWT Function Register 2 Use the DWT Function Registers 2 to control the operation of the comparator 2. This comparator can emit data or PC couples, trigger the ETM, or generate a watchpoint depending on the operation defined by FUNCTION.
Type | RW

Bits | Field Name | Description | Type | Reset
31:25 | RESERVED25 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RW | 0x00
24 | MATCHED | This bit is set when the comparator matches, and indicates that the operation defined by FUNCTION has occurred since this bit was last read. This bit is cleared on read. | RW | 0
23:6 | RESERVED6 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0 0000
5 | EMITRANGE | Emit range field. This bit permits emitting offset when range match occurs. PC sampling is not supported when emit range is enabled. This field only applies for: FUNCTION = 1, 2, 3, 12, 13, 14, and 15. | RW | 0
4 | RESERVED4 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0
3:0 | FUNCTION | Function settings. 0x0: Disabled 0x1: EMITRANGE = 0, sample and emit PC through ITM. EMITRANGE = 1, emit address offset through ITM 0x2: EMITRANGE = 0, emit data through ITM on read and write. EMITRANGE = 1, emit data and address offset through ITM on read or write. 0x3: EMITRANGE = 0, sample PC and data value through ITM on read or write. EMITRANGE = 1, emit address offset and data value through ITM on read or write. 0x4: Watchpoint on PC match. 0x5: Watchpoint on read. 0x6: Watchpoint on write. 0x7: Watchpoint on read or write. 0x8: ETM trigger on PC match 0x9: ETM trigger on read 0xA: ETM trigger on write 0xB: ETM trigger on read or write 0xC: EMITRANGE = 0, sample data for read transfers. EMITRANGE = 1, sample Daddr (lower 16 bits) for read transfers 0xD: EMITRANGE = 0, sample data for write transfers. EMITRANGE = 1, sample Daddr (lower 16 bits) for write transfers 0xE: EMITRANGE = 0, sample PC + data for read transfers. EMITRANGE = 1, sample Daddr (lower 16 bits) + data for read transfers 0xF: EMITRANGE = 0, sample PC + data for write transfers. EMITRANGE = 1, sample Daddr (lower 16 bits) + data for write transfers Note 1: If the ETM is not fitted, then ETM trigger is not possible. Note 2: Data value is only sampled for accesses that do not fault (MPU or bus fault). The PC is sampled irrespective of any faults. The PC is only sampled for the first address of a burst. Note 3: PC match is not recommended for watchpoints because it stops after the instruction. It mainly guards and triggers the ETM. | RW | 0x0

### TOP:CPU_DWT:COMP3

Address offset | 0x0000 0050
Physical address | 0xE000 1050 | Instance | CPU_DWT
Description | DWT Comparator Register 3 This register is used to write the reference value for comparator 3.
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | COMP | Reference value to compare against PC or the data address as given by FUNCTION3. | RW | 0x0000 0000

### TOP:CPU_DWT:MASK3

Address offset | 0x0000 0054
Physical address | 0xE000 1054 | Instance | CPU_DWT
Description | DWT Mask Register 3 Use the DWT Mask Registers 3 to apply a mask to data addresses when matching against COMP3.
Type | RW

Bits | Field Name | Description | Type | Reset
31:4 | RESERVED4 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RW | 0x000 0000
3:0 | MASK | Mask on data address when matching against COMP3. This is the size of the ignore mask. That is, DWT matching is performed as:(ADDR ANDed with (0xFFFF left bit-shifted by MASK)) == COMP3. However, the actual comparison is slightly more complex to enable matching an address wherever it appears on a bus. So, if COMP3 is 3, this matches a word access of 0, because 3 would be within the word. | RW | 0x0

### TOP:CPU_DWT:FUNCTION3

Address offset | 0x0000 0058
Physical address | 0xE000 1058 | Instance | CPU_DWT
Description | DWT Function Register 3 Use the DWT Function Registers 3 to control the operation of the comparator 3. This comparator can emit data or PC couples, trigger the ETM, or generate a watchpoint depending on the operation defined by FUNCTION.
Type | RW

Bits | Field Name | Description | Type | Reset
31:25 | RESERVED25 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RW | 0x00
24 | MATCHED | This bit is set when the comparator matches, and indicates that the operation defined by FUNCTION has occurred since this bit was last read. This bit is cleared on read. | RW | 0
23:6 | RESERVED6 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RW | 0x0 0000
5 | EMITRANGE | Emit range field. This bit permits emitting offset when range match occurs. PC sampling is not supported when emit range is enabled. This field only applies for: FUNCTION = 1, 2, 3, 12, 13, 14, and 15. | RW | 0
4 | RESERVED4 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RW | 0
3:0 | FUNCTION | Function settings. 0x0: Disabled 0x1: EMITRANGE = 0, sample and emit PC through ITM. EMITRANGE = 1, emit address offset through ITM 0x2: EMITRANGE = 0, emit data through ITM on read and write. EMITRANGE = 1, emit data and address offset through ITM on read or write. 0x3: EMITRANGE = 0, sample PC and data value through ITM on read or write. EMITRANGE = 1, emit address offset and data value through ITM on read or write. 0x4: Watchpoint on PC match. 0x5: Watchpoint on read. 0x6: Watchpoint on write. 0x7: Watchpoint on read or write. 0x8: ETM trigger on PC match 0x9: ETM trigger on read 0xA: ETM trigger on write 0xB: ETM trigger on read or write 0xC: EMITRANGE = 0, sample data for read transfers. EMITRANGE = 1, sample Daddr (lower 16 bits) for read transfers 0xD: EMITRANGE = 0, sample data for write transfers. EMITRANGE = 1, sample Daddr (lower 16 bits) for write transfers 0xE: EMITRANGE = 0, sample PC + data for read transfers. EMITRANGE = 1, sample Daddr (lower 16 bits) + data for read transfers 0xF: EMITRANGE = 0, sample PC + data for write transfers. EMITRANGE = 1, sample Daddr (lower 16 bits) + data for write transfers Note 1: If the ETM is not fitted, then ETM trigger is not possible. Note 2: Data value is only sampled for accesses that do not fault (MPU or bus fault). The PC is sampled irrespective of any faults. The PC is only sampled for the first address of a burst. Note 3: PC match is not recommended for watchpoints because it stops after the instruction. It mainly guards and triggers the ETM. | RW | 0x0