## CPU_ITM

Instance: CPU_ITM
Component: CPU_ITM
Base address: 0xe0000000

Cortex-M's Instrumentation Trace Macrocell (ITM)

### TOP:CPU_ITM Register Summary

Register Name | Type | Register Width (Bits) | Register Reset | Address Offset | Physical Address
STIM0 | RW | 32 | 0x0000 0000 | 0x0000 0000 | 0xE000 0000
STIM1 | RW | 32 | 0x0000 0000 | 0x0000 0004 | 0xE000 0004
STIM2 | RW | 32 | 0x0000 0000 | 0x0000 0008 | 0xE000 0008
STIM3 | RW | 32 | 0x0000 0000 | 0x0000 000C | 0xE000 000C
STIM4 | RW | 32 | 0x0000 0000 | 0x0000 0010 | 0xE000 0010
STIM5 | RW | 32 | 0x0000 0000 | 0x0000 0014 | 0xE000 0014
STIM6 | RW | 32 | 0x0000 0000 | 0x0000 0018 | 0xE000 0018
STIM7 | RW | 32 | 0x0000 0000 | 0x0000 001C | 0xE000 001C
STIM8 | RW | 32 | 0x0000 0000 | 0x0000 0020 | 0xE000 0020
STIM9 | RW | 32 | 0x0000 0000 | 0x0000 0024 | 0xE000 0024
STIM10 | RW | 32 | 0x0000 0000 | 0x0000 0028 | 0xE000 0028
STIM11 | RW | 32 | 0x0000 0000 | 0x0000 002C | 0xE000 002C
STIM12 | RW | 32 | 0x0000 0000 | 0x0000 0030 | 0xE000 0030
STIM13 | RW | 32 | 0x0000 0000 | 0x0000 0034 | 0xE000 0034
STIM14 | RW | 32 | 0x0000 0000 | 0x0000 0038 | 0xE000 0038
STIM15 | RW | 32 | 0x0000 0000 | 0x0000 003C | 0xE000 003C
STIM16 | RW | 32 | 0x0000 0000 | 0x0000 0040 | 0xE000 0040
STIM17 | RW | 32 | 0x0000 0000 | 0x0000 0044 | 0xE000 0044
STIM18 | RW | 32 | 0x0000 0000 | 0x0000 0048 | 0xE000 0048
STIM19 | RW | 32 | 0x0000 0000 | 0x0000 004C | 0xE000 004C
STIM20 | RW | 32 | 0x0000 0000 | 0x0000 0050 | 0xE000 0050
STIM21 | RW | 32 | 0x0000 0000 | 0x0000 0054 | 0xE000 0054
STIM22 | RW | 32 | 0x0000 0000 | 0x0000 0058 | 0xE000 0058
STIM23 | RW | 32 | 0x0000 0000 | 0x0000 005C | 0xE000 005C
STIM24 | RW | 32 | 0x0000 0000 | 0x0000 0060 | 0xE000 0060
STIM25 | RW | 32 | 0x0000 0000 | 0x0000 0064 | 0xE000 0064
STIM26 | RW | 32 | 0x0000 0000 | 0x0000 0068 | 0xE000 0068
STIM27 | RW | 32 | 0x0000 0000 | 0x0000 006C | 0xE000 006C
STIM28 | RW | 32 | 0x0000 0000 | 0x0000 0070 | 0xE000 0070
STIM29 | RW | 32 | 0x0000 0000 | 0x0000 0074 | 0xE000 0074
STIM30 | RW | 32 | 0x0000 0000 | 0x0000 0078 | 0xE000 0078
STIM31 | RW | 32 | 0x0000 0000 | 0x0000 007C | 0xE000 007C
TER | RW | 32 | 0x0000 0000 | 0x0000 0E00 | 0xE000 0E00
TPR | RW | 32 | 0x0000 0000 | 0x0000 0E40 | 0xE000 0E40
TCR | RW | 32 | 0x0000 0000 | 0x0000 0E80 | 0xE000 0E80
LAR | WO | 32 | 0x0000 0000 | 0x0000 0FB0 | 0xE000 0FB0
LSR | RO | 32 | 0x0000 0003 | 0x0000 0FB4 | 0xE000 0FB4

### TOP:CPU_ITM Register Descriptions

### TOP:CPU_ITM:STIM0

Address offset | 0x0000 0000
Physical address | 0xE000 0000 | Instance | CPU_ITM
Description | ITM Stimulus Port 0
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | STIM0 | A write to this location causes data to be written into the FIFO if TER.STIMENA0 is set. Reading from the stimulus port returns the FIFO status in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not provide an atomic read-modify-write, so it's users responsibility to ensure exclusive read-modify-write if this ITM port is used concurrently by interrupts or other threads. | RW | 0x0000 0000

### TOP:CPU_ITM:STIM1

Address offset | 0x0000 0004
Physical address | 0xE000 0004 | Instance | CPU_ITM
Description | ITM Stimulus Port 1
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | STIM1 | A write to this location causes data to be written into the FIFO if TER.STIMENA1 is set. Reading from the stimulus port returns the FIFO status in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not provide an atomic read-modify-write, so it's users responsibility to ensure exclusive read-modify-write if this ITM port is used concurrently by interrupts or other threads. | RW | 0x0000 0000

### TOP:CPU_ITM:STIM2

Address offset | 0x0000 0008
Physical address | 0xE000 0008 | Instance | CPU_ITM
Description | ITM Stimulus Port 2
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | STIM2 | A write to this location causes data to be written into the FIFO if TER.STIMENA2 is set. Reading from the stimulus port returns the FIFO status in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not provide an atomic read-modify-write, so it's users responsibility to ensure exclusive read-modify-write if this ITM port is used concurrently by interrupts or other threads. | RW | 0x0000 0000

### TOP:CPU_ITM:STIM3

Address offset | 0x0000 000C
Physical address | 0xE000 000C | Instance | CPU_ITM
Description | ITM Stimulus Port 3
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | STIM3 | A write to this location causes data to be written into the FIFO if TER.STIMENA3 is set. Reading from the stimulus port returns the FIFO status in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not provide an atomic read-modify-write, so it's users responsibility to ensure exclusive read-modify-write if this ITM port is used concurrently by interrupts or other threads. | RW | 0x0000 0000

### TOP:CPU_ITM:STIM4

Address offset | 0x0000 0010
Physical address | 0xE000 0010 | Instance | CPU_ITM
Description | ITM Stimulus Port 4
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | STIM4 | A write to this location causes data to be written into the FIFO if TER.STIMENA4 is set. Reading from the stimulus port returns the FIFO status in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not provide an atomic read-modify-write, so it's users responsibility to ensure exclusive read-modify-write if this ITM port is used concurrently by interrupts or other threads. | RW | 0x0000 0000

### TOP:CPU_ITM:STIM5

Address offset | 0x0000 0014
Physical address | 0xE000 0014 | Instance | CPU_ITM
Description | ITM Stimulus Port 5
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | STIM5 | A write to this location causes data to be written into the FIFO if TER.STIMENA5 is set. Reading from the stimulus port returns the FIFO status in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not provide an atomic read-modify-write, so it's users responsibility to ensure exclusive read-modify-write if this ITM port is used concurrently by interrupts or other threads. | RW | 0x0000 0000

### TOP:CPU_ITM:STIM6

Address offset | 0x0000 0018
Physical address | 0xE000 0018 | Instance | CPU_ITM
Description | ITM Stimulus Port 6
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | STIM6 | A write to this location causes data to be written into the FIFO if TER.STIMENA6 is set. Reading from the stimulus port returns the FIFO status in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not provide an atomic read-modify-write, so it's users responsibility to ensure exclusive read-modify-write if this ITM port is used concurrently by interrupts or other threads. | RW | 0x0000 0000

### TOP:CPU_ITM:STIM7

Address offset | 0x0000 001C
Physical address | 0xE000 001C | Instance | CPU_ITM
Description | ITM Stimulus Port 7
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | STIM7 | A write to this location causes data to be written into the FIFO if TER.STIMENA7 is set. Reading from the stimulus port returns the FIFO status in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not provide an atomic read-modify-write, so it's users responsibility to ensure exclusive read-modify-write if this ITM port is used concurrently by interrupts or other threads. | RW | 0x0000 0000

### TOP:CPU_ITM:STIM8

Address offset | 0x0000 0020
Physical address | 0xE000 0020 | Instance | CPU_ITM
Description | ITM Stimulus Port 8
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | STIM8 | A write to this location causes data to be written into the FIFO if TER.STIMENA8 is set. Reading from the stimulus port returns the FIFO status in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not provide an atomic read-modify-write, so it's users responsibility to ensure exclusive read-modify-write if this ITM port is used concurrently by interrupts or other threads. | RW | 0x0000 0000

### TOP:CPU_ITM:STIM9

Address offset | 0x0000 0024
Physical address | 0xE000 0024 | Instance | CPU_ITM
Description | ITM Stimulus Port 9
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | STIM9 | A write to this location causes data to be written into the FIFO if TER.STIMENA9 is set. Reading from the stimulus port returns the FIFO status in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not provide an atomic read-modify-write, so it's users responsibility to ensure exclusive read-modify-write if this ITM port is used concurrently by interrupts or other threads. | RW | 0x0000 0000

### TOP:CPU_ITM:STIM10

Address offset | 0x0000 0028
Physical address | 0xE000 0028 | Instance | CPU_ITM
Description | ITM Stimulus Port 10
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | STIM10 | A write to this location causes data to be written into the FIFO if TER.STIMENA10 is set. Reading from the stimulus port returns the FIFO status in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not provide an atomic read-modify-write, so it's users responsibility to ensure exclusive read-modify-write if this ITM port is used concurrently by interrupts or other threads. | RW | 0x0000 0000

### TOP:CPU_ITM:STIM11

Address offset | 0x0000 002C
Physical address | 0xE000 002C | Instance | CPU_ITM
Description | ITM Stimulus Port 11
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | STIM11 | A write to this location causes data to be written into the FIFO if TER.STIMENA11 is set. Reading from the stimulus port returns the FIFO status in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not provide an atomic read-modify-write, so it's users responsibility to ensure exclusive read-modify-write if this ITM port is used concurrently by interrupts or other threads. | RW | 0x0000 0000

### TOP:CPU_ITM:STIM12

Address offset | 0x0000 0030
Physical address | 0xE000 0030 | Instance | CPU_ITM
Description | ITM Stimulus Port 12
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | STIM12 | A write to this location causes data to be written into the FIFO if TER.STIMENA12 is set. Reading from the stimulus port returns the FIFO status in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not provide an atomic read-modify-write, so it's users responsibility to ensure exclusive read-modify-write if this ITM port is used concurrently by interrupts or other threads. | RW | 0x0000 0000

### TOP:CPU_ITM:STIM13

Address offset | 0x0000 0034
Physical address | 0xE000 0034 | Instance | CPU_ITM
Description | ITM Stimulus Port 13
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | STIM13 | A write to this location causes data to be written into the FIFO if TER.STIMENA13 is set. Reading from the stimulus port returns the FIFO status in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not provide an atomic read-modify-write, so it's users responsibility to ensure exclusive read-modify-write if this ITM port is used concurrently by interrupts or other threads. | RW | 0x0000 0000

### TOP:CPU_ITM:STIM14

Address offset | 0x0000 0038
Physical address | 0xE000 0038 | Instance | CPU_ITM
Description | ITM Stimulus Port 14
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | STIM14 | A write to this location causes data to be written into the FIFO if TER.STIMENA14 is set. Reading from the stimulus port returns the FIFO status in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not provide an atomic read-modify-write, so it's users responsibility to ensure exclusive read-modify-write if this ITM port is used concurrently by interrupts or other threads. | RW | 0x0000 0000

### TOP:CPU_ITM:STIM15

Address offset | 0x0000 003C
Physical address | 0xE000 003C | Instance | CPU_ITM
Description | ITM Stimulus Port 15
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | STIM15 | A write to this location causes data to be written into the FIFO if TER.STIMENA15 is set. Reading from the stimulus port returns the FIFO status in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not provide an atomic read-modify-write, so it's users responsibility to ensure exclusive read-modify-write if this ITM port is used concurrently by interrupts or other threads. | RW | 0x0000 0000

### TOP:CPU_ITM:STIM16

Address offset | 0x0000 0040
Physical address | 0xE000 0040 | Instance | CPU_ITM
Description | ITM Stimulus Port 16
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | STIM16 | A write to this location causes data to be written into the FIFO if TER.STIMENA16 is set. Reading from the stimulus port returns the FIFO status in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not provide an atomic read-modify-write, so it's users responsibility to ensure exclusive read-modify-write if this ITM port is used concurrently by interrupts or other threads. | RW | 0x0000 0000

### TOP:CPU_ITM:STIM17

Address offset | 0x0000 0044
Physical address | 0xE000 0044 | Instance | CPU_ITM
Description | ITM Stimulus Port 17
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | STIM17 | A write to this location causes data to be written into the FIFO if TER.STIMENA17 is set. Reading from the stimulus port returns the FIFO status in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not provide an atomic read-modify-write, so it's users responsibility to ensure exclusive read-modify-write if this ITM port is used concurrently by interrupts or other threads. | RW | 0x0000 0000

### TOP:CPU_ITM:STIM18

Address offset | 0x0000 0048
Physical address | 0xE000 0048 | Instance | CPU_ITM
Description | ITM Stimulus Port 18
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | STIM18 | A write to this location causes data to be written into the FIFO if TER.STIMENA18 is set. Reading from the stimulus port returns the FIFO status in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not provide an atomic read-modify-write, so it's users responsibility to ensure exclusive read-modify-write if this ITM port is used concurrently by interrupts or other threads. | RW | 0x0000 0000

### TOP:CPU_ITM:STIM19

Address offset | 0x0000 004C
Physical address | 0xE000 004C | Instance | CPU_ITM
Description | ITM Stimulus Port 19
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | STIM19 | A write to this location causes data to be written into the FIFO if TER.STIMENA19 is set. Reading from the stimulus port returns the FIFO status in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not provide an atomic read-modify-write, so it's users responsibility to ensure exclusive read-modify-write if this ITM port is used concurrently by interrupts or other threads. | RW | 0x0000 0000

### TOP:CPU_ITM:STIM20

Address offset | 0x0000 0050
Physical address | 0xE000 0050 | Instance | CPU_ITM
Description | ITM Stimulus Port 20
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | STIM20 | A write to this location causes data to be written into the FIFO if TER.STIMENA20 is set. Reading from the stimulus port returns the FIFO status in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not provide an atomic read-modify-write, so it's users responsibility to ensure exclusive read-modify-write if this ITM port is used concurrently by interrupts or other threads. | RW | 0x0000 0000

### TOP:CPU_ITM:STIM21

Address offset | 0x0000 0054
Physical address | 0xE000 0054 | Instance | CPU_ITM
Description | ITM Stimulus Port 21
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | STIM21 | A write to this location causes data to be written into the FIFO if TER.STIMENA21 is set. Reading from the stimulus port returns the FIFO status in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not provide an atomic read-modify-write, so it's users responsibility to ensure exclusive read-modify-write if this ITM port is used concurrently by interrupts or other threads. | RW | 0x0000 0000

### TOP:CPU_ITM:STIM22

Address offset | 0x0000 0058
Physical address | 0xE000 0058 | Instance | CPU_ITM
Description | ITM Stimulus Port 22
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | STIM22 | A write to this location causes data to be written into the FIFO if TER.STIMENA22 is set. Reading from the stimulus port returns the FIFO status in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not provide an atomic read-modify-write, so it's users responsibility to ensure exclusive read-modify-write if this ITM port is used concurrently by interrupts or other threads. | RW | 0x0000 0000

### TOP:CPU_ITM:STIM23

Address offset | 0x0000 005C
Physical address | 0xE000 005C | Instance | CPU_ITM
Description | ITM Stimulus Port 23
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | STIM23 | A write to this location causes data to be written into the FIFO if TER.STIMENA23 is set. Reading from the stimulus port returns the FIFO status in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not provide an atomic read-modify-write, so it's users responsibility to ensure exclusive read-modify-write if this ITM port is used concurrently by interrupts or other threads. | RW | 0x0000 0000

### TOP:CPU_ITM:STIM24

Address offset | 0x0000 0060
Physical address | 0xE000 0060 | Instance | CPU_ITM
Description | ITM Stimulus Port 24
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | STIM24 | A write to this location causes data to be written into the FIFO if TER.STIMENA24 is set. Reading from the stimulus port returns the FIFO status in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not provide an atomic read-modify-write, so it's users responsibility to ensure exclusive read-modify-write if this ITM port is used concurrently by interrupts or other threads. | RW | 0x0000 0000

### TOP:CPU_ITM:STIM25

Address offset | 0x0000 0064
Physical address | 0xE000 0064 | Instance | CPU_ITM
Description | ITM Stimulus Port 25
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | STIM25 | A write to this location causes data to be written into the FIFO if TER.STIMENA25 is set. Reading from the stimulus port returns the FIFO status in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not provide an atomic read-modify-write, so it's users responsibility to ensure exclusive read-modify-write if this ITM port is used concurrently by interrupts or other threads. | RW | 0x0000 0000

### TOP:CPU_ITM:STIM26

Address offset | 0x0000 0068
Physical address | 0xE000 0068 | Instance | CPU_ITM
Description | ITM Stimulus Port 26
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | STIM26 | A write to this location causes data to be written into the FIFO if TER.STIMENA26 is set. Reading from the stimulus port returns the FIFO status in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not provide an atomic read-modify-write, so it's users responsibility to ensure exclusive read-modify-write if this ITM port is used concurrently by interrupts or other threads. | RW | 0x0000 0000

### TOP:CPU_ITM:STIM27

Address offset | 0x0000 006C
Physical address | 0xE000 006C | Instance | CPU_ITM
Description | ITM Stimulus Port 27
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | STIM27 | A write to this location causes data to be written into the FIFO if TER.STIMENA27 is set. Reading from the stimulus port returns the FIFO status in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not provide an atomic read-modify-write, so it's users responsibility to ensure exclusive read-modify-write if this ITM port is used concurrently by interrupts or other threads. | RW | 0x0000 0000

### TOP:CPU_ITM:STIM28

Address offset | 0x0000 0070
Physical address | 0xE000 0070 | Instance | CPU_ITM
Description | ITM Stimulus Port 28
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | STIM28 | A write to this location causes data to be written into the FIFO if TER.STIMENA28 is set. Reading from the stimulus port returns the FIFO status in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not provide an atomic read-modify-write, so it's users responsibility to ensure exclusive read-modify-write if this ITM port is used concurrently by interrupts or other threads. | RW | 0x0000 0000

### TOP:CPU_ITM:STIM29

Address offset | 0x0000 0074
Physical address | 0xE000 0074 | Instance | CPU_ITM
Description | ITM Stimulus Port 29
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | STIM29 | A write to this location causes data to be written into the FIFO if TER.STIMENA29 is set. Reading from the stimulus port returns the FIFO status in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not provide an atomic read-modify-write, so it's users responsibility to ensure exclusive read-modify-write if this ITM port is used concurrently by interrupts or other threads. | RW | 0x0000 0000

### TOP:CPU_ITM:STIM30

Address offset | 0x0000 0078
Physical address | 0xE000 0078 | Instance | CPU_ITM
Description | ITM Stimulus Port 30
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | STIM30 | A write to this location causes data to be written into the FIFO if TER.STIMENA30 is set. Reading from the stimulus port returns the FIFO status in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not provide an atomic read-modify-write, so it's users responsibility to ensure exclusive read-modify-write if this ITM port is used concurrently by interrupts or other threads. | RW | 0x0000 0000

### TOP:CPU_ITM:STIM31

Address offset | 0x0000 007C
Physical address | 0xE000 007C | Instance | CPU_ITM
Description | ITM Stimulus Port 31
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | STIM31 | A write to this location causes data to be written into the FIFO if TER.STIMENA31 is set. Reading from the stimulus port returns the FIFO status in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not provide an atomic read-modify-write, so it's users responsibility to ensure exclusive read-modify-write if this ITM port is used concurrently by interrupts or other threads. | RW | 0x0000 0000

### TOP:CPU_ITM:TER

Address offset | 0x0000 0E00
Physical address | 0xE000 0E00 | Instance | CPU_ITM
Description | ITM Trace Enable Register Use the Trace Enable Register to generate trace data by writing to the corresponding stimulus port. Note: Privileged writes are accepted to this register if TCR.ITMENA is set. User writes are accepted to this register if TCR.ITMENA is set and the appropriate privilege mask is cleared. Privileged access to the stimulus ports enables an RTOS kernel to guarantee instrumentation slots or bandwidth as required.
Type | RW

Bits | Field Name | Description | Type | Reset
31 | STIMENA31 | Bit mask to enable tracing on ITM stimulus port 31. | RW | 0
30 | STIMENA30 | Bit mask to enable tracing on ITM stimulus port 30. | RW | 0
29 | STIMENA29 | Bit mask to enable tracing on ITM stimulus port 29. | RW | 0
28 | STIMENA28 | Bit mask to enable tracing on ITM stimulus port 28. | RW | 0
27 | STIMENA27 | Bit mask to enable tracing on ITM stimulus port 27. | RW | 0
26 | STIMENA26 | Bit mask to enable tracing on ITM stimulus port 26. | RW | 0
25 | STIMENA25 | Bit mask to enable tracing on ITM stimulus port 25. | RW | 0
24 | STIMENA24 | Bit mask to enable tracing on ITM stimulus port 24. | RW | 0
23 | STIMENA23 | Bit mask to enable tracing on ITM stimulus port 23. | RW | 0
22 | STIMENA22 | Bit mask to enable tracing on ITM stimulus port 22. | RW | 0
21 | STIMENA21 | Bit mask to enable tracing on ITM stimulus port 21. | RW | 0
20 | STIMENA20 | Bit mask to enable tracing on ITM stimulus port 20. | RW | 0
19 | STIMENA19 | Bit mask to enable tracing on ITM stimulus port 19. | RW | 0
18 | STIMENA18 | Bit mask to enable tracing on ITM stimulus port 18. | RW | 0
17 | STIMENA17 | Bit mask to enable tracing on ITM stimulus port 17. | RW | 0
16 | STIMENA16 | Bit mask to enable tracing on ITM stimulus port 16. | RW | 0
15 | STIMENA15 | Bit mask to enable tracing on ITM stimulus port 15. | RW | 0
14 | STIMENA14 | Bit mask to enable tracing on ITM stimulus port 14. | RW | 0
13 | STIMENA13 | Bit mask to enable tracing on ITM stimulus port 13. | RW | 0
12 | STIMENA12 | Bit mask to enable tracing on ITM stimulus port 12. | RW | 0
11 | STIMENA11 | Bit mask to enable tracing on ITM stimulus port 11. | RW | 0
10 | STIMENA10 | Bit mask to enable tracing on ITM stimulus port 10. | RW | 0
9 | STIMENA9 | Bit mask to enable tracing on ITM stimulus port 9. | RW | 0
8 | STIMENA8 | Bit mask to enable tracing on ITM stimulus port 8. | RW | 0
7 | STIMENA7 | Bit mask to enable tracing on ITM stimulus port 7. | RW | 0
6 | STIMENA6 | Bit mask to enable tracing on ITM stimulus port 6. | RW | 0
5 | STIMENA5 | Bit mask to enable tracing on ITM stimulus port 5. | RW | 0
4 | STIMENA4 | Bit mask to enable tracing on ITM stimulus port 4. | RW | 0
3 | STIMENA3 | Bit mask to enable tracing on ITM stimulus port 3. | RW | 0
2 | STIMENA2 | Bit mask to enable tracing on ITM stimulus port 2. | RW | 0
1 | STIMENA1 | Bit mask to enable tracing on ITM stimulus port 1. | RW | 0
0 | STIMENA0 | Bit mask to enable tracing on ITM stimulus port 0. | RW | 0

### TOP:CPU_ITM:TPR

Address offset | 0x0000 0E40
Physical address | 0xE000 0E40 | Instance | CPU_ITM
Description | ITM Trace Privilege Register This register is used to enable an operating system to control which stimulus ports are accessible by user code. This register can only be used in privileged mode.
Type | RW

Bits | Field Name | Description | Type | Reset
31:4 | RESERVED4 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RW | 0x000 0000
3:0 | PRIVMASK | Bit mask to enable unprivileged (User) access to ITM stimulus ports: Bit [0] enables stimulus ports 0, 1, ..., and 7. Bit [1] enables stimulus ports 8, 9, ..., and 15. Bit [2] enables stimulus ports 16, 17, ..., and 23. Bit [3] enables stimulus ports 24, 25, ..., and 31. 0: User access allowed to stimulus ports 1: Privileged access only to stimulus ports | RW | 0x0

### TOP:CPU_ITM:TCR

Address offset | 0x0000 0E80
Physical address | 0xE000 0E80 | Instance | CPU_ITM
Description | ITM Trace Control Register Use this register to configure and control ITM transfers. This register can only be written in privilege mode. DWT is not enabled in the ITM block. However, DWT stimulus entry into the FIFO is controlled by DWTENA. If DWT requires timestamping, the TSENA bit must be set.
Type | RW

Bits | Field Name | Description | Type | Reset
31:24 | RESERVED24 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RW | 0x00
23 | BUSY | Set when ITM events present and being drained. | RW | 0
22:16 | ATBID | Trace Bus ID for CoreSight system. Optional identifier for multi-source trace stream formatting. If multi-source trace is in use, this field must be written with a non-zero value. | RW | 0x00
15:10 | RESERVED10 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RW | 0x00
9:8 | TSPRESCALE | Timestamp prescaler
Value | ENUM name | Description
0x0 | NOPRESCALING | No prescaling
0x1 | DIV4 | Divide by 4
0x2 | DIV16 | Divide by 16
0x3 | DIV64 | Divide by 64
| RW | 0x0
7:5 | RESERVED5 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RW | 0x0
4 | SWOENA | Enables asynchronous clocking of the timestamp counter (when TSENA = 1). If TSENA = 0, writing this bit to 1 does not enable asynchronous clocking of the timestamp counter. 0x0: Mode disabled. Timestamp counter uses system clock from the core and counts continuously. 0x1: Timestamp counter uses lineout (data related) clock from TPIU interface. The timestamp counter is held in reset while the output line is idle. | RW | 0
3 | DWTENA | Enables the DWT stimulus (hardware event packet emission to the TPIU from the DWT) | RW | 0
2 | SYNCENA | Enables synchronization packet transmission for a synchronous TPIU. CPU_DWT:CTRL.SYNCTAP must be configured for the correct synchronization speed. | RW | 0
1 | TSENA | Enables differential timestamps. Differential timestamps are emitted when a packet is written to the FIFO with a non-zero timestamp counter, and when the timestamp counter overflows. Timestamps are emitted during idle times after a fixed number of two million cycles. This provides a time reference for packets and inter-packet gaps. If SWOENA (bit [4]) is set, timestamps are triggered by activity on the internal trace bus only. In this case there is no regular timestamp output when the ITM is idle. | RW | 0
0 | ITMENA | Enables ITM. This is the master enable, and must be set before ITM Stimulus and Trace Enable registers can be written. | RW | 0

### TOP:CPU_ITM:LAR

Address offset | 0x0000 0FB0
Physical address | 0xE000 0FB0 | Instance | CPU_ITM
Description | ITM Lock Access Register This register is used to prevent write accesses to the Control Registers: TER, TPR and TCR.
Type | WO

Bits | Field Name | Description | Type | Reset
31:0 | LOCK_ACCESS | A privileged write of 0xC5ACCE55 enables more write access to Control Registers TER, TPR and TCR. An invalid write removes write access. | WO | 0x0000 0000

### TOP:CPU_ITM:LSR

Address offset | 0x0000 0FB4
Physical address | 0xE000 0FB4 | Instance | CPU_ITM
Description | ITM Lock Status Register Use this register to enable write accesses to the Control Register.
Type | RO

Bits | Field Name | Description | Type | Reset
31:3 | RESERVED3 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0000 0000
2 | BYTEACC | Reads 0 which means 8-bit lock access is not be implemented. | RO | 0
1 | ACCESS | Write access to component is blocked. All writes are ignored, reads are permitted. | RO | 1
0 | PRESENT | Indicates that a lock mechanism exists for this component. | RO | 1