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timer.c
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1 /******************************************************************************
2 * Filename: timer.c
3 * Revised: 2015-01-13 16:59:55 +0100 (ti, 13 jan 2015)
4 * Revision: 42365
5 *
6 * Description: Driver for the General Purpose Timer
7 *
8 * Copyright (c) 2015, Texas Instruments Incorporated
9 * All rights reserved.
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions are met:
13 *
14 * 1) Redistributions of source code must retain the above copyright notice,
15 * this list of conditions and the following disclaimer.
16 *
17 * 2) Redistributions in binary form must reproduce the above copyright notice,
18 * this list of conditions and the following disclaimer in the documentation
19 * and/or other materials provided with the distribution.
20 *
21 * 3) Neither the name of the ORGANIZATION nor the names of its contributors may
22 * be used to endorse or promote products derived from this software without
23 * specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
26 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
28 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
29 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
35 * POSSIBILITY OF SUCH DAMAGE.
36 *
37 ******************************************************************************/
38
39 #include <driverlib/timer.h>
40
41 //*****************************************************************************
42 //
43 // Handle support for DriverLib in ROM:
44 // This section will undo prototype renaming made in the header file
45 //
46 //*****************************************************************************
47 #ifndef DRIVERLIB_GENERATE_ROM
48 #undef TimerConfigure
49 #define TimerConfigure NOROM_TimerConfigure
50 #undef TimerLevelControl
51 #define TimerLevelControl NOROM_TimerLevelControl
52 #undef TimerTriggerControl
53 #define TimerTriggerControl NOROM_TimerTriggerControl
54 #undef TimerStallControl
55 #define TimerStallControl NOROM_TimerStallControl
56 #undef TimerWaitOnTriggerControl
57 #define TimerWaitOnTriggerControl NOROM_TimerWaitOnTriggerControl
58 #undef TimerIntRegister
59 #define TimerIntRegister NOROM_TimerIntRegister
60 #undef TimerIntUnregister
61 #define TimerIntUnregister NOROM_TimerIntUnregister
62 #endif
63
64 //*****************************************************************************
65 //
76 //
77 //*****************************************************************************
78 static uint32_t
79 TimerIntNumberGet(uint32_t ui32Base)
80 {
81 uint32_t ui32Int;
82
83 //
84 // Loop through the table that maps timer base addresses to interrupt
85 // numbers.
86 //
87 switch(ui32Base)
88 {
89 case GPT0_BASE :
90 ui32Int = INT_TIMER0A;
91 break;
92 case GPT1_BASE :
93 ui32Int = INT_TIMER1A;
94 break;
95 case GPT2_BASE :
96 ui32Int = INT_TIMER2A;
97 break;
98 case GPT3_BASE :
99 ui32Int = INT_TIMER3A;
100 break;
101 default :
102 ui32Int = 0x0;
103 }
104
105 //
106 // Return the interrupt number or (-1) if not base address is not matched.
107 //
108 return (ui32Int);
109 }
110
111 //*****************************************************************************
112 //
114 //
115 //*****************************************************************************
116 void
117 TimerConfigure(uint32_t ui32Base, uint32_t ui32Config)
118 {
119 //
120 // Check the arguments.
121 //
122 ASSERT(TimerBaseValid(ui32Base));
123 ASSERT((ui32Config == TIMER_CFG_ONE_SHOT) ||
124 (ui32Config == TIMER_CFG_ONE_SHOT_UP) ||
125 (ui32Config == TIMER_CFG_PERIODIC) ||
126 (ui32Config == TIMER_CFG_PERIODIC_UP) ||
127 (ui32Config == TIMER_CFG_RTC) ||
128 ((ui32Config & 0xFF000000) == TIMER_CFG_SPLIT_PAIR));
129 ASSERT(((ui32Config & 0xFF000000) != TIMER_CFG_SPLIT_PAIR) ||
130 ((((ui32Config & 0x000000FF) == TIMER_CFG_A_ONE_SHOT) ||
131 ((ui32Config & 0x000000FF) == TIMER_CFG_A_ONE_SHOT_UP) ||
132 ((ui32Config & 0x000000FF) == TIMER_CFG_A_PERIODIC) ||
133 ((ui32Config & 0x000000FF) == TIMER_CFG_A_PERIODIC_UP) ||
134 ((ui32Config & 0x000000FF) == TIMER_CFG_A_CAP_COUNT) ||
135 ((ui32Config & 0x000000FF) == TIMER_CFG_A_CAP_COUNT_UP) ||
136 ((ui32Config & 0x000000FF) == TIMER_CFG_A_CAP_TIME) ||
137 ((ui32Config & 0x000000FF) == TIMER_CFG_A_CAP_TIME_UP) ||
138 ((ui32Config & 0x000000FF) == TIMER_CFG_A_PWM)) &&
139 (((ui32Config & 0x0000FF00) == TIMER_CFG_B_ONE_SHOT) ||
140 ((ui32Config & 0x0000FF00) == TIMER_CFG_B_ONE_SHOT_UP) ||
141 ((ui32Config & 0x0000FF00) == TIMER_CFG_B_PERIODIC) ||
142 ((ui32Config & 0x0000FF00) == TIMER_CFG_B_PERIODIC_UP) ||
143 ((ui32Config & 0x0000FF00) == TIMER_CFG_B_CAP_COUNT) ||
144 ((ui32Config & 0x0000FF00) == TIMER_CFG_B_CAP_COUNT_UP) ||
145 ((ui32Config & 0x0000FF00) == TIMER_CFG_B_CAP_TIME) ||
146 ((ui32Config & 0x0000FF00) == TIMER_CFG_B_CAP_TIME_UP) ||
147 ((ui32Config & 0x0000FF00) == TIMER_CFG_B_PWM))));
148
149 //
150 // Disable the timers.
151 //
152 HWREG(ui32Base + GPT_O_CTL) &= ~(GPT_CTL_TAEN | GPT_CTL_TBEN);
153
154 //
155 // Set the global timer configuration.
156 //
157 HWREG(ui32Base + GPT_O_CFG) = ui32Config >> 24;
158
159 //
160 // Set the configuration of the A and B timers. Note that the B timer
161 // configuration is ignored by the hardware in 32-bit modes.
162 //
163 HWREG(ui32Base + GPT_O_TAMR) = (ui32Config & 0xFF) | GPT_TAMR_TAPWMIE;
164 HWREG(ui32Base + GPT_O_TBMR) =
165 ((ui32Config >> 8) & 0xFF) | GPT_TBMR_TBPWMIE;
166 }
167
168 //*****************************************************************************
169 //
171 //
172 //*****************************************************************************
173 void
174 TimerLevelControl(uint32_t ui32Base, uint32_t ui32Timer, bool bInvert)
175 {
176 //
177 // Check the arguments.
178 //
179 ASSERT(TimerBaseValid(ui32Base));
180 ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) ||
181 (ui32Timer == TIMER_BOTH));
182
183 //
184 // Set the output levels as requested.
185 //
186 ui32Timer &= GPT_CTL_TAPWML | GPT_CTL_TBPWML;
187 HWREG(ui32Base + GPT_O_CTL) = (bInvert ?
188 (HWREG(ui32Base + GPT_O_CTL) | ui32Timer) :
189 (HWREG(ui32Base + GPT_O_CTL) &
190 ~(ui32Timer)));
191 }
192
193 //*****************************************************************************
194 //
196 //
197 //*****************************************************************************
198 void
199 TimerTriggerControl(uint32_t ui32Base, uint32_t ui32Timer, bool bEnable)
200 {
201 uint32_t ui32Val;
202
203 //
204 // Check the arguments.
205 //
206 ASSERT(TimerBaseValid(ui32Base));
207 ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) ||
208 (ui32Timer == TIMER_BOTH));
209
210 //
211 // Determine which bits to set or clear in GPTM_ADCEV.
212 //
213 ui32Val = (GPT_ADCEV_TATOADCEN | GPT_ADCEV_TBTOADCEN);
214 ui32Val &= ui32Timer;
215
216 //
217 // Write the GPTM ADC Event register to enable or disable the trigger.
218 // to the ADC.
219 //
220 HWREG(ui32Base + GPT_O_ADCEV) = (bEnable ?
221 (HWREG(ui32Base + GPT_O_ADCEV) | ui32Val) :
222 (HWREG(ui32Base + GPT_O_ADCEV) &
223 ~(ui32Val)));
224
225 //
226 // Set the trigger output as requested.
227 // Set the ADC trigger output as requested.
228 //
229 ui32Timer &= GPT_CTL_TAOTE | GPT_CTL_TBOTE;
230 HWREG(ui32Base + GPT_O_CTL) = (bEnable ?
231 (HWREG(ui32Base + GPT_O_CTL) | ui32Timer) :
232 (HWREG(ui32Base + GPT_O_CTL) &
233 ~(ui32Timer)));
234 }
235
236 //*****************************************************************************
237 //
239 //
240 //*****************************************************************************
241 void
242 TimerStallControl(uint32_t ui32Base, uint32_t ui32Timer, bool bStall)
243 {
244 //
245 // Check the arguments.
246 //
247 ASSERT(TimerBaseValid(ui32Base));
248 ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) ||
249 (ui32Timer == TIMER_BOTH));
250
251 //
252 // Set the stall mode.
253 //
254 ui32Timer &= GPT_CTL_TASTALL | GPT_CTL_TBSTALL;
255 HWREG(ui32Base + GPT_O_CTL) = (bStall ?
256 (HWREG(ui32Base + GPT_O_CTL) | ui32Timer) :
257 (HWREG(ui32Base + GPT_O_CTL) & ~(ui32Timer)));
258 }
259
260 //*****************************************************************************
261 //
263 //
264 //*****************************************************************************
265 void
266 TimerWaitOnTriggerControl(uint32_t ui32Base, uint32_t ui32Timer, bool bWait)
267 {
268 //
269 // Check the arguments.
270 //
271 ASSERT(TimerBaseValid(ui32Base));
272 ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) ||
273 (ui32Timer == TIMER_BOTH));
274
275 //
276 // Set the wait on trigger mode for timer A.
277 //
278 if(ui32Timer & TIMER_A)
279 {
280 if(bWait)
281 {
282 HWREG(ui32Base + GPT_O_TAMR) |= GPT_TAMR_TAWOT;
283 }
284 else
285 {
286 HWREG(ui32Base + GPT_O_TAMR) &= ~(GPT_TAMR_TAWOT);
287 }
288 }
289
290 //
291 // Set the wait on trigger mode for timer B.
292 //
293 if(ui32Timer & TIMER_B)
294 {
295 if(bWait)
296 {
297 HWREG(ui32Base + GPT_O_TBMR) |= GPT_TBMR_TBWOT;
298 }
299 else
300 {
301 HWREG(ui32Base + GPT_O_TBMR) &= ~(GPT_TBMR_TBWOT);
302 }
303 }
304 }
305
306 //*****************************************************************************
307 //
309 //
310 //*****************************************************************************
311 void
312 TimerIntRegister(uint32_t ui32Base, uint32_t ui32Timer, void (*pfnHandler)(void))
313 {
314 uint32_t ui32Int;
315
316 //
317 // Check the arguments.
318 //
319 ASSERT(TimerBaseValid(ui32Base));
320 ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) ||
321 (ui32Timer == TIMER_BOTH));
322
323 //
324 // Get the interrupt number for this timer module.
325 //
326 ui32Int = TimerIntNumberGet(ui32Base);
327
328 //
329 // Register an interrupt handler for timer A if requested.
330 //
331 if(ui32Timer & TIMER_A)
332 {
333 //
334 // Register the interrupt handler.
335 //
336 IntRegister(ui32Int, pfnHandler);
337
338 //
339 // Enable the interrupt.
340 //
341 IntEnable(ui32Int);
342 }
343
344 //
345 // Register an interrupt handler for timer B if requested.
346 //
347 if(ui32Timer & TIMER_B)
348 {
349 //
350 // Register the interrupt handler.
351 //
352 IntRegister(ui32Int + 1, pfnHandler);
353
354 //
355 // Enable the interrupt.
356 //
357 IntEnable(ui32Int + 1);
358 }
359 }
360
361 //*****************************************************************************
362 //
364 //
365 //*****************************************************************************
366 void
367 TimerIntUnregister(uint32_t ui32Base, uint32_t ui32Timer)
368 {
369 uint32_t ui32Int;
370
371 //
372 // Check the arguments.
373 //
374 ASSERT(TimerBaseValid(ui32Base));
375 ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) ||
376 (ui32Timer == TIMER_BOTH));
377
378 //
379 // Get the interrupt number for this timer module.
380 //
381 ui32Int = TimerIntNumberGet(ui32Base);
382
383 //
384 // Unregister the interrupt handler for timer A if requested.
385 //
386 if(ui32Timer & TIMER_A)
387 {
388 //
389 // Disable the interrupt.
390 //
391 IntDisable(ui32Int);
392
393 //
394 // Unregister the interrupt handler.
395 //
396 IntUnregister(ui32Int);
397 }
398
399 //
400 // Unregister the interrupt handler for timer B if requested.
401 //
402 if(ui32Timer & TIMER_B)
403 {
404 //
405 // Disable the interrupt.
406 //
407 IntDisable(ui32Int + 1);
408
409 //
410 // Unregister the interrupt handler.
411 //
412 IntUnregister(ui32Int + 1);
413 }
414 }
TIMER_CFG_SPLIT_PAIR
#define TIMER_CFG_SPLIT_PAIR
Definition: timer.h:102
TimerWaitOnTriggerControl
void TimerWaitOnTriggerControl(uint32_t ui32Base, uint32_t ui32Timer, bool bWait)
Controls the wait on trigger handling.
Definition: timer.c:266
TIMER_CFG_A_PWM
#define TIMER_CFG_A_PWM
Definition: timer.h:111
TIMER_CFG_B_ONE_SHOT
#define TIMER_CFG_B_ONE_SHOT
Definition: timer.h:112
TIMER_CFG_A_ONE_SHOT_UP
#define TIMER_CFG_A_ONE_SHOT_UP
Definition: timer.h:104
TIMER_CFG_A_CAP_TIME_UP
#define TIMER_CFG_A_CAP_TIME_UP
Definition: timer.h:110
TIMER_CFG_PERIODIC_UP
#define TIMER_CFG_PERIODIC_UP
Definition: timer.h:100
TimerStallControl
void TimerStallControl(uint32_t ui32Base, uint32_t ui32Timer, bool bStall)
Controls the stall handling.
Definition: timer.c:242
TIMER_CFG_ONE_SHOT
#define TIMER_CFG_ONE_SHOT
Definition: timer.h:97
ASSERT
#define ASSERT(expr)
Definition: debug.h:65
TIMER_CFG_A_CAP_COUNT_UP
#define TIMER_CFG_A_CAP_COUNT_UP
Definition: timer.h:108
timer.h
TimerIntRegister
void TimerIntRegister(uint32_t ui32Base, uint32_t ui32Timer, void(*pfnHandler)(void))
Registers an interrupt handler for the timer interrupt.
Definition: timer.c:312
TIMER_CFG_B_ONE_SHOT_UP
#define TIMER_CFG_B_ONE_SHOT_UP
Definition: timer.h:113
TIMER_CFG_B_PWM
#define TIMER_CFG_B_PWM
Definition: timer.h:120
TIMER_CFG_B_CAP_TIME
#define TIMER_CFG_B_CAP_TIME
Definition: timer.h:118
TimerConfigure
void TimerConfigure(uint32_t ui32Base, uint32_t ui32Config)
Configures the timer(s)
Definition: timer.c:117
TIMER_CFG_ONE_SHOT_UP
#define TIMER_CFG_ONE_SHOT_UP
Definition: timer.h:98
TIMER_B
#define TIMER_B
Definition: timer.h:157
TIMER_CFG_A_PERIODIC
#define TIMER_CFG_A_PERIODIC
Definition: timer.h:105
TIMER_CFG_B_CAP_TIME_UP
#define TIMER_CFG_B_CAP_TIME_UP
Definition: timer.h:119
TimerIntUnregister
void TimerIntUnregister(uint32_t ui32Base, uint32_t ui32Timer)
Unregisters an interrupt handler for the timer interrupt.
Definition: timer.c:367
TimerLevelControl
void TimerLevelControl(uint32_t ui32Base, uint32_t ui32Timer, bool bInvert)
Controls the output level.
Definition: timer.c:174
TIMER_CFG_B_PERIODIC
#define TIMER_CFG_B_PERIODIC
Definition: timer.h:114
TIMER_CFG_B_CAP_COUNT
#define TIMER_CFG_B_CAP_COUNT
Definition: timer.h:116
TIMER_CFG_B_CAP_COUNT_UP
#define TIMER_CFG_B_CAP_COUNT_UP
Definition: timer.h:117
TIMER_A
#define TIMER_A
Definition: timer.h:156
IntUnregister
void IntUnregister(uint32_t ui32Interrupt)
Unregisters the function to be called when an interrupt occurs.
Definition: interrupt.c:205
TimerTriggerControl
void TimerTriggerControl(uint32_t ui32Base, uint32_t ui32Timer, bool bEnable)
Enables or disables the ADC trigger output.
Definition: timer.c:199
TIMER_CFG_PERIODIC
#define TIMER_CFG_PERIODIC
Definition: timer.h:99
TIMER_CFG_A_ONE_SHOT
#define TIMER_CFG_A_ONE_SHOT
Definition: timer.h:103
TIMER_CFG_A_CAP_COUNT
#define TIMER_CFG_A_CAP_COUNT
Definition: timer.h:107
TIMER_CFG_A_CAP_TIME
#define TIMER_CFG_A_CAP_TIME
Definition: timer.h:109
TIMER_CFG_RTC
#define TIMER_CFG_RTC
Definition: timer.h:101
TIMER_CFG_A_PERIODIC_UP
#define TIMER_CFG_A_PERIODIC_UP
Definition: timer.h:106
TIMER_BOTH
#define TIMER_BOTH
Definition: timer.h:158
IntDisable
void IntDisable(uint32_t ui32Interrupt)
Disables an interrupt.
Definition: interrupt.c:383
IntRegister
void IntRegister(uint32_t ui32Interrupt, void(*pfnHandler)(void))
Registers a function to be called when an interrupt occurs.
Definition: interrupt.c:157
IntEnable
void IntEnable(uint32_t ui32Interrupt)
Enables an interrupt.
Definition: interrupt.c:323
TIMER_CFG_B_PERIODIC_UP
#define TIMER_CFG_B_PERIODIC_UP
Definition: timer.h:115