## CPU_FPB

Instance: CPU_FPB
Component: CPU_FPB
Base address: 0xe0002000

Cortex-M's Flash Patch and Breakpoint (FPB)

### TOP:CPU_FPB Register Summary

Register Name | Type | Register Width (Bits) | Register Reset | Address Offset | Physical Address
CTRL | RW | 32 | 0x0000 0260 | 0x0000 0000 | 0xE000 2000
REMAP | RW | 32 | 0x2000 0000 | 0x0000 0004 | 0xE000 2004
COMP0 | RW | 32 | 0x0000 0000 | 0x0000 0008 | 0xE000 2008
COMP1 | RW | 32 | 0x0000 0000 | 0x0000 000C | 0xE000 200C
COMP2 | RW | 32 | 0x0000 0000 | 0x0000 0010 | 0xE000 2010
COMP3 | RW | 32 | 0x0000 0000 | 0x0000 0014 | 0xE000 2014
COMP4 | RW | 32 | 0x0000 0000 | 0x0000 0018 | 0xE000 2018
COMP5 | RW | 32 | 0x0000 0000 | 0x0000 001C | 0xE000 201C
COMP6 | RW | 32 | 0x0000 0000 | 0x0000 0020 | 0xE000 2020
COMP7 | RW | 32 | 0x0000 0000 | 0x0000 0024 | 0xE000 2024

### TOP:CPU_FPB Register Descriptions

### TOP:CPU_FPB:CTRL

Address offset | 0x0000 0000
Physical address | 0xE000 2000 | Instance | CPU_FPB
Description | Flash Patch Control Register This register is used to enable the flash patch block.
Type | RW

Bits | Field Name | Description | Type | Reset
31:14 | RESERVED14 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0 0000
13:12 | NUM_CODE2 | Number of full banks of code comparators, sixteen comparators per bank. Where less than sixteen code comparators are provided, the bank count is zero, and the number present indicated by NUM_CODE1. This read only field contains 3'b000 to indicate 0 banks for Cortex-M processor. | RO | 0x0
11:8 | NUM_LIT | Number of literal slots field. 0x0: No literal slots 0x2: Two literal slots | RO | 0x2
7:4 | NUM_CODE1 | Number of code slots field. 0x0: No code slots 0x2: Two code slots 0x6: Six code slots | RO | 0x6
3:2 | RESERVED2 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0
1 | KEY | Key field. In order to write to this register, this bit-field must be written to '1'. This bit always reads 0. | WO | 0
0 | ENABLE | Flash patch unit enable bit 0x0: Flash patch unit disabled 0x1: Flash patch unit enabled | RW | 0

### TOP:CPU_FPB:REMAP

Address offset | 0x0000 0004
Physical address | 0xE000 2004 | Instance | CPU_FPB
Description | Flash Patch Remap Register This register provides the remap base address location where a matched addresses are remapped. The three most significant bits and the five least significant bits of the remap base address are hard-coded to 3'b001 and 5'b00000 respectively. The remap base address must be in system space and is it required to be 8-word aligned, with one word allocated to each of the eight FPB comparators.
Type | RW

Bits | Field Name | Description | Type | Reset
31:29 | RESERVED29 | This field always reads 3'b001. Writing to this field is ignored. | RO | 0x1
28:5 | REMAP | Remap base address field. | RW | 0x00 0000
4:0 | RESERVED0 | This field always reads 0. Writing to this field is ignored. | RO | 0x00

### TOP:CPU_FPB:COMP0

Address offset | 0x0000 0008
Physical address | 0xE000 2008 | Instance | CPU_FPB
Description | Flash Patch Comparator Register 0
Type | RW

Bits | Field Name | Description | Type | Reset
31:30 | REPLACE | This selects what happens when the COMP address is matched. Address remapping only takes place for the 0x0 setting. 0x0: Remap to remap address. See REMAP.REMAP 0x1: Set BKPT on lower halfword, upper is unaffected 0x2: Set BKPT on upper halfword, lower is unaffected 0x3: Set BKPT on both lower and upper halfwords. | RW | 0x0
29 | RESERVED29 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RW | 0
28:2 | COMP | Comparison address. | RW | 0x000 0000
1 | RESERVED1 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RW | 0
0 | ENABLE | Compare and remap enable comparator 0. CTRL.ENABLE must also be set to enable comparisons. 0x0: Compare and remap for comparator 0 disabled 0x1: Compare and remap for comparator 0 enabled | RW | 0

### TOP:CPU_FPB:COMP1

Address offset | 0x0000 000C
Physical address | 0xE000 200C | Instance | CPU_FPB
Description | Flash Patch Comparator Register 1
Type | RW

Bits | Field Name | Description | Type | Reset
31:30 | REPLACE | This selects what happens when the COMP address is matched. Address remapping only takes place for the 0x0 setting. 0x0: Remap to remap address. See REMAP.REMAP 0x1: Set BKPT on lower halfword, upper is unaffected 0x2: Set BKPT on upper halfword, lower is unaffected 0x3: Set BKPT on both lower and upper halfwords. | RW | 0x0
29 | RESERVED29 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RW | 0
28:2 | COMP | Comparison address. | RW | 0x000 0000
1 | RESERVED1 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RW | 0
0 | ENABLE | Compare and remap enable comparator 1. CTRL.ENABLE must also be set to enable comparisons. 0x0: Compare and remap for comparator 1 disabled 0x1: Compare and remap for comparator 1 enabled | RW | 0

### TOP:CPU_FPB:COMP2

Address offset | 0x0000 0010
Physical address | 0xE000 2010 | Instance | CPU_FPB
Description | Flash Patch Comparator Register 2
Type | RW

Bits | Field Name | Description | Type | Reset
31:30 | REPLACE | This selects what happens when the COMP address is matched. Address remapping only takes place for the 0x0 setting. 0x0: Remap to remap address. See REMAP.REMAP 0x1: Set BKPT on lower halfword, upper is unaffected 0x2: Set BKPT on upper halfword, lower is unaffected 0x3: Set BKPT on both lower and upper halfwords. | RW | 0x0
29 | RESERVED29 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RW | 0
28:2 | COMP | Comparison address. | RW | 0x000 0000
1 | RESERVED1 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RW | 0
0 | ENABLE | Compare and remap enable comparator 2. CTRL.ENABLE must also be set to enable comparisons. 0x0: Compare and remap for comparator 2 disabled 0x1: Compare and remap for comparator 2 enabled | RW | 0

### TOP:CPU_FPB:COMP3

Address offset | 0x0000 0014
Physical address | 0xE000 2014 | Instance | CPU_FPB
Description | Flash Patch Comparator Register 3
Type | RW

Bits | Field Name | Description | Type | Reset
31:30 | REPLACE | This selects what happens when the COMP address is matched. Address remapping only takes place for the 0x0 setting. 0x0: Remap to remap address. See REMAP.REMAP 0x1: Set BKPT on lower halfword, upper is unaffected 0x2: Set BKPT on upper halfword, lower is unaffected 0x3: Set BKPT on both lower and upper halfwords. | RW | 0x0
29 | RESERVED29 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RW | 0
28:2 | COMP | Comparison address. | RW | 0x000 0000
1 | RESERVED1 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RW | 0
0 | ENABLE | Compare and remap enable comparator 3. CTRL.ENABLE must also be set to enable comparisons. 0x0: Compare and remap for comparator 3 disabled 0x1: Compare and remap for comparator 3 enabled | RW | 0

### TOP:CPU_FPB:COMP4

Address offset | 0x0000 0018
Physical address | 0xE000 2018 | Instance | CPU_FPB
Description | Flash Patch Comparator Register 4
Type | RW

Bits | Field Name | Description | Type | Reset
31:30 | REPLACE | This selects what happens when the COMP address is matched. Address remapping only takes place for the 0x0 setting. 0x0: Remap to remap address. See REMAP.REMAP 0x1: Set BKPT on lower halfword, upper is unaffected 0x2: Set BKPT on upper halfword, lower is unaffected 0x3: Set BKPT on both lower and upper halfwords. | RW | 0x0
29 | RESERVED29 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RW | 0
28:2 | COMP | Comparison address. | RW | 0x000 0000
1 | RESERVED1 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RW | 0
0 | ENABLE | Compare and remap enable comparator 4. CTRL.ENABLE must also be set to enable comparisons. 0x0: Compare and remap for comparator 4 disabled 0x1: Compare and remap for comparator 4 enabled | RW | 0

### TOP:CPU_FPB:COMP5

Address offset | 0x0000 001C
Physical address | 0xE000 201C | Instance | CPU_FPB
Description | Flash Patch Comparator Register 5
Type | RW

Bits | Field Name | Description | Type | Reset
31:30 | REPLACE | This selects what happens when the COMP address is matched. Address remapping only takes place for the 0x0 setting. 0x0: Remap to remap address. See REMAP.REMAP 0x1: Set BKPT on lower halfword, upper is unaffected 0x2: Set BKPT on upper halfword, lower is unaffected 0x3: Set BKPT on both lower and upper halfwords. | RW | 0x0
29 | RESERVED29 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RW | 0
28:2 | COMP | Comparison address. | RW | 0x000 0000
1 | RESERVED1 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RW | 0
0 | ENABLE | Compare and remap enable comparator 5. CTRL.ENABLE must also be set to enable comparisons. 0x0: Compare and remap for comparator 5 disabled 0x1: Compare and remap for comparator 5 enabled | RW | 0

### TOP:CPU_FPB:COMP6

Address offset | 0x0000 0020
Physical address | 0xE000 2020 | Instance | CPU_FPB
Description | Flash Patch Comparator Register 6
Type | RW

Bits | Field Name | Description | Type | Reset
31:30 | REPLACE | This selects what happens when the COMP address is matched. Comparator 6 is a literal comparator and the only supported setting is 0x0. Other settings will be ignored. 0x0: Remap to remap address. See REMAP.REMAP 0x1: Set BKPT on lower halfword, upper is unaffected 0x2: Set BKPT on upper halfword, lower is unaffected 0x3: Set BKPT on both lower and upper halfwords. | RW | 0x0
29 | RESERVED29 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RW | 0
28:2 | COMP | Comparison address. | RW | 0x000 0000
1 | RESERVED1 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RW | 0
0 | ENABLE | Compare and remap enable comparator 6. CTRL.ENABLE must also be set to enable comparisons. 0x0: Compare and remap for comparator 6 disabled 0x1: Compare and remap for comparator 6 enabled | RW | 0

### TOP:CPU_FPB:COMP7

Address offset | 0x0000 0024
Physical address | 0xE000 2024 | Instance | CPU_FPB
Description | Flash Patch Comparator Register 7
Type | RW

Bits | Field Name | Description | Type | Reset
31:30 | REPLACE | This selects what happens when the COMP address is matched. Comparator 7 is a literal comparator and the only supported setting is 0x0. Other settings will be ignored. 0x0: Remap to remap address. See REMAP.REMAP 0x1: Set BKPT on lower halfword, upper is unaffected 0x2: Set BKPT on upper halfword, lower is unaffected 0x3: Set BKPT on both lower and upper halfwords. | RW | 0x0
29 | RESERVED29 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RW | 0
28:2 | COMP | Comparison address. | RW | 0x000 0000
1 | RESERVED1 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RW | 0
0 | ENABLE | Compare and remap enable comparator 7. CTRL.ENABLE must also be set to enable comparisons. 0x0: Compare and remap for comparator 7 disabled 0x1: Compare and remap for comparator 7 enabled | RW | 0