## VIMS

Instance: VIMS
Component: VIMS
Base address: 0x40034000

Versatile Instruction Memory System
Controls memory access to the Flash and encapsulates the following instruction memories:
- Boot ROM
- Cache / GPRAM

### TOP:VIMS Register Summary

Register Name | Type | Register Width (Bits) | Register Reset | Address Offset | Physical Address
STAT | RO | 32 | 0x0000 0000 | 0x0000 0000 | 0x4003 4000
CTL | RW | 32 | 0x0000 0000 | 0x0000 0004 | 0x4003 4004
STATS0 | RO | 32 | 0x0000 0000 | 0x0000 0100 | 0x4003 4100
STATS1 | RO | 32 | 0x0000 0000 | 0x0000 0104 | 0x4003 4104
STATS2 | RO | 32 | 0x0000 0000 | 0x0000 0108 | 0x4003 4108
STATS3 | RO | 32 | 0x0000 0000 | 0x0000 010C | 0x4003 410C
STATS4 | RO | 32 | 0x0000 0000 | 0x0000 0110 | 0x4003 4110
STATS5 | RO | 32 | 0x0000 0000 | 0x0000 0114 | 0x4003 4114

### TOP:VIMS Register Descriptions

### TOP:VIMS:STAT

Address offset | 0x0000 0000
Physical address | 0x4003 4000 | Instance | VIMS
Description | Status Displays current VIMS mode and line buffer status
Type | RO

Bits | Field Name | Description | Type | Reset
31:6 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x000 0000
5 | IDCODE_LB_DIS | Icode/Dcode flash line buffer status 0: Enabled or in transition to disabled 1: Disabled and flushed | RO | 0
4 | SYSBUS_LB_DIS | Sysbus flash line buffer control 0: Enabled or in transition to disabled 1: Disabled and flushed | RO | 0
3 | MODE_CHANGING | VIMS mode change status 0: VIMS is in the mode defined by MODE 1: VIMS is in the process of changing to the mode given in CTL.MODE | RO | 0
2 | INV | This bit is set when invalidation of the cache memory is active / ongoing | RO | 0
1:0 | MODE | Current VIMS mode
Value | ENUM name | Description
0x0 | GPRAM | VIMS GPRAM mode
0x1 | CACHE | VIMS Cache mode
0x2 | SPLIT | VIMS Split Cache mode
0x3 | OFF | VIMS Off mode
| RO | 0x0

### TOP:VIMS:CTL

Address offset | 0x0000 0004
Physical address | 0x4003 4004 | Instance | VIMS
Description | Control Configure VIMS mode and line buffer settings
Type | RW

Bits | Field Name | Description | Type | Reset
31 | STATS_CLR | Set this bit to clear statistic counters. | RW | 0
30 | STATS_EN | Set this bit to enable statistic counters. | RW | 0
29 | DYN_CG_EN | Internal field controlled by TI provided startup code | RW | 0
28:6 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x00 0000
5 | IDCODE_LB_DIS | Icode/Dcode flash line buffer control 0: Enable 1: Disable | RW | 0
4 | SYSBUS_LB_DIS | Sysbus flash line buffer control 0: Enable 1: Disable | RW | 0
3 | ARB_CFG | Icode/Dcode and sysbus arbitation scheme 0: Static arbitration (icode/docde > sysbus) 1: Round-robin arbitration | RW | 0
2 | PREF_EN | Tag prefetch control 0: Disabled 1: Enabled | RW | 0
1:0 | MODE | Internal field controlled by TI provided startup code
Value | ENUM name | Description
0x0 | GPRAM | VIMS GPRAM mode
0x1 | CACHE | VIMS Cache mode
0x2 | SPLIT | VIMS Split Cache mode
0x3 | OFF | VIMS Off mode
| RW | 0x0

### TOP:VIMS:STATS0

Address offset | 0x0000 0100
Physical address | 0x4003 4100 | Instance | VIMS
Description | Cache Statistics Cache hit counter
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | HIT | Cache hit counter (not incuding cache line bufffer accesses) Enabled by setting CTL.STATS_EN Cleared by setting CTL.STATS_CLR | RO | 0x0000 0000

### TOP:VIMS:STATS1

Address offset | 0x0000 0104
Physical address | 0x4003 4104 | Instance | VIMS
Description | Cache Statistics Cache miss counter
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | MISS | Cache miss counter (not incuding cache line bufffer accesses) Enabled by setting CTL.STATS_EN Cleared by setting CTL.STATS_CLR | RO | 0x0000 0000

### TOP:VIMS:STATS2

Address offset | 0x0000 0108
Physical address | 0x4003 4108 | Instance | VIMS
Description | Cache Statistics Cache line buffer hit counter
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | LB_HIT | Cache line buffer hit counter Enabled by setting CTL.STATS_EN Cleared by setting CTL.STATS_CLR | RO | 0x0000 0000

### TOP:VIMS:STATS3

Address offset | 0x0000 010C
Physical address | 0x4003 410C | Instance | VIMS
Description | Cache Statistics Tag prefetch hit counter
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | PREF_HIT | Tag prefetch hit counter Enabled by setting CTL.STATS_EN Cleared by setting CTL.STATS_CLR | RO | 0x0000 0000

### TOP:VIMS:STATS4

Address offset | 0x0000 0110
Physical address | 0x4003 4110 | Instance | VIMS
Description | Cache Statistics Icode stall counter
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | ICODE_STALL | Icode stall counter Enabled by setting CTL.STATS_EN Cleared by setting CTL.STATS_CLR | RO | 0x0000 0000

### TOP:VIMS:STATS5

Address offset | 0x0000 0114
Physical address | 0x4003 4114 | Instance | VIMS
Description | Cache Statistics Dcode Stall counter
Type | RO

Bits | Field Name | Description | Type | Reset
31:0 | DCODE_STALL | Dcode stall counter Enabled by setting CTL.STATS_EN Cleared by setting CTL.STATS_CLR | RO | 0x0000 0000