## RFC_S2R

Instance: RFC_S2R
Component: RFC_S2R
Base address: 0x40048000

Component for s2r register bank

### TOP:RFC_S2R Register Summary

Register Name | Type | Register Width (Bits) | Register Reset | Address Offset | Physical Address
S2RCFG | RW | 32 | 0x0000 0000 | 0x0000 0000 | 0x4004 8000
S2RSTART | RW | 32 | 0x0000 0000 | 0x0000 0004 | 0x4004 8004
S2RSTOP | RW | 32 | 0x0000 0000 | 0x0000 0008 | 0x4004 8008
S2RON | RO | 32 | 0x07FF 0000 | 0x0000 000C | 0x4004 800C

### TOP:RFC_S2R Register Descriptions

### TOP:RFC_S2R:S2RCFG

Address offset | 0x0000 0000
Physical address | 0x4004 8000 | Instance | RFC_S2R
Description | Sample2RAM Config Register
Type | RW

Bits | Field Name | Description | Type | Reset
31:6 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x000 0000
5 | TRIGGER | Trigger a new sample capture (or arm it if the trigger mode is trigger on event) | RW | 0
4:3 | TRIGGERMODE | Trigger mode
Value | ENUM name | Description
0x0 | ONESHOT | One shot mode, i.e. fill memory area once, from start to stop address, upon a manual trigger.
0x1 | PERIODIC | Periodic mode, i.e. fill memory area periodically, continuing at the start address after reaching the stop address, upon a manual trigger.
0x2 | ONEVENT | Trigger on event, i.e. fill memory area once, but wait for an event from the selected sample source.
| RW | 0x0
2:1 | SELECT | Select sample source
Value | ENUM name | Description
0x0 | SYNTH | Samples from frequency synthesizer's DTST interface.
0x1 | ADCDIG | Samples from ADCDIG.
0x2 | FRONTEND | Samples from frontend mux. The sample source is selected in RFC_MDM:DEMDEBUG.FRONTENDDEBUG register.
0x3 | DECSTAGE | Samples from decode stage mux. The sample source is selected in RFC_MDM:DEMDEBUG.DECSTAGEDEBUG register.
| RW | 0x0
0 | ENABLED | Sample2RAM module enable | RW | 0

### TOP:RFC_S2R:S2RSTART

Address offset | 0x0000 0004
Physical address | 0x4004 8004 | Instance | RFC_S2R
Description | Sample2RAM Start Address Register
Type | RW

Bits | Field Name | Description | Type | Reset
31:11 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x00 0000
10:0 | START | Memory start address for where to dump the samples. A custom, unified 32-bit word oriented memory map is used; MCERAM at 0-511, RFERAM at 512-1023, CPERAM at 1024-2047. Please note that it is not possible (due to hardware easter egg) to do a capture which uses the full 2048 words memory range (e.g. 0-2047). | RW | 0x000

### TOP:RFC_S2R:S2RSTOP

Address offset | 0x0000 0008
Physical address | 0x4004 8008 | Instance | RFC_S2R
Description | Sample2RAM Stop Address Register
Type | RW

Bits | Field Name | Description | Type | Reset
31:11 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x00 0000
10:0 | STOP | Memory stop address for where to dump the samples. A custom, unified 32-bit word oriented memory map is used; MCERAM at 0-511, RFERAM at 512-1023, CPERAM at 1024-2047. Please note that it is not possible (due to hardware easter egg) to do a capture which uses the full 2048 words memory range (e.g. 0-2047). | RW | 0x000

### TOP:RFC_S2R:S2RON

Address offset | 0x0000 000C
Physical address | 0x4004 800C | Instance | RFC_S2R
Description | Sample2RAM Status Register
Type | RO

Bits | Field Name | Description | Type | Reset
31:27 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x00
26:16 | ADDRCNT | Current address counter value | RO | 0x7FF
15:1 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0x0000
0 | RUNNING | S2R running status | RO | 0