## CCFG

Instance: CCFG
Component: CCFG
Base address: 0x50003000

Customer configuration area (CCFG)

### TOP:CCFG Register Summary

Register Name | Type | Register Width (Bits) | Register Reset | Address Offset | Physical Address
MODE_CONF_1 | RW | 32 | 0xFFFF FFFF | 0x0000 0FAC | 0x5000 3FAC
SIZE_AND_DIS_FLAGS | RW | 32 | 0xFFFF FFFF | 0x0000 0FB0 | 0x5000 3FB0
MODE_CONF | RW | 32 | 0xFFFF FFFF | 0x0000 0FB4 | 0x5000 3FB4
VOLT_LOAD_0 | RW | 32 | 0xFFFF FFFF | 0x0000 0FB8 | 0x5000 3FB8
VOLT_LOAD_1 | RW | 32 | 0xFFFF FFFF | 0x0000 0FBC | 0x5000 3FBC
RTC_OFFSET | RW | 32 | 0xFFFF FFFF | 0x0000 0FC0 | 0x5000 3FC0
FREQ_OFFSET | RW | 32 | 0xFFFF FFFF | 0x0000 0FC4 | 0x5000 3FC4
IEEE_MAC_0 | RW | 32 | 0xFFFF FFFF | 0x0000 0FC8 | 0x5000 3FC8
IEEE_MAC_1 | RW | 32 | 0xFFFF FFFF | 0x0000 0FCC | 0x5000 3FCC
IEEE_BLE_0 | RW | 32 | 0xFFFF FFFF | 0x0000 0FD0 | 0x5000 3FD0
IEEE_BLE_1 | RW | 32 | 0xFFFF FFFF | 0x0000 0FD4 | 0x5000 3FD4
BL_CONFIG | RW | 32 | 0xC5FF FFFF | 0x0000 0FD8 | 0x5000 3FD8
ERASE_CONF | RW | 32 | 0xFFFF FFFF | 0x0000 0FDC | 0x5000 3FDC
CCFG_TI_OPTIONS | RW | 32 | 0xFFFF FFC5 | 0x0000 0FE0 | 0x5000 3FE0
CCFG_TAP_DAP_0 | RW | 32 | 0xFFC5 C5C5 | 0x0000 0FE4 | 0x5000 3FE4
CCFG_TAP_DAP_1 | RW | 32 | 0xFFC5 C5C5 | 0x0000 0FE8 | 0x5000 3FE8
IMAGE_VALID_CONF | RW | 32 | 0x0000 0000 | 0x0000 0FEC | 0x5000 3FEC
CCFG_PROT_31_0 | RW | 32 | 0xFFFF FFFF | 0x0000 0FF0 | 0x5000 3FF0
CCFG_PROT_63_32 | RW | 32 | 0xFFFF FFFF | 0x0000 0FF4 | 0x5000 3FF4
CCFG_PROT_95_64 | RW | 32 | 0xFFFF FFFF | 0x0000 0FF8 | 0x5000 3FF8
CCFG_PROT_127_96 | RW | 32 | 0xFFFF FFFF | 0x0000 0FFC | 0x5000 3FFC

### TOP:CCFG Register Descriptions

### TOP:CCFG:MODE_CONF_1

Address offset | 0x0000 0FAC
Physical address | 0x5000 3FAC | Instance | CCFG
Description | Mode Configuration 1
Type | RW

Bits | Field Name | Description | Type | Reset
31:24 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text) | RW | 0xFF
23:20 | ALT_DCDC_VMIN | Minimum voltage to use DC/DC is (28 + ALT_DCDC_VMIN)/16. 0: 1.75V 1: 1.8125V . . 14: 2.625V 15: 2.6875V | RW | 0xF
19 | ALT_DCDC_DITHER_EN | Enable DC/DC dithering | RW | 1
18:16 | ALT_DCDC_IPEAK | Inductor peak current. 0: Min 31mA 4: Typical 47mA 7: Max 59mA | RW | 0x7
15:12 | DELTA_IBIAS_INIT | Signed delta value for IBIAS_INIT | RW | 0xF
11:8 | DELTA_IBIAS_OFFSET | Signed delta value for IBIAS_OFFSET | RW | 0xF
7:0 | XOSC_MAX_START | Unsigned value of maximum XOSC startup time in units of 100us | RW | 0xFF

### TOP:CCFG:SIZE_AND_DIS_FLAGS

Address offset | 0x0000 0FB0
Physical address | 0x5000 3FB0 | Instance | CCFG
Description | CCFG Size and Disable Flags
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | SIZE_OF_CCFG | Total size of CCFG | RW | 0xFFFF
15:2 | DISABLE_FLAGS | Reserved for functionality disable flags. Currently unused. | RW | 0x3FFF
1 | DIS_ALT_DCDC_SETTING | Disable flag for alternative DCDC setting | RW | 1
0 | DIS_XOSC_OVR | Disable flag for XOSC override functionality. | RW | 1

### TOP:CCFG:MODE_CONF

Address offset | 0x0000 0FB4
Physical address | 0x5000 3FB4 | Instance | CCFG
Description | Mode Configuration 0
Type | RW

Bits | Field Name | Description | Type | Reset
31:28 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text) | RW | 0xF
27 | DCDC_RECHARGE | 0: Use the DC/DC during recharge in powerdown 1:Do not use the DC/DC during recharge in powerdown (default) | RW | 1
26 | DCDC_ACTIVE | 0: Use the DC/DC during active mode 1: Do not use the DC/DC during active mode (default) | RW | 1
25 | VDDR_EXT_LOAD | 0: VDDR may be loaded externally (may not be supported) 1: VDDR is not loaded externally (default) | RW | 1
24 | VDDS_BOD_LEVEL | 1: VDDS BOD level is 1.8V (or 1.65V for external regulator mode) (default). 0: VDDS BOD level is 2.0V (necessary for 125 degrees C or for external load mode, or for maximum PA output power on CC13xx). Note that production devices meant for 125 degrees C operation will have a VDDS_BOD level of 2.0V trimmed in e-fuse, which means that this field will have no function on these devices. | RW | 1
23:22 | SCLK_LF_OPTION | 0: Low frequency clock derived from High Frequency XOSC 1: TBD: Digital input from AON (selects XOSC_LF as source and XOSC_LF_DIG_BYPASS=1) 2: Low frequency XOSC 3: Low frequency RCOSC (default) | RW | 0x3
21 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text) | RW | 1
20 | RTC_COMP | 0: Apply RTC temperature compensation (may not be supported) 1: Don't apply temperature compensation to the RTC (default) | RW | 1
19:18 | XOSC_FREQ | 00: MEMS, reserved 01: BAW, reserved 10: 48MHz (may not be supported) 11: 24MHz (default) | RW | 0x3
17 | XOSC_CAP_MOD | 0: Apply cap-array delta (may not be supported) 1: Don't apply cap-array delta (default) | RW | 1
16 | HF_COMP | 0: Apply 48MHz compensation (may not be supported) 1: Don't apply 48MHz frequency compensation (default) | RW | 1
15:8 | XOSC_CAPARRAY_DELTA | Signed 8-bit value, directly modifying trimmed XOSC cap-array value. | RW | 0xFF
7:0 | VDDR_CAP | Unsigned 8-bit integer, representing the minimum decoupling capacitance on VDDR, in units of 100nF. This should take into account capacitor tolerance and voltage dependent capacitance variation. | RW | 0xFF

### TOP:CCFG:VOLT_LOAD_0

Address offset | 0x0000 0FB8
Physical address | 0x5000 3FB8 | Instance | CCFG
Description | Voltage Load 0
Type | RW

Bits | Field Name | Description | Type | Reset
31:24 | VDDR_EXT_TP45 | Maximum external VDDR load in powerdown at +45C, on a log2 scale with 4 fractional bits. Current is defined as 10nA*2^N/16 | RW | 0xFF
23:16 | VDDR_EXT_TP25 | Maximum external VDDR load in powerdown at +25C, on a log2 scale with 4 fractional bits. Current is defined as 10nA*2^N/16 | RW | 0xFF
15:8 | VDDR_EXT_TP5 | Maximum external VDDR load in powerdown at +5C, on a log2 scale with 4 fractional bits. Current is defined as 10nA*2^N/16 | RW | 0xFF
7:0 | VDDR_EXT_TM15 | Maximum external VDDR load in powerdown at -15C, on a log2 scale with 4 fractional bits. Current is defined as 10nA*2^N/16 | RW | 0xFF

### TOP:CCFG:VOLT_LOAD_1

Address offset | 0x0000 0FBC
Physical address | 0x5000 3FBC | Instance | CCFG
Description | Voltage Load 1
Type | RW

Bits | Field Name | Description | Type | Reset
31:24 | VDDR_EXT_TP125 | Maximum external VDDR load in powerdown at +125C, on a log2 scale with 4 fractional bits. Current is defined as 10nA*2^N/16 | RW | 0xFF
23:16 | VDDR_EXT_TP105 | Maximum external VDDR load in powerdown at +105C, on a log2 scale with 4 fractional bits. Current is defined as 10nA*2^N/16 | RW | 0xFF
15:8 | VDDR_EXT_TP85 | Maximum external VDDR load in powerdown at +85C, on a log2 scale with 4 fractional bits. Current is defined as 10nA*2^N/16 | RW | 0xFF
7:0 | VDDR_EXT_TP65 | Maximum external VDDR load in powerdown at +65C, on a log2 scale with 4 fractional bits. Current is defined as 10nA*2^N/16 | RW | 0xFF

### TOP:CCFG:RTC_OFFSET

Address offset | 0x0000 0FC0
Physical address | 0x5000 3FC0 | Instance | CCFG
Description | Real Time Clock Offset
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | RTC_COMP_P0 | Signed 16-bit value, representing the RTC offset at 27 degrees C. | RW | 0xFFFF
15:8 | RTC_COMP_P1 | Signed 8-bit value, representing the first order RTC offset slope. | RW | 0xFF
7:0 | RTC_COMP_P2 | Signed 8-bit value, representing the second order RTC offset slope. The actual RTC accumulation value would be defined as 1/32768*(1+d), where d = P0*2^(-20) + P1*(T-27)*2^(-21) + P2*(T-27)^2*2^(-27). | RW | 0xFF

### TOP:CCFG:FREQ_OFFSET

Address offset | 0x0000 0FC4
Physical address | 0x5000 3FC4 | Instance | CCFG
Description | Frequency Offset
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | HF_COMP_P0 | Signed 16-bit value, representing the frequency offset at 27 degrees C. | RW | 0xFFFF
15:8 | HF_COMP_P1 | Signed 8-bit value, representing the first order frequency offset slope. | RW | 0xFF
7:0 | HF_COMP_P2 | Signed 8-bit value, representing the second order frequency offset slope. The actual frequency of the clock would be defined as 48MHz*(1+d), where d = P0*2(-22) + P1*(T-27)*2^(-25) + P2*(T-27)^2*2^(-31). | RW | 0xFF

### TOP:CCFG:IEEE_MAC_0

Address offset | 0x0000 0FC8
Physical address | 0x5000 3FC8 | Instance | CCFG
Description | IEEE MAC Address 0
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | ADDR | Bits[31:0] of the 64-bits IEEE MAC address | RW | 0xFFFF FFFF

### TOP:CCFG:IEEE_MAC_1

Address offset | 0x0000 0FCC
Physical address | 0x5000 3FCC | Instance | CCFG
Description | IEEE MAC Address 1
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | ADDR | Bits[63:32] of the 64-bits IEEE MAC address | RW | 0xFFFF FFFF

### TOP:CCFG:IEEE_BLE_0

Address offset | 0x0000 0FD0
Physical address | 0x5000 3FD0 | Instance | CCFG
Description | IEEE BLE Address 0
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | ADDR | Bits[31:0] of the 64-bits IEEE BLE address | RW | 0xFFFF FFFF

### TOP:CCFG:IEEE_BLE_1

Address offset | 0x0000 0FD4
Physical address | 0x5000 3FD4 | Instance | CCFG
Description | IEEE BLE Address 1
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | ADDR | Bits[63:32] of the 64-bits IEEE BLE address | RW | 0xFFFF FFFF

### TOP:CCFG:BL_CONFIG

Address offset | 0x0000 0FD8
Physical address | 0x5000 3FD8 | Instance | CCFG
Description | Bootloader Config Configures the functionality of the ROM boot loader. If both the boot loader is enabled and the failura analysis is enabled it is possible to force entry of the ROM boot loader even if a valid image is present in flash.
Type | RW

Bits | Field Name | Description | Type | Reset
31:24 | BOOTLOADER_ENABLE | 0xC5: Boot loader is enabled Any other value: Boot loader is disabled NOTE! This parameter must be written to the value of 0xC5 by production test. | RW | 0xC5
23:17 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text) | RW | 0x7F
16 | BL_LEVEL | BL_LEVEL - sets the active level of the selected pin. 0: Active low. 1: Active high. | RW | 1
15:8 | BL_PIN_NUMBER | BL_PIN_NUMBER - is the number of the I/O-pin that is level checked if the boot loader failure analysis is enabled. | RW | 0xFF
7:0 | BL_ENABLE | BL_ENABLE - enables or disables the boot loader failure analysis.. 0xC5: Failure analysis enabled. Any other value: Failure analysis disabled. | RW | 0xFF

### TOP:CCFG:ERASE_CONF

Address offset | 0x0000 0FDC
Physical address | 0x5000 3FDC | Instance | CCFG
Description | Erase Configuration
Type | RW

Bits | Field Name | Description | Type | Reset
31:9 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text) | RW | 0x7F FFFF
8 | CHIP_ERASE_DIS_N | 0: Any chip erase request detected during boot will be ignored. The boot FW will clear AON_WUC:CTL1.CHIP_ERASE and proceed with normal boot sequence. 1: Any chip erase request detected during boot will be performed by the boot FW. | RW | 1
7:1 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text) | RW | 0x7F
0 | BANK_ERASE_DIS_N | Setting this bit to 0 will disable the boot loader bank erase function. This bit will be tested by the ROM boot loader in order to verify if a received Bank Erase boot loader command can be executed or not. Bank erase is also referred to as mass erase. | RW | 1

### TOP:CCFG:CCFG_TI_OPTIONS

Address offset | 0x0000 0FE0
Physical address | 0x5000 3FE0 | Instance | CCFG
Description | TI Options
Type | RW

Bits | Field Name | Description | Type | Reset
31:8 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text) | RW | 0xFF FFFF
7:0 | TI_FA_ENABLE | Must have a value of 0xC5 in order to enable the functionality of unlocking the TI FA (TI Failure Analysis) option with the unlock code. All other values will disable the functionality of unlocking the TI FA option with the unlock code. Unlock is configured by ROM startup code while in safezone dependent on TI_FA_ENABLE. NOTE! This parameter must be written to the value of 0xC5 by production test. | RW | 0xC5

### TOP:CCFG:CCFG_TAP_DAP_0

Address offset | 0x0000 0FE4
Physical address | 0x5000 3FE4 | Instance | CCFG
Description | Test Access Points Enable 0
Type | RW

Bits | Field Name | Description | Type | Reset
31:24 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text) | RW | 0xFF
23:16 | CPU_DAP_ENABLE | 0xC5: AON_WUC:JTAGCFG.CPU_DAP will be set to 1 if FCFG1:FCFG1_TAP_DAP_0.CPU_DAP_ENABLE also have a value of 0xC5. Bit field is written by boot FW while in safezone. Any other value: AON_WUC:JTAGCFG.CPU_DAP will be set to 0 by boot FW while in safezone. NOTE! This parameter must be written to the value of 0xC5 by production test. | RW | 0xC5
15:8 | PRCM_TAP_ENABLE | 0xC5: AON_WUC:JTAGCFG.PRCM_TAP will be set to 1 if FCFG1:FCFG1_TAP_DAP_0.PRCM_TAP_ENABLE also have a value of 0xC5. Bit field is written by boot FW while in safezone. Any other value: AON_WUC:JTAGCFG.PRCM_TAP will be set to 0 by boot FW while in safezone. NOTE! This parameter must be written to the value of 0xC5 by production test. | RW | 0xC5
7:0 | TEST_TAP_ENABLE | 0xC5: AON_WUC:JTAGCFG.TEST_TAP will be set to 1 if FCFG1:FCFG1_TAP_DAP_0.TEST_TAP_ENABLE also have a value of 0xC5. Bit field is written by boot FW while in safezone. Any other value: AON_WUC:JTAGCFG.TEST_TAP will be set to 0 by boot FW while in safezone. NOTE! This parameter must be written to the value of 0xC5 by production test. | RW | 0xC5

### TOP:CCFG:CCFG_TAP_DAP_1

Address offset | 0x0000 0FE8
Physical address | 0x5000 3FE8 | Instance | CCFG
Description | Test Access Points Enable 1
Type | RW

Bits | Field Name | Description | Type | Reset
31:24 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text) | RW | 0xFF
23:16 | PBIST2_TAP_ENABLE | 0xC5: AON_WUC:JTAGCFG.PBIST2_TAP will be set to 1 if FCFG1:FCFG1_TAP_DAP_1.PBIST2_TAP_ENABLE also have a value of 0xC5. Bit field is written by boot FW while in safezone. Any other value: AON_WUC:JTAGCFG.PBIST2_TAP will be set to 0 by boot FW while in safezone. NOTE! This parameter must be written to the value of 0xC5 by production test. | RW | 0xC5
15:8 | PBIST1_TAP_ENABLE | 0xC5: AON_WUC:JTAGCFG.PBIST1_TAP will be set to 1 if FCFG1:FCFG1_TAP_DAP_1.PBIST1_TAP_ENABLE also have a value of 0xC5. Bit field is written by boot FW while in safezone. Any other value: AON_WUC:JTAGCFG.PBIST1_TAP will be set to 0 by boot FW while in safezone. NOTE! This parameter must be written to the value of 0xC5 by production test. | RW | 0xC5
7:0 | WUC_TAP_ENABLE | 0xC5: AON_WUC:JTAGCFG.WUC_TAP will be set to 1 if FCFG1:FCFG1_TAP_DAP_1.WUC_TAP_ENABLE also have a value of 0xC5. Bit field is written by boot FW while in safezone. Any other value: AON_WUC:JTAGCFG.WUC_TAP will be set to 0 by boot FW while in safezone. NOTE! This parameter must be written to the value of 0xC5 by production test. | RW | 0xC5

### TOP:CCFG:IMAGE_VALID_CONF

Address offset | 0x0000 0FEC
Physical address | 0x5000 3FEC | Instance | CCFG
Description | Image Valid
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | IMAGE_VALID | IMAGE_VALID: This field must have a value of 0x00000000 in order for enabling the boot sequence to transfer control to a flash image. | RW | 0x0000 0000

### TOP:CCFG:CCFG_PROT_31_0

Address offset | 0x0000 0FF0
Physical address | 0x5000 3FF0 | Instance | CCFG
Description | Protect Sectors 0-31 Each bit write protects one sector from being both programmed and erased. Bit must be set to 0 in order to enable sector write protect. The sector write protection is enabled by setting corresponding bit in the FSM_BSLE0- and FSM_BSLP0-registers in the flash controller.
Type | RW

Bits | Field Name | Description | Type | Reset
31 | WRT_PROT_SEC_31 | 0: Sector protected | RW | 1
30 | WRT_PROT_SEC_30 | 0: Sector protected | RW | 1
29 | WRT_PROT_SEC_29 | 0: Sector protected | RW | 1
28 | WRT_PROT_SEC_28 | 0: Sector protected | RW | 1
27 | WRT_PROT_SEC_27 | 0: Sector protected | RW | 1
26 | WRT_PROT_SEC_26 | 0: Sector protected | RW | 1
25 | WRT_PROT_SEC_25 | 0: Sector protected | RW | 1
24 | WRT_PROT_SEC_24 | 0: Sector protected | RW | 1
23 | WRT_PROT_SEC_23 | 0: Sector protected | RW | 1
22 | WRT_PROT_SEC_22 | 0: Sector protected | RW | 1
21 | WRT_PROT_SEC_21 | 0: Sector protected | RW | 1
20 | WRT_PROT_SEC_20 | 0: Sector protected | RW | 1
19 | WRT_PROT_SEC_19 | 0: Sector protected | RW | 1
18 | WRT_PROT_SEC_18 | 0: Sector protected | RW | 1
17 | WRT_PROT_SEC_17 | 0: Sector protected | RW | 1
16 | WRT_PROT_SEC_16 | 0: Sector protected | RW | 1
15 | WRT_PROT_SEC_15 | 0: Sector protected | RW | 1
14 | WRT_PROT_SEC_14 | 0: Sector protected | RW | 1
13 | WRT_PROT_SEC_13 | 0: Sector protected | RW | 1
12 | WRT_PROT_SEC_12 | 0: Sector protected | RW | 1
11 | WRT_PROT_SEC_11 | 0: Sector protected | RW | 1
10 | WRT_PROT_SEC_10 | 0: Sector protected | RW | 1
9 | WRT_PROT_SEC_9 | 0: Sector protected | RW | 1
8 | WRT_PROT_SEC_8 | 0: Sector protected | RW | 1
7 | WRT_PROT_SEC_7 | 0: Sector protected | RW | 1
6 | WRT_PROT_SEC_6 | 0: Sector protected | RW | 1
5 | WRT_PROT_SEC_5 | 0: Sector protected | RW | 1
4 | WRT_PROT_SEC_4 | 0: Sector protected | RW | 1
3 | WRT_PROT_SEC_3 | 0: Sector protected | RW | 1
2 | WRT_PROT_SEC_2 | 0: Sector protected | RW | 1
1 | WRT_PROT_SEC_1 | 0: Sector protected | RW | 1
0 | WRT_PROT_SEC_0 | 0: Sector protected | RW | 1

### TOP:CCFG:CCFG_PROT_63_32

Address offset | 0x0000 0FF4
Physical address | 0x5000 3FF4 | Instance | CCFG
Description | Protect Sectors 32-63 Each bit write protects one sector from being both programmed and erased. Bit must be set to 0 in order to enable sector write protect. The sector write protection is enabled by setting corresponding bit in the FSM_BSLE1- and FSM_BSLP1-registers in the flash controller. These registers are not in use by CC26xx.
Type | RW

Bits | Field Name | Description | Type | Reset
31 | WRT_PROT_SEC_63 | 0: Sector protected | RW | 1
30 | WRT_PROT_SEC_62 | 0: Sector protected | RW | 1
29 | WRT_PROT_SEC_61 | 0: Sector protected | RW | 1
28 | WRT_PROT_SEC_60 | 0: Sector protected | RW | 1
27 | WRT_PROT_SEC_59 | 0: Sector protected | RW | 1
26 | WRT_PROT_SEC_58 | 0: Sector protected | RW | 1
25 | WRT_PROT_SEC_57 | 0: Sector protected | RW | 1
24 | WRT_PROT_SEC_56 | 0: Sector protected | RW | 1
23 | WRT_PROT_SEC_55 | 0: Sector protected | RW | 1
22 | WRT_PROT_SEC_54 | 0: Sector protected | RW | 1
21 | WRT_PROT_SEC_53 | 0: Sector protected | RW | 1
20 | WRT_PROT_SEC_52 | 0: Sector protected | RW | 1
19 | WRT_PROT_SEC_51 | 0: Sector protected | RW | 1
18 | WRT_PROT_SEC_50 | 0: Sector protected | RW | 1
17 | WRT_PROT_SEC_49 | 0: Sector protected | RW | 1
16 | WRT_PROT_SEC_48 | 0: Sector protected | RW | 1
15 | WRT_PROT_SEC_47 | 0: Sector protected | RW | 1
14 | WRT_PROT_SEC_46 | 0: Sector protected | RW | 1
13 | WRT_PROT_SEC_45 | 0: Sector protected | RW | 1
12 | WRT_PROT_SEC_44 | 0: Sector protected | RW | 1
11 | WRT_PROT_SEC_43 | 0: Sector protected | RW | 1
10 | WRT_PROT_SEC_42 | 0: Sector protected | RW | 1
9 | WRT_PROT_SEC_41 | 0: Sector protected | RW | 1
8 | WRT_PROT_SEC_40 | 0: Sector protected | RW | 1
7 | WRT_PROT_SEC_39 | 0: Sector protected | RW | 1
6 | WRT_PROT_SEC_38 | 0: Sector protected | RW | 1
5 | WRT_PROT_SEC_37 | 0: Sector protected | RW | 1
4 | WRT_PROT_SEC_36 | 0: Sector protected | RW | 1
3 | WRT_PROT_SEC_35 | 0: Sector protected | RW | 1
2 | WRT_PROT_SEC_34 | 0: Sector protected | RW | 1
1 | WRT_PROT_SEC_33 | 0: Sector protected | RW | 1
0 | WRT_PROT_SEC_32 | 0: Sector protected | RW | 1

### TOP:CCFG:CCFG_PROT_95_64

Address offset | 0x0000 0FF8
Physical address | 0x5000 3FF8 | Instance | CCFG
Description | Protect Sectors 64-95 Each bit write protects one sector from being both programmed and erased. Bit must be set to 0 in order to enable sector write protect. Not in use on CC26xx.
Type | RW

Bits | Field Name | Description | Type | Reset
31 | WRT_PROT_SEC_95 | 0: Sector protected | RW | 1
30 | WRT_PROT_SEC_94 | 0: Sector protected | RW | 1
29 | WRT_PROT_SEC_93 | 0: Sector protected | RW | 1
28 | WRT_PROT_SEC_92 | 0: Sector protected | RW | 1
27 | WRT_PROT_SEC_91 | 0: Sector protected | RW | 1
26 | WRT_PROT_SEC_90 | 0: Sector protected | RW | 1
25 | WRT_PROT_SEC_89 | 0: Sector protected | RW | 1
24 | WRT_PROT_SEC_88 | 0: Sector protected | RW | 1
23 | WRT_PROT_SEC_87 | 0: Sector protected | RW | 1
22 | WRT_PROT_SEC_86 | 0: Sector protected | RW | 1
21 | WRT_PROT_SEC_85 | 0: Sector protected | RW | 1
20 | WRT_PROT_SEC_84 | 0: Sector protected | RW | 1
19 | WRT_PROT_SEC_83 | 0: Sector protected | RW | 1
18 | WRT_PROT_SEC_82 | 0: Sector protected | RW | 1
17 | WRT_PROT_SEC_81 | 0: Sector protected | RW | 1
16 | WRT_PROT_SEC_80 | 0: Sector protected | RW | 1
15 | WRT_PROT_SEC_79 | 0: Sector protected | RW | 1
14 | WRT_PROT_SEC_78 | 0: Sector protected | RW | 1
13 | WRT_PROT_SEC_77 | 0: Sector protected | RW | 1
12 | WRT_PROT_SEC_76 | 0: Sector protected | RW | 1
11 | WRT_PROT_SEC_75 | 0: Sector protected | RW | 1
10 | WRT_PROT_SEC_74 | 0: Sector protected | RW | 1
9 | WRT_PROT_SEC_73 | 0: Sector protected | RW | 1
8 | WRT_PROT_SEC_72 | 0: Sector protected | RW | 1
7 | WRT_PROT_SEC_71 | 0: Sector protected | RW | 1
6 | WRT_PROT_SEC_70 | 0: Sector protected | RW | 1
5 | WRT_PROT_SEC_69 | 0: Sector protected | RW | 1
4 | WRT_PROT_SEC_68 | 0: Sector protected | RW | 1
3 | WRT_PROT_SEC_67 | 0: Sector protected | RW | 1
2 | WRT_PROT_SEC_66 | 0: Sector protected | RW | 1
1 | WRT_PROT_SEC_65 | 0: Sector protected | RW | 1
0 | WRT_PROT_SEC_64 | 0: Sector protected | RW | 1

### TOP:CCFG:CCFG_PROT_127_96

Address offset | 0x0000 0FFC
Physical address | 0x5000 3FFC | Instance | CCFG
Description | Protect Sectors 96-127 Each bit write protects one sector from being both programmed and erased. Bit must be set to 0 in order to enable sector write protect. Not in use on CC26xx.
Type | RW

Bits | Field Name | Description | Type | Reset
31 | WRT_PROT_SEC_127 | 0: Sector protected | RW | 1
30 | WRT_PROT_SEC_126 | 0: Sector protected | RW | 1
29 | WRT_PROT_SEC_125 | 0: Sector protected | RW | 1
28 | WRT_PROT_SEC_124 | 0: Sector protected | RW | 1
27 | WRT_PROT_SEC_123 | 0: Sector protected | RW | 1
26 | WRT_PROT_SEC_122 | 0: Sector protected | RW | 1
25 | WRT_PROT_SEC_121 | 0: Sector protected | RW | 1
24 | WRT_PROT_SEC_120 | 0: Sector protected | RW | 1
23 | WRT_PROT_SEC_119 | 0: Sector protected | RW | 1
22 | WRT_PROT_SEC_118 | 0: Sector protected | RW | 1
21 | WRT_PROT_SEC_117 | 0: Sector protected | RW | 1
20 | WRT_PROT_SEC_116 | 0: Sector protected | RW | 1
19 | WRT_PROT_SEC_115 | 0: Sector protected | RW | 1
18 | WRT_PROT_SEC_114 | 0: Sector protected | RW | 1
17 | WRT_PROT_SEC_113 | 0: Sector protected | RW | 1
16 | WRT_PROT_SEC_112 | 0: Sector protected | RW | 1
15 | WRT_PROT_SEC_111 | 0: Sector protected | RW | 1
14 | WRT_PROT_SEC_110 | 0: Sector protected | RW | 1
13 | WRT_PROT_SEC_109 | 0: Sector protected | RW | 1
12 | WRT_PROT_SEC_108 | 0: Sector protected | RW | 1
11 | WRT_PROT_SEC_107 | 0: Sector protected | RW | 1
10 | WRT_PROT_SEC_106 | 0: Sector protected | RW | 1
9 | WRT_PROT_SEC_105 | 0: Sector protected | RW | 1
8 | WRT_PROT_SEC_104 | 0: Sector protected | RW | 1
7 | WRT_PROT_SEC_103 | 0: Sector protected | RW | 1
6 | WRT_PROT_SEC_102 | 0: Sector protected | RW | 1
5 | WRT_PROT_SEC_101 | 0: Sector protected | RW | 1
4 | WRT_PROT_SEC_100 | 0: Sector protected | RW | 1
3 | WRT_PROT_SEC_99 | 0: Sector protected | RW | 1
2 | WRT_PROT_SEC_98 | 0: Sector protected | RW | 1
1 | WRT_PROT_SEC_97 | 0: Sector protected | RW | 1
0 | WRT_PROT_SEC_96 | 0: Sector protected | RW | 1