## EFUSE

Instance: EFUSE
Component: EFUSE
Base address: 0x10000000

Efuse area

### TOP:EFUSE Register Summary

Register Name | Type | Register Width (Bits) | Register Reset | Address Offset | Physical Address
DIE_ID_0 | RW | 32 | 0bX000_0000_0000_0000_0000_0000_0000_0000 | 0x0000 000C | NA
DIE_ID_1 | RW | 32 | 0bX000_0000_0000_0000_0000_0000_0000_0000 | 0x0000 0010 | NA
DIE_ID_2 | RW | 32 | 0bX000_0000_0000_0000_0000_0000_0000_0000 | 0x0000 0014 | NA
DIE_ID_3 | RW | 32 | 0bX000_0000_0000_0000_0000_0000_0000_0000 | 0x0000 0018 | NA
SCAN_DATA0 | RW | 32 | 0bX000_0000_0000_0000_0000_0000_0000_0000 | 0x0000 001C | NA
SCAN_DATA1 | RW | 32 | 0bX000_0000_0000_0000_0000_0000_0000_0000 | 0x0000 0020 | NA
SCAN_DATA2_BOOT | RW | 32 | 0bX000_0000_0000_0000_0000_0000_0000_0000 | 0x0000 0024 | NA
BANK_TRIM_BOOT | RW | 32 | 0bX000_0000_0000_0000_0000_0000_0000_0000 | 0x0000 0028 | NA
OSC_BIAS_LDO_TRIM | RW | 32 | 0bX000_0000_0000_0000_0000_0000_0000_0000 | 0x0000 002C | NA
ANA_TRIM | RW | 32 | 0bX000_0000_0000_0000_0000_0000_0000_0000 | 0x0000 0030 | NA

### TOP:EFUSE Register Descriptions

### TOP:EFUSE:DIE_ID_0

Address offset | 0x0000 000C
Physical address | NA | Instance | EFUSE
Description | Note: Efuse row number = (Address Offset / 4)
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | ID_31_0 | Bit[31:0] of the 128-bit die ID | RW | 0xXXXX XXXX

### TOP:EFUSE:DIE_ID_1

Address offset | 0x0000 0010
Physical address | NA | Instance | EFUSE
Description | Note: Efuse row number = (Address Offset / 4)
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | ID_63_32 | Bit[63:32] of the 128-bit die ID | RW | 0xXXXX XXXX

### TOP:EFUSE:DIE_ID_2

Address offset | 0x0000 0014
Physical address | NA | Instance | EFUSE
Description | Note: Efuse row number = (Address Offset / 4)
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | ID_95_64 | Bit[95:64] of the 128-bit die ID | RW | 0xXXXX XXXX

### TOP:EFUSE:DIE_ID_3

Address offset | 0x0000 0018
Physical address | NA | Instance | EFUSE
Description | Note: Efuse row number = (Address Offset / 4)
Type | RW

Bits | Field Name | Description | Type | Reset
31:0 | ID_127_96 | Bit[127:96] of the 128-bit die ID | RW | 0xXXXX XXXX

### TOP:EFUSE:SCAN_DATA0

Address offset | 0x0000 001C
Physical address | NA | Instance | EFUSE
Description | Note: Efuse row number = (Address Offset / 4). This row is included in the HW scan. Bit[0] is the first bit in the scan chain.
Type | RW

Bits | Field Name | Description | Type | Reset
31:29 | ULL_MCU_RAM1_REP | Bits[2:0] of MCU RAM1 repair | RW | 0x0
28:19 | ULL_MCU_RAM2_REP | Bits[9:0] of MCU RAM2 repair | RW | 0x000
18:9 | ULL_MCU_RAM3_REP | Bits[9:0] of MCU RAM3 repair | RW | 0x000
8:1 | ULL_AUX_RAM_REP | Bits[7:0] of AUX RAM repair | RW | 0x00
0 | TAP_DAP_LOCK | If TAP_DAP_LOCK == SCAN_DATA2_BOOT.TAP_DAP_LOCK_N: Device locked If TAP_DAP_LOCK != SCAN_DATA2_BOOT.TAP_DAP_LOCK_N: Device unlocked The device lock status will be reflected [CPU_MMAP::AON_WUC.LOCKCFG.UNLOCK] | RW | 0

### TOP:EFUSE:SCAN_DATA1

Address offset | 0x0000 0020
Physical address | NA | Instance | EFUSE
Description | Note: Efuse row number = (Address Offset / 4). This row is included in the HW scan and crc but not used in HW.
Type | RW

Bits | Field Name | Description | Type | Reset
31:17 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text) | RW | 0x0000
16:7 | ULL_MCU_RAM0_REP | Bits[9:0] of MCU RAM0 repair | RW | 0x000
6:0 | ULL_MCU_RAM1_REP | Bits[9:3] of MCU RAM1 repair | RW | 0x00

### TOP:EFUSE:SCAN_DATA2_BOOT

Address offset | 0x0000 0024
Physical address | NA | Instance | EFUSE
Description | Note: Efuse row number = (Address Offset / 4). Bits[8:0] of this row is included in the HW scan. Bit[8] is the last bit in the scan chain.
Type | RW

Bits | Field Name | Description | Type | Reset
31 | FLASH_RDY | 0: FW halts CPU during boot with all DAP/TAPs unlocked after having configured flash module for read capability. 1: FW will not interfere the boot process due to this value. | RW | 1
30 | STANDBY_MODE_SEL_INT | If AON_SYSCTL:PWRCTL.EXT_REG_MODE = 0, this value will be written to FLASH:CFG.STANDBY_MODE_SEL by FW during boot. This register bit field will be updated by FW with trim value from FCFG1 later in the boot sequence. | RW | 0
29:28 | STANDBY_PW_SEL_INT | If AON_SYSCTL:PWRCTL.EXT_REG_MODE = 0, this value will be written to FLASH:CFG.STANDBY_PW_SEL by FW during boot. This register bit field will be updated by FW with trim value from FCFG1 later in the boot sequence. | RW | 0x0
27 | DIS_STANDBY_INT | If AON_SYSCTL:PWRCTL.EXT_REG_MODE = 0, this value will be written to FLASH:CFG.DIS_STANDBY by FW during boot. This register bit field will be updated by FW with trim value from FCFG1 later in the boot sequence. | RW | 0
26:24 | VIN_AT_X_INT | If AON_SYSCTL:PWRCTL.EXT_REG_MODE = 0, this value will be written to [FLASH.FSEQPMP.VIN_AT_X] by FW during boot. This register bit field will be updated by FW with trim value from FCFG1 later in the boot sequence. | RW | 0x0
23 | STANDBY_MODE_SEL_EXT | If AON_SYSCTL:PWRCTL.EXT_REG_MODE = 1, this value will be written to FLASH:CFG.STANDBY_MODE_SEL by FW during boot. This register bit field will be updated by FW with trim value from FCFG1 later in the boot sequence. | RW | 0
22:21 | STANDBY_PW_SEL_EXT | If AON_SYSCTL:PWRCTL.EXT_REG_MODE = 1, this value will be written to FLASH:CFG.STANDBY_PW_SEL by FW during boot. This register bit field will be updated by FW with trim value from FCFG1 later in the boot sequence. | RW | 0x0
20 | DIS_STANDBY_EXT | If AON_SYSCTL:PWRCTL.EXT_REG_MODE = 1, this value will be written to FLASH:CFG.DIS_STANDBY by FW during boot. This register bit field will be updated by FW with trim value from FCFG1 later in the boot sequence. | RW | 0
19:17 | VIN_AT_X_EXT | If AON_SYSCTL:PWRCTL.EXT_REG_MODE = 1, this value will be written to FLASH:FSEQPMP.VIN_AT_X by FW during boot. This register bit field will be updated by FW with trim value from FCFG1 later in the boot sequence. | RW | 0x0
16:9 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text) | RW | 0x00
8:1 | CRC | Checksum of SCAN_DATA0 row bits[31:0] and SCAN_DATA1 row bit[31:0] and SCAN_DATA2_TRIM row bit[0]. This field is included in the scan chain. | RW | 0xXX
0 | TAP_DAP_LOCK_N | If TAP_DAP_LOCK == SCAN_DATA2_BOOT.TAP_DAP_LOCK_N: [CPU_MMAP::AON_WUC.LOCKCFG.SECURITY_STATE] = 0, ie device is locked. If TAP_DAP_LOCK != SCAN_DATA2_BOOT.TAP_DAP_LOCK_N: [CPU_MMAP::AON_WUC.LOCKCFG.SECURITY_STATE] = 1, ie device is unlocked. | RW | 0

### TOP:EFUSE:BANK_TRIM_BOOT

Address offset | 0x0000 0028
Physical address | NA | Instance | EFUSE
Description | Note: Efuse row number = (Address Offset / 4). The data in this row will be written to registers in the FLASH module by FW during boot. ROM_BOOT will control debug capabilities of the boot FW.
Type | RW

Bits | Field Name | Description | Type | Reset
31:30 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text) | RW | 0x0
29 | ROM_BOOT | 0: FW will halt CPU immediatly after release of reset and the reading of this bit. 1: FW will not interfere the boot process due to this value. | RW | 1
28:25 | TRIM3P4 | Value will be written to FLASH:FSEQPMP.TRIM_3P4 by FW during boot. | RW | 0x5
24:21 | VCG2P5CT | Value will be written to FLASH:FVNVCT.VCG2P5CT by FW during boot. | RW | 0xX
20:17 | VREADCT | Value will be written to FLASH:FVREADCT.VREADCT by FW during boot. | RW | 0xX
16:13 | TRIM_0P8 | Value will be written to FLASH:FSEQPMP.TRIM_0P8by FW during boot. | RW | 0x8
12:10 | TRIM_SADLY | This value will be written to bit[12:10] of FLASH:BANK_0_EFUSE by FW during boot. The 19 MSB bits of that register will be written to the pattern 0b0000000000001001000 by FW. | RW | 0x1
9:5 | TRIM_NMOS | This value will be written to bit[9:5] of FLASH:BANK_0_EFUSE by FW during boot. The 19 MSB bits of that register will be written to the pattern 0b0000000000001001000 by FW. | RW | 0xXX
4:0 | TRIM_PMOS | This value will be written to bit[4:0] of FLASH:BANK_0_EFUSE by FW during boot. The 19 MSB bits of that register will be written to the pattern 0b0000000000001001000 by FW. | RW | 0xXX

### TOP:EFUSE:OSC_BIAS_LDO_TRIM

Address offset | 0x0000 002C
Physical address | NA | Instance | EFUSE
Description | Note: Efuse row number = (Address Offset / 4)
Type | RW

Bits | Field Name | Description | Type | Reset
31:29 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text) | RW | 0x0
28:27 | SET_RCOSC_HF_COARSE_RESISTOR | Value will be written to DDI_0_OSC:ATESTCTL.SET_RCOSC_HF_FINE_RESISTOR by FW during boot. | RW | 0xX
26:23 | TRIMMAG | Value will be written to ADI_3_REFSYS:REFSYSCTL2.TRIM_VREF by FW during boot. | RW | 0xX
22:18 | TRIMIREF | Value will be written to ADI_2_REFSYS:REFSYSCTL0.TRIM_IREF by FW during boot. | RW | 0xXX
17:16 | ITRIM_DIG_LDO | Value is read by FW and is used in the calculation to find the value that is written to ADI_2_REFSYS:SOCLDOCTL3.ITRIM_DIGLDO during boot. 0x0: ADI_2_REFSYS:SOCLDOCTL3.ITRIM_DIGLDO = 0x0 0x1: ADI_2_REFSYS:SOCLDOCTL3.ITRIM_DIGLDO = 0x3 0x2: ADI_2_REFSYS:SOCLDOCTL3.ITRIM_DIGLDO = 0x5 0x3: ADI_2_REFSYS:SOCLDOCTL3.ITRIM_DIGLDO = 0x7 | RW | 0x0
15:12 | VTRIM_DIG | Value will be written to ADI_2_REFSYS:SOCLDOCTL1.VTRIM_DIG by FW during boot. | RW | 0xX
11:8 | VTRIM_COARSE | Value will be written to ADI_2_REFSYS:SOCLDOCTL1.VTRIM_COARSE by FW during boot. | RW | 0xX
7:0 | RCOSCHF_CTRIM | The boot FW will use this value as a trim target for the RCOSCHF cap trim. FW calculates the delta between current register bit field value of DDI_0_OSC:RCOSCHFCTL.RCOSCHF_CTRIM and this field. 1/16 of this delta value is added to DDI_0_OSC:RCOSCHFCTL.RCOSCHF_CTRIM in each loop of a total of 16. The 2 MSB bits of the value read and written from/to DDI_0_OSC:RCOSCHFCTL.RCOSCHF_CTRIM register bit field will be inverted by FW. | RW | 0xXX

### TOP:EFUSE:ANA_TRIM

Address offset | 0x0000 0030
Physical address | NA | Instance | EFUSE
Description | Note: Efuse row number = (Address Offset / 4)
Type | RW

Bits | Field Name | Description | Type | Reset
31:27 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text) | RW | 0x00
26:25 | BOD_BANDGAP_TRIM_CNF | Configuration of ROM boot FW trim algorithm for Bandgap and VDDS BOD. 0: ROM boot FW will disable all BOD reset sources except VDDS BOD followed by a sync to AON and then latch the trim target values for Bandgap and VDDS BOD in ANATOP. 1: ROM boot FW will disable all BOD reset sources followed by a sync to AON. Then the trim target values for Bandgap and VDDS BOD are latched in ANATOP. Then VDDS BOD is re-enabled followed by one sync to AON. 2: ROM boot FW will disable all BOD reset sources followed by a sync to AON. Then the trim target values for Bandgap and VDDS BOD are latched in ANATOP followed by a sync to AON. Then VDDS BOD is re-enabled followed by one sync to AON. 3: ROM boot FW will disable all BOD reset sources followed by a sync to AON. Then the trim target values for Bandgap and VDDS BOD are latched in ANATOP followed by two syncs to AON. Then VDDS BOD is re-enabled followed by one sync to AON. | RW | 0x1
24 | VDDR_ENABLE_PG1 | This value will be written to ADI_3_REFSYS:DCDCCTL2.TURNON_EA_SW by FW during boot. If value is 1 it will cause the ' trim-down VDDR_OK glitch fix' in PG2 to be bypassed and it will also cause the boot FW to include a delay of approx. 700 us after the global LDO trimming, if VDDR_TRIM < -2. | RW | 0
23 | VDDR_OK_HYS | Value will be written to ADI_3_REFSYS:DCDCCTL1.VDDR_OK_HYST by FW during boot. | RW | 0
22:21 | IPTAT_TRIM | Value will be written to ADI_3_REFSYS:DCDCCTL1.IPTAT_TRIM by FW during boot. | RW | 0x0
20:16 | VDDR_TRIM | Value will be written to ADI_3_REFSYS:DCDCCTL0.VDDR_TRIM by FW during boot. | RW | 0xXX
15:11 | TRIMBOD_INTMODE | Value will be written to ADI_3_REFSYS:REFSYSCTL1.TRIM_VDDS_BOD by FW during boot if AON_SYSCTL:PWRCTL.EXT_REG_MODE = 0. | RW | 0xXX
10:6 | TRIMBOD_EXTMODE | Value will be written to ADI_3_REFSYS:REFSYSCTL1.TRIM_VDDS_BOD by FW during boot if AON_SYSCTL:PWRCTL.EXT_REG_MODE = 1. | RW | 0xXX
5:0 | TRIMTEMP | Value will be written to ADI_3_REFSYS:REFSYSCTL3.TRIM_VBG by FW during boot. | RW | 0xXX