## DDI_0_OSC

Instance: DDI_0_OSC
Component: DDI_0_OSC
Base address: 0x400ca000

This is the DDI for the digital block that controls all the analog clock oscillators (OSC_DIG) and performs qualification of the clocks generated.

### TOP:DDI_0_OSC Register Summary

Register Name | Type | Register Width (Bits) | Register Reset | Address Offset | Physical Address
CTL0 | RW | 32 | 0x0000 0000 | 0x0000 0000 | 0x400C A000
CTL1 | RW | 32 | 0x0000 0000 | 0x0000 0004 | 0x400C A004
RADCEXTCFG | RW | 32 | 0x0000 0000 | 0x0000 0008 | 0x400C A008
AMPCOMPCTL | RW | 32 | 0x0000 0000 | 0x0000 000C | 0x400C A00C
AMPCOMPTH1 | RW | 32 | 0x0000 0000 | 0x0000 0010 | 0x400C A010
AMPCOMPTH2 | RW | 32 | 0x0000 0000 | 0x0000 0014 | 0x400C A014
ANABYPASSVAL1 | RW | 32 | 0x0000 0000 | 0x0000 0018 | 0x400C A018
ANABYPASSVAL2 | RW | 32 | 0x0000 0000 | 0x0000 001C | 0x400C A01C
ATESTCTL | RW | 32 | 0x0000 0000 | 0x0000 0020 | 0x400C A020
ADCDOUBLERNANOAMPCTL | RW | 32 | 0x0000 0000 | 0x0000 0024 | 0x400C A024
XOSCHFCTL | RW | 32 | 0x0000 0000 | 0x0000 0028 | 0x400C A028
LFOSCCTL | RW | 32 | 0x0000 0000 | 0x0000 002C | 0x400C A02C
RCOSCHFCTL | RW | 32 | 0x0000 0000 | 0x0000 0030 | 0x400C A030
STAT0 | RO | 32 | 0x0000 0000 | 0x0000 0034 | 0x400C A034
STAT1 | RO | 32 | 0x0000 0000 | 0x0000 0038 | 0x400C A038
STAT2 | RO | 32 | 0x0000 0000 | 0x0000 003C | 0x400C A03C

### TOP:DDI_0_OSC Register Descriptions

### TOP:DDI_0_OSC:CTL0

Address offset | 0x0000 0000
Physical address | 0x400C A000 | Instance | DDI_0_OSC
Description | Control 0 Controls various clock source selects
Type | RW

Bits | Field Name | Description | Type | Reset
31 | XTAL_IS_24M | Set based on the accurate high frequency XTAL or BAW. 0: 48MHz XTAL or 48MHz BAW 1: 24MHz XTAL
Value | ENUM name | Description
0 | 48M | 48MHz
1 | 24M | 24MHz
| RW | 0
30 | DOUBLER_BYPASS_CTL | When this bit is set, the XOSC_HF doubler is bypassed - i.e. the XOSC_HF clock is not double but is instead routed to the output of the doubler. 0: Hardware controls doubler bypass. 1: Doubler is bypassed The hardware will bypass the doubler when a 48MHz XTAL is connected to XOSC_HF. | RW | 0
29 | BYPASS_XOSC_LF_CLK_QUAL | Bypass XOSC_LF clock gating. Extremely useful not to get glitch on sclk_lf. Should be '1' once sclk_lf source is switched to xosc_lf. 0: Disable 1: Enable | RW | 0
28 | BYPASS_RCOSC_LF_CLK_QUAL | Override enable of clock gate that gates RCOSC_LF clock being fed to GF MUX. Extremely useful not to get glitch on sclk_lf. Should be '1' once sclk_lf source is switched to rcosc_lf 0: Disable 1: Enable | RW | 0
27:26 | DOUBLER_START_DURATION | Controls the Doubler startup duration. This is the time that determines when the doubler output is good from the start of the doubler enable sequence. The time the doubler has to lock is determined by this bitfield and also DOUBLER_RESET_DURATION. DOUBLER_RESET_DURATION determines when reset ends - i.e. locking can start. This field determines when locking must complete. The allowable lock time is this setting minus the DOUBLER_RESET_DURATION setting. 0: 10 us minumum duration 1: 12 us minimum duration 2: 14 us minimum duration 3: 16 us minimum duration | RW | 0x0
25 | DOUBLER_RESET_DURATION | Controls the doubler reset duration - the time that DOULBER_RESET and DOUBLER_EN are both active in the beginning of the doubler startup sequence. 0: 2 us minimum duration 1: 3 us minimum duration | RW | 0
24 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text) | RW | 0
23 | Reserved |  | RW | 0
22 | FORCE_KICKSTART_EN | Kickstart the rcosc_hf oscillator if the high-frequency system clock (sclk_hf) is enabled while the OSC_DIG is in the HOLD state (no high frequency oscillator is enabled), and the source of sclk_lf is the xosc_hf. 0: Kickstart disabled 1: Kickstart enable. The sclk_hf source is selected by SCLK_HF_SRC_SEL. It is needed to ensure there are no system hangs on very rapid wakeup request following a powerdown request. | RW | 0
21 | Reserved |  | RW | 0
20 | Reserved |  | RW | 0
19 | Reserved |  | RW | 0
18 | Reserved |  | RW | 0
17 | Reserved |  | RW | 0
16 | ALLOW_SCLK_HF_SWITCHING | 0: Default - Switching of HF clock source is disabled . 1: Allows swtiching of sclk_hf source. Provided to prevent switching of the SCLK_HF source when running from flash (a long period during switching could corrupt flash). When sclk_hf switching is disabled, a new source can be started when SCLK_HF_SRC_SEL is changed, but the switch will not occur until this bit is set. This bit should be set to enable clock switching after STAT0.PENDINGSCLKHFSWITCHING indicates the new HF clock is ready. When switching completes (also indicated by STAT0.PENDINGSCLKHFSWITCHING) sclk_hf switching should be disabled to prevent flash corruption. Switching should not be enabled when running from flash. | RW | 0
15 | Reserved |  | RW | 0
14 | BAW_MODE_EN | 0: Selects dtst_osc_clkin when OSC_DIG is bypassed 1: Selects internal OSC_DIG _clk (RCOSC_HF or XOSC_HF derived 2 MHz) | RW | 0
13 | Reserved |  | RW | 0
12 | RCOSC_LF_TRIMMED | Determines the accuracy at which RCOSC_LF_CLK is qualified. The RCOSC_LF_CLK is measured against the oscdig_clk (2MHz). This bit determines the acceptable ratio of oscdig_clk periods per RCOSC_LF period. 0: RCOSC_LF_CLK is good if 6-200 2MHz periods per one RCOSC_LF period (intended for an untrimmed RCOSC_LF). 1: RCOSC_LF_CLK is good if 55-67 2MHz periods per one RCOSC_LF period (intended for a trimmed RCOSC_LF). | RW | 0
11 | XOSC_HF_POWER_MODE | XOSC/AMPCOMP mode. 0: High Power Mode (HPM) 1: Low Power Mode (LPM) Sets the XOSC_HF Power mode. If in the HPM_UPDATE (LPM_UPDATE) state, the AMPCOMP FSM will transition to the (HPM_UPDATE) LPM_UPDATE state when this bit is set to a '1' ('0). If set to LPM when the XOSC_HF is started, the XOSC_HF will startup in High-Power Mode then transition to Low-Power Mode. STAT1.RAMPSTATE indicates the current FSM State. It can be polled to see that a transtion to the desired power mode has completed. Note well that XOSC_HF settings in AMPCOMPCTL, RADCEXTCFG, AMPCOMPTH1, and AMPCOMPTH2 must be set correctly, and are usually set by FW. | RW | 0
10 | XOSC_LF_DIG_BYPASS | Bypass XOSC_LF and use the digital input clock from AON for the xosc_lf clock.. 0: Use 32kHz XOSC as xosc_lf clock source 1: Use digital input (from AON) as xosc_lf clock source. This bit will only have effect when SCLK_LF_SRC_SEL is selecting the xosc_lf as the sclk_lf source. The muxing performed by this bit is not glitch free. The following procedure should be followed when changing this field to avoid glitches on sclk_lf.. 1) Set SCLK_LF_SRC_SEL to select any source other than the xosc_lf clock source. 2) Set or clear this bit to bypass or not bypass the xosc_lf. 3) Set SCLK_LF_SRC_SEL to use xosc_lf. It is recommended that either the rcosc_hf or xosc_hf (whichever is currently active) be selected as the source in step 1 above. This provides a faster clock change. | RW | 0
9 | CLK_LOSS_EN | Enable clock loss circuit and hence the indicators to system controller. Checks both SCLK_HF and SCLK_LF clock loss indicators. 0: Disable 1: Enable Clock loss detection should be disabled when changing the sclk_lf source. STAT0.SCLK_LF_SRC can be polled to determine when a change to a new sclk_lf source has completed. | RW | 0
8:7 | ACLK_TDC_SRC_SEL | Source select for aclk_tdc. 00: rcosc_hf_clk 01: rcosc_hf_d24m_clk 10: xosc_hf_d24m_clk 11: Not valid | RW | 0x0
6:5 | ACLK_REF_SRC_SEL | Source select for aclk_ref 00: rcosc_hf_dlf_clk 01: xosc_hf_dlf_clk 10: rcosc_lf_clk 11: xosc_lf_clk | RW | 0x0
4 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text) | RW | 0
3:2 | SCLK_LF_SRC_SEL | Source select for sclk_lf
Value | ENUM name | Description
0x0 | RCOSCHFDLF | rcosc_hf_dlf_clk. Low frequency clock derived from High Frequency RCOSC
0x1 | XOSCHFDLF | xosc_hf_dlf_clk. Low frequency clock derived from High Frequency XOSC
0x2 | RCOSCLF | rcosc_lf_clk Low frequency RCOSC
0x3 | XOSCLF | xosc_lf_clk Low frequency XOSC
| RW | 0x0
1 | SCLK_MF_SRC_SEL | Source select for sclk_mf
Value | ENUM name | Description
0 | RCOSCHFDMF | rcosc_hf_dmf_clk Medium frequency clock derived from high frequency RCOSC
1 | XCOSCHFDMF | xosc_hf_dmf_clk Medium frequency clock derived from high frequency XOSC or BAW.
| RW | 0
0 | SCLK_HF_SRC_SEL | Source select for sclk_hf
Value | ENUM name | Description
0 | RCOSC | High frequency RCOSC clk
1 | XOSC | High frequency XOSC or BAW clk (use BAW when BAW_MODE_EN = 1
| RW | 0

### TOP:DDI_0_OSC:CTL1

Address offset | 0x0000 0004
Physical address | 0x400C A004 | Instance | DDI_0_OSC
Description | Comtrol 1 This register contains various OSC_DIG configuration
Type | RW

Bits | Field Name | Description | Type | Reset
31:28 | Reserved | Internal | RW | 0x0
27:24 | Reserved | Internal | RW | 0x0
23 | Reserved | Internal | RW | 0
22:18 | RCOSCHFCTRIMFRACT | Sets the fractional tuning of the RCOSC_HF capacitor trim. This field only has an effect if RCOSC_HF fractional trim is enabled via RCOSCHFCTRIMFRACT_EN. This field sets the duty cycle of the signal which enables the capacitor for fractional trimming. The field is an unsigned integer value. The duty cycle is RCOSCHFCTRIMFRACT/32. The fractional trim capacitor is 2X the size of the capacitors controlled by RCOSCHFCTL.RCOSCHF_CTRIM. The effective additional capacitance added to the RCOSC_HF is equal to the duty cycle times 2X. E.g. If this field is set to 16, then the duty cycle is 50% so the effective trim adds one capacitor to the RCOSC_HF capacitance. Setting this field to 8 gives a duty cycle of 25% which effectively adds 1/2 of a capacitor. The value of this field is calibrated and set via FW. This field should only be changed when the fractional tuning is disabled or when the RCOSC_HF is off. | RW | 0x00
17 | RCOSCHFCTRIMFRACT_EN | This field enables the fractional trimming of the RCOSC_HF captrim. 0: Disabled 1: Enabled When Fractional Trimming is enabled, the effective capacitance for tuning the RCOSC_HF frequency can be fractionally increased/decreased by defining the duty cycle of the signal that enables the RCOSC_HF Fractional Tuning Capacitor. The duty cycle is controlled by RCOSCHFCTRIMFRACT. | RW | 0
16:2 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text) | RW | 0x0000
1:0 | XOSC_HF_FAST_START | Set precharge duration of fast startup of the XOSC_HF 00: Disable 01: 3 us 10: 5 us 11: 8 us This field enables and sets the duration of the XOSC_HF fast startup mode. This field will be set by firmware based on XTAL characteristics and other considerations. | RW | 0x0

### TOP:DDI_0_OSC:RADCEXTCFG

Address offset | 0x0000 0008
Physical address | 0x400C A008 | Instance | DDI_0_OSC
Description | RADC External Configuration
Type | RW

Bits | Field Name | Description | Type | Reset
31:22 | HPM_IBIAS_WAIT_CNT | AMPCOMP FSM waits for this count of OSC_DIG clock cycles in order to compensate the effect of slow crystal response. HPM_IBIAS_WAIT_CNT*0.5 us is absolute wait time and should be close to XTAL's response time towards ibias/cap change | RW | 0x000
21:16 | LPM_IBIAS_WAIT_CNT | FSM waits for LPM_IBIAS_WAIT_CNT clock cycles in the IBIAS_INCREMENT state in order to compensate slow response of the xtal. Typical values = 64. | RW | 0x00
15:12 | IDAC_STEP | IDAC step size that will be used in IBIAS_CAP_UPDATE state. xosc_hf_idac is incremented IDAC_STEP times for each iteration of the loop that is performed during IBIAS_CAP_UPDATE. This setting is XTAL dependent and applied by FW. | RW | 0x0
11:6 | RADC_DAC_TH | RADC threshhold value when in comparator mode. Used when RADC_EXTERNAL_USE_EN = 1. RADC_DAC_TH is an unsigned integer input to the DAC that sets the voltage that goes to the compare input to the RADC comparator. The DAC voltage is ~ 0.0153*RADC_DAC_TH + 0.00765. | RW | 0x00
5 | RADC_MODE_IS_SAR | RADC mode when RADC_EXTERNAL_USE_EN = 1. 0: Comparator mode 1: SAR mode | RW | 0
4 | RADC_START_CONV | Start conversion signal when RADC_EXTERNAL_USE_EN = 1. | RW | 0
3 | Reserved | Internal | RW | 0
2 | Reserved | Internal | RW | 0
1 | DDI_RADC_CLRZ | Active low clrz for RADC_DIG. 0: Reset digital logic in the RADC. 1: Release reset of digital logic in RADC. Used when RADC_EXTERNAL_USE_EN = 1. | RW | 0
0 | Reserved | Internal | RW | 0

### TOP:DDI_0_OSC:AMPCOMPCTL

Address offset | 0x0000 000C
Physical address | 0x400C A00C | Instance | DDI_0_OSC
Description | Amplitude Compensation Control
Type | RW

Bits | Field Name | Description | Type | Reset
31 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text) | RW | 0
30 | AMPCOMP_REQ_MODE | RADC mode during ampcomp_req from AON. FSM forces ADC to be in selected mode during ampcomp request (during amplitude maintainance). 0: Comparator 1: 1-time SAR mode This bit is not used during the ramping up or transitioning from one mode to other. | RW | 0
29:28 | AMPCOMP_FSM_UPDATE_RATE | Run all XOSC input updates at 2M/1M/500K/250K. 00: 2 MHz 01: 1 MHz 10: 500KHz 11: 250KHz
Value | ENUM name | Description
0x0 | 2MHZ | 2 MHz ampcomp rate
0x1 | 1MHZ | 1 MHz ampcomp rate
0x2 | 500KHZ | 500 kHz ampcomp rate
0x3 | 250KHZ | 250 kHz ampcomp rate
| RW | 0x0
27 | AMPCOMP_SW_CTRL | 0: OSC_DIG HW controls enabled amplitude compensation. 1: Give control to the software. SW is now responsible for start of ampcomp fsm. Requires that AMPCOMP_SW_EN = 1. | RW | 0
26 | AMPCOMP_SW_EN | 0: Default 1: Starts ampcomp FSM Used when AMPCOMP_SW_CTRL = 1. | RW | 0
25 | XOSC_HF_HP_BUF_SW_CTRL | This field give SW control of the enabling of the XOSC_HF or BAW clock to the synth. 0: OSC_DIG HW controls enabling the clock buffer to the synthesizer. 1: SW control enabling the clock buffer to the synthesizer. If this field = 1,. then XOSC_HF_HP_BUF_SW_EN enables/disables the clock to the synthesizer. The user may find this useful if the synth clock is generated externally by a TXO on X48P pin. | RW | 0
24 | XOSC_HF_HP_BUF_SW_EN | If XOSC_HF_HP_BUF_SW_CTRL = 0, then this bit has no effect. If XOSC_HF_HP_BUF_SW_CTRL = 1, this field controls the enable of the clock to the synthesizer. 0: Disable clock to the synthesizer. 1: Enable clock to the synthesizer. In XOSC_HF mode, this field activates the "high power" buffer in the XOSC_HF module to drive the clock to the synthesizer. In BAW mode, this field activates the BAW Clock Good signal to the BAW Module which enables the clock buffer that drives the clock to the synthesizer. The user may find this useful if the synth clock is generated externally by a TXO on X48P pin. | RW | 0
23:20 | IBIAS_OFFSET | Offset (minimum) value of XOSC IBIAS trim. IBIAS trim value would always be greater than or equal to this offset in both HPM and **LPM.** The value is an unsigned integer. The setting is XTAL dependent and set by FW. | RW | 0x0
19:16 | IBIAS_INIT | Value of XOSC IBIAS trim above the IBIAS_OFFSET for HPM. During ramp-up, IBIAS trim is set initially to the max value and then decreased to IBIAS_OFFSET + IBIAS_INIT on the way to HPM_UPDATE. The value is an unsigned integer. The setting is XTAL dependent and set by FW. | RW | 0x0
15:8 | LPM_IBIAS_WAIT_CNT_FINAL | FSM waits for LPM_IBIAS_WAIT_CNT_FINAL clock cycles in the IDAC_DECREMENT_WITH_MEASURE state in order to compensate slow response of the xtal. The value is an unsigned integer. The setting is XTAL dependent and set by FW. | RW | 0x00
7:4 | CAP_STEP | Step size of XOSC capasitor trim (both Q1 and Q2) during XOSC mode transition. Can vary from 6 to 12. Other values are possible but not valid. The value is an unsigned integer. The setting is XTAL dependent and set by FW. | RW | 0x0
3:0 | IBIASCAP_HPTOLP_OL_CNT | During a HPM to LPM transition a HW loop is entered that modifies cap, ibias and iDAC trims. This field sets the number of loop iterations. In each iteration the cap trim is decremented CAP_STEP times, then the iDAC trim is incremented RADCEXTCFG.IDAC_STEP times, and finally the ibias trim is decremented by 1. After IBIASCAP_HPTOLP_OL_CNT iterations, the cap trim is decremented to 0 (if greater than 0) and the iDAC trim is incremented to 96 (if less than 96). The setting of this field is XTAL dependant and set by FW. | RW | 0x0

### TOP:DDI_0_OSC:AMPCOMPTH1

Address offset | 0x0000 0010
Physical address | 0x400C A010 | Instance | DDI_0_OSC
Description | Amplitude Compensation Threashold 1 This register contains various threshhold values for amplitude compensation algorithm
Type | RW

Bits | Field Name | Description | Type | Reset
31:26 | Reserved |  | RW | 0x00
25:24 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text) | RW | 0x0
23:18 | HPMRAMP3_LTH | HPM Ramp3 low amplitude threshhold. In HPM_UPDATE, if amplitude < HPMRAMP3_LTH increase iDAC trim, unless max trim has been reached. In IDAC_DECREMENT_WITH_MEASURE, exit the state if amplitude < HPMRAMP3_LTH. The value is an unsigned integer. The settiing is XTAL dependent and set by FW. | RW | 0x00
17:16 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text) | RW | 0x0
15:10 | HPMRAMP3_HTH | In HPM_RAMP3, if amp < HPMRAMP3_HTH then move to HPM_UPDATE. In HPM_UPDATE, if amplitude > HPMRAMP3_HTH decrease iDAC trim, unless min trim has been reached. In IDAC_DECREMENT_WITH_MEASURE, exit the state if amplitude < HPMRAMP3_HTH. The value is an unsigned integer. The settiing is XTAL dependent and set by FW. | RW | 0x00
9:6 | IBIASCAP_LPTOHP_OL_CNT | During a LPM to HPM transition a HW loop is entered that modifies cap, and ibias trims. This field sets the number of loop iterations. In each iteration the cap trim is incremented AMPCOMPCTL.CAP_STEP times, then the ibias trim is decremented once. After IBIASCAP_LPTOHP_OL_CNT iterations, the cap trim is incremented until the trim is equal to the setting defined by ANABYPASSVAL1.XOSC_HF_ROW_Q12 and ANABYPASSVAL1.XOSC_HF_COLUMN_Q12. The value is an unsigned integer. The settiing is XTAL dependent and set by FW. | RW | 0x0
5:0 | HPMRAMP1_TH | HPM Ramp1 amplitude threshhold. Wait in HPM_RAMP1 until amplitude > HPMRAMP1_TH. The value is an unsigned integer. The settiing is XTAL dependent and set by FW. The XOSCHF clock to the synth will be released after the amplitude of XOSC_HF passes HPMRAMP1_TH, as is the DOUBLER clock. | RW | 0x00

### TOP:DDI_0_OSC:AMPCOMPTH2

Address offset | 0x0000 0014
Physical address | 0x400C A014 | Instance | DDI_0_OSC
Description | Amplitude Compensation Threashold 2 This register contains various threshhold values for amplitude compensation algorithm.
Type | RW

Bits | Field Name | Description | Type | Reset
31:26 | LPMUPDATE_LTH | LPM Update low amplitude threshhold when RADC is in SAR mode. In the LPM_UPDATE state and RADC is in SAR Mode, increment iDAC trim (unless at max) if amplitude < LPMUPDATE_LTH. The value is an unsigned integer. The settiing is XTAL dependent and set by FW. | RW | 0x00
25:24 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text) | RW | 0x0
23:18 | LPMUPDATE_HTH | LPM update high amplitude threshhold when RADC is in SAR mode. In the LPM_UPDATE state and RADC is in SAR Mode, decrement iDAC trim (unless at min) if amplitude > LPMUPDATE_HTH. The value is an unsigned integer. The settiing is XTAL dependent and set by FW. | RW | 0x00
17:16 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text) | RW | 0x0
15:10 | ADC_COMP_AMPTH_LPM | Low Power Mode Amplitude Threshold for Comparator mode. When ADC is in comparator mode, this field sets the amplitude threshold used during the LPM_UPDATE state (Low Power Mode amplitude maintenance). The xosc_hf amplitude is periodically compared against the threshold. The iDAC bias is decremented if the amplitude is greater than the threshold, otherwise it is incremented. The value is an unsigned integer. The settiing is XTAL dependent and set by FW. | RW | 0x00
9:8 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text) | RW | 0x0
7:2 | ADC_COMP_AMPTH_HPM | High Power Mode Amplitude Threshold for Comparator mode. When ADC is in comparator mode, this field sets the amplitude threshold used during the HPM_UPDATE state (High Power Mode amplitude maintenance). The xosc_hf amplitude is periodically compared against the threshold. The iDAC bias is decremented if the amplitude is greater than the threshold, otherwise it is incremented. The value is an unsigned integer. The settiing is XTAL dependent and set by FW. | RW | 0x00
1:0 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text) | RW | 0x0

### TOP:DDI_0_OSC:ANABYPASSVAL1

Address offset | 0x0000 0018
Physical address | 0x400C A018 | Instance | DDI_0_OSC
Description | Analog Bypass Values 1 Several signals generated within OSC_DIG can be bypassed. I.e. the signals can be controlled by software via writes to ANABYPASSVAL1 and ANABYPASSVAL2. Bypass is enabled via an OSC_DIG module input signal (bypass_oscdig) driven by the AON_WUC TAP controller. Using the OSC_DIG bypass is only practical if you have intimate knowledge of the oscilator design.
Type | RW

Bits | Field Name | Description | Type | Reset
31 | Reserved | Internal | RW | 0
30 | Reserved | Internal | RW | 0
29 | Reserved | Internal | RW | 0
28 | Reserved | Internal | RW | 0
27 | Reserved | Internal | RW | 0
26:20 | Reserved | Internal | RW | 0x00
19:16 | XOSC_HF_ROW_Q12 | This field is used whether or not OSC_DIG is bypassed. When OSC_DIG is not bypassed this setting determines the cap_init_row value used in the High-Power Mode. This value is XTAL dependent and set by FW. When OSC_DIG is bypassed this setting determines the xosc_hf capacitor bank row value The xosc_hf capacitor bank uses a row/column encoding. The row value is a thermometer encoded. | RW | 0x0
15:0 | XOSC_HF_COLUMN_Q12 | This field is used whether or not OSC_DIG is bypassed. When OSC_DIG is not bypassed this setting determines the cap_init_column value used in HPM. This value is XTAL dependent and set by FW. When OSC_DIG is bypassed this setting determines the target xosc_hf capacitor bank column value. The xosc_hf capacitor bank uses a row/column encoding. The column value is a thermometer encoded. | RW | 0x0000

### TOP:DDI_0_OSC:ANABYPASSVAL2

Address offset | 0x0000 001C
Physical address | 0x400C A01C | Instance | DDI_0_OSC
Description | Internal Register. Customers can control this through TI provided API
Type | RW

Bits | Field Name | Description | Type | Reset
31 | Reserved | Internal | RW | 0
30 | Reserved | Internal | RW | 0
29 | Reserved | Internal | RW | 0
28 | Reserved | Internal | RW | 0
27 | Reserved | Internal | RW | 0
26 | Reserved | Internal | RW | 0
25:14 | Reserved | Internal | RW | 0x000
13:0 | XOSC_HF_IBIASTHERM | Internal | RW | 0x0000

### TOP:DDI_0_OSC:ATESTCTL

Address offset | 0x0000 0020
Physical address | 0x400C A020 | Instance | DDI_0_OSC
Description | Analog Test Control
Type | RW

Bits | Field Name | Description | Type | Reset
31:30 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text) | RW | 0x0
29 | SCLK_LF_AUX_EN | Enable 32 kHz clock to SOC_AUX. | RW | 0
28:20 | ATEST_OSC_CTRL | Select lines for top-level OSC_TOP ATEST mux. There are two outputs (ATEST1 and ATEST0) and each has an independently controlled mux. The muxes use a one-hot encoding. Bits 23:20 select the source for the ATEST0 output as follows: 0x0: Not driven 0x1: OSCLFANA to ATEST0 0x2: OSCHFANA to ATEST0 0x4: RADC to ATEST0 0x8: Doubler to ATEST0 Bits 28:24 select the source for the ATEST1 output as follows: 0x00: Not driven 0x01: OSCLFCLK to ATEST1 (output from OSCLF lower-level mux. ATESTLF_OSC_1P2V controls the lower-level mux) 0x02: OSCHFCLK to ATEST1 (ATEST_OSC_HF_SEL) 0x04: RADC to ATEST1 0x08: Doubler to ATEST1 0x10: Doubler clock to ATEST1 ATEST is intended for debug and characterization. Programming ATEST correctly requires that paths are setup in the correct order. Incorrectly programmed paths can short signals together or to ground. A higher level of muxing (between OSC_TOP and other analog modules) and enabling exists and is controlled by ADI_4_AUX:ATEST. See the ATEST Design Memo for details. | RW | 0x000
19:16 | ATEST_OSC_HF_SEL | Selects the source for high frequency oscillator test outputs. Note, does not control muxing of BAW related test signals. These are controled by ATESTLF_OSC_1P2V and ATESTLF_OSC_1P8V. Controls two test outputs ATEST_OSCHF_CLCKOUT_1P8V and ATEST_OSCHF_ANA_OUT. 0x0: ATEST_OSCHF_CLKOUT_1P8V is XOSC_HF LP clock output. ATEST_OSCHF_ANA_OUT is Not Driven. 0x1: ATEST_OSCHF_CLKOUT_1P8V is Not Driven. ATEST_OSCHF_ANA_OUT is XOSC_HF ATEST0 output. 0x2: ATEST_OSCHF_CLKOUT_1P8V is RCOSC_HF clock output. ATEST_OSCHF_ANA_OUT is Not Driven. 0x3: ATEST_OSCHF_CLKOUT_1P8V is RCOSC_HF clock output. ATEST_OSCHF_ANA_OUT is RCOSC_HF ATEST0 output. 0x4: ATEST_OSCHF_CLKOUT_1P8V is XOSC_HF HP clock output ATEST_OSCHF_ANA_OUT is Not Driven 0x5: ATEST_OSCHF_CLKOUT_1P8V is XOSC_HF HP clock output ATEST_OSCHF_ANA_OUT is XOSC ATEST0 output | RW | 0x0
15:12 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text) | RW | 0x0
11:10 | Reserved | Internal field controlled by TI provided startup code | RW | 0x0
9:8 | Reserved | Internal field controlled by TI provided startup code | RW | 0x0
7 | ATESTLF_RCOSCLF_IBIAS_TRIM | Set high to increase the bias current to RCOSC_LF by 25 nA. Nominal value is 50 nA. With this bit enabled current is 75 nA. | RW | 0
6 | ATESTLF_UDIGLDO_IBIAS_TRIM | Set high to enable an extra 25 nA of bias current to uDIGLDO (100% increase from nominal). | RW | 0
5 | ATESTLF_SOXAUX_IBIAS_TRIM | Set high to enable extra 25 nA to SOCAUX (100% increase from nominal). | RW | 0
4:3 | ATESTLF_OSC_1P2V | Select 1.2V output test clock to drive the ATEST1 signal. 00: RCOSC_LF clock 01: BAW HF clock 10: XOSC_LF clock This field only selects the source to be driven. The output is enabled to drive ATEST1 by ATESTLF_EN. | RW | 0x0
2:1 | ATESTLF_OSC_1P8V | Select the 1.8V test output to drive ATEST0. 00: BAW analog test 01: XOSC_LF analog test 10: NANOAMP_BIAS test current 11: RCOSC_LF VDD_LOCAL This field only selects the source to be driven. The output is enabled to drive ATEST0 by ATESTLF_EN. | RW | 0x0
0 | ATESTLF_EN | Enables the 1p8V test output selected by ATESTLF_OSC_1P8V. 0: Disable 1: Enable | RW | 0

### TOP:DDI_0_OSC:ADCDOUBLERNANOAMPCTL

Address offset | 0x0000 0024
Physical address | 0x400C A024 | Instance | DDI_0_OSC
Description | ADC Doubler Nanoamp Control
Type | RW

Bits | Field Name | Description | Type | Reset
31 | Reserved |  | RW | 0
30:25 | Reserved |  | RW | 0x00
24 | NANOAMP_BIAS_ENABLE | Internal field controlled by TI provided startup code | RW | 0
23 | SPARE23 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior | RW | 0
22 | DBLR_ATEST_SELECT | Analog test select for Doubler 0: VCTRL Output (ATEST0=VCTRL, ATEST1=DOUBLER_RST) 1: Bias Output (ATEST0=VBP, ATEST1=VBN) Used when DBLR_ATEST_ENABLE = 1 DOUBLER_RST allows control of **DOUBLER RST** signal via ATEST | RW | 0
21 | DBLR_ATEST_ENABLE | Enable ATEST for DBLR. If enabled used DBLR_ATEST_SELECT to set ATEST bit. 0: Disable 1: Enable | RW | 0
20 | DBLR_TOOHI_MODE | Not used. | RW | 0
19 | DBLR_LOOP_FILTER_CAP | Loop filter cap 0: 100% Nominal (17.5 pF) 1: 83% Nominal; (14.5 Pf) | RW | 0
18:17 | DBLR_LOOP_FILTER_RESET_VOLTAGE | Loop filter reset voltage 10: 0.533*VDD = 0.666V 11: 0.615*VDD = 0.768V 00: 0.667*VDD = 0.833V 01: 0.800*VDD = 1.000V | RW | 0x0
16 | DOUBLER_BIAS_DIS | Disable dummy bias current. 0: Dummy bias current on (Default) 1: Dummy bias current off | RW | 0
15:10 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text) | RW | 0x00
9 | RADC_BIAS_DIS | Disable dummy bias current. 0: Dummy bias current on (Default) 1: Dummy bias current off | RW | 0
8:7 | ADC_ATEST_SRC | Select ATEST0 muxed output from RADC mux. Mux is enabled by ADC_EN_ATEST. 0x0: Output of DAC - indicates if the current compare input is greater than the reference 0x1: COMP_IN (Comparator input signal after filtering and sample-hold) 0x2: FILTER_OUT (Comparator input signal after filtering - not sample-hold) 0x3: DAC_REF (DAC Reference Voltage - input is compared to this) | RW | 0x0
6 | ADC_EN_ATEST | Enable ATEST0 mux whose output is selected by the ADC_ATEST_SRC bitfield. 0: Disable 1: Enable | RW | 0
5 | ADC_SH_MODE_EN | Enable S&H Mode 0: Disable 1: Enable | RW | 0
4 | ADC_SH_VBUF_EN | Enable S&H voltage buffer mode 0: Disable 1: Enable | RW | 0
3:2 | ADC_MUX_SEL | Select line for 4-to-1 mux that feeds ADC input. Default is '00' Selects OSC_DIG input 00: Peak detector output 01: Vtemp 10: ATEST0 11: ATEST1 Must be programmed to select the Peak detector output if xosc_hf is enabled so that amplitude compensation can be performed correctly so the clock is not lost. | RW | 0x0
1:0 | ADC_IREF_CTRL | Select RADC IBIAS source. 00: Use V2I 10: Connect external IREF to DAC 01: Use IREF 2uA from REFSYS for DAC 11: Reserved | RW | 0x0

### TOP:DDI_0_OSC:XOSCHFCTL

Address offset | 0x0000 0028
Physical address | 0x400C A028 | Instance | DDI_0_OSC
Description | XOSCHF Control
Type | RW

Bits | Field Name | Description | Type | Reset
31:12 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text) | RW | 0x0 0000
11 | HPBUFF_BIAS_DIS | Disable dummy bias current. 0: Dummy bias current on (Default) 1: Dummy bias current off | RW | 0
10 | PEAKDET_BIAS_DIS | Disable dummy bias current. 0: Dummy bias current on (Default) 1: Dummy bias current off | RW | 0
9:8 | PEAK_DET_ITRIM | Adjust Ibias trim of peak detector 00: 16 uA (default) 01: 20 uA 10: 24 uA 11: 28 uA This value is XTAL dependent and set by FW. | RW | 0x0
7 | HP_ALT_BIAS | Improve phase noise and reduce power consumption at the cost of reduced supply rejection. 0: Disable 1: Enable | RW | 0
6 | BYPASS | Bypass XOSC_HF core and pass through external clock from X48P. | RW | 0
5 | TESTMUX_EN | Enable XOSC_HF ATEST Outputs 0: XOSC_HF ATEST outputs disabled 1: XOSC_HF ATEST outputs enabled. When enabled, the XOSC_HF COREREG bias current can be connected to drive ATEST0, and the HP Buffer clock or LP Buffer clock can be connected to drive ATEST1. This enable causes the XOSC_HF to drive the ATEST signals to a mux controlled by ATESTCTL.ATEST_OSC_HF_SEL. To drive these signals further on to the ATEST outputs, that mux must be programmed to select these inputs. | RW | 0
4:2 | HP_BUF_ITRIM | Adjust Ibias trim for HP buffer. 0x4: Min (16 uA) 0x0: Default (64 uA) 0x3: Max (128 uA) This field uses a 2's complement encoding. This value is XTAL dependent and set by FW. | RW | 0x0
1:0 | LP_BUF_ITRIM | Adjust Ibias trim for LP buffer. 01: Min (700 nA) 00: Default (900 nA) 11: 1 step up (1.1 uA) 10: Max (2.0 uA) This value is XTAL dependent and set by FW | RW | 0x0

### TOP:DDI_0_OSC:LFOSCCTL

Address offset | 0x0000 002C
Physical address | 0x400C A02C | Instance | DDI_0_OSC
Description | Low Frequency Oscillator Control
Type | RW

Bits | Field Name | Description | Type | Reset
31:27 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text) | RW | 0x00
26 | XOSCLF_BUFFER_TRIM | Set high to double current mirror ratio in XOSCLF_LPBUFF (from 25 nA to 50 nA). Not normally used. | RW | 0
25 | XOSCLF_TESTMUX_EN | This enables ATEST0 and ATEST1 outputs from xosclf. 0: Diable (Default) 1: Enable This must be active to see the xosc_lf clock if it is selected by ATESTCTL.ATESTLF_OSC_1P2V onto ATEST1. This must be active to see the xosc_lf core regulator bias current on ATEST0. | RW | 0
24 | Reserved |  | RW | 0
23:22 | XOSCLF_REGULATOR_TRIM | Trims resistor in constant gm bias 00: Default (225 k), 10: Min (425k), 01: Max (125k), 11: 1 step more than min (325k) This value is XTAL dependent and set by FW. | RW | 0x0
21:18 | XOSCLF_CMIRRWR_RATIO | Adjust current mirror ratio into osc core 0x8: Min 0x0: Default 0x7: Max This field uses a 2's complement encoding. This value is XTAL dependent and set by FW | RW | 0x0
17 | XOSCLF_ANA_AMP_CTRL | Disables analog amplitude control 0: Enabled 1: Disabled | RW | 0
16 | XOSCLF_RXTX_MODE | Enables xosc_lf high-power buffer and disables the low-power-buffer. The high-power buffer provides better phase-noise but the use model doesn't require high performance of the xosc_lf. If the xosc_lf XTAL is not populated, an external clock can be driven on the xosc_lf_q1 pin to provide an external 32KHz source. This bit must be set to '1' to use this method. I.e. the external source must pass throught the xosc_lf high-power buffer. Note: This is a different method of providing a 32KHz external clock than the method enabled by CTL0.XOSC_LF_DIG_BYPASS The low power buffer is the buffer of choice and the use-model is that it is on whenever the xosc_lf is used. The high-power buffer is only expected to be used for the external clock. | RW | 0
15:14 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text) | RW | 0x0
13:12 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text) | RW | 0x0
11 | RCOSCLF_VDD_LOCAL_TRIM | Not used. | RW | 0
10 | RCOSCLF_LOCAL_ATEST_EN | Enable RCOSC_LF ATEST Outputs 0: RCOSC_LF ATEST outputs disabled 1: RCOSC_LF ATEST outputs enabled. When enabled, the RCOSC_LF 0P7V local supply and the RCOSC_LF clock can be connected to drive ATEST0 and ATEST1 (respectively). This enable causes the RCOSC_LF to drive the ATEST signals to muxes that do further selection. One mux selects the clock on ATEST1 and it is controled by ATESTCTL.ATESTLF_OSC_1P2V. The other mux selects the data and is controlled by ATESTCTL.ATESTLF_OSC_1P8V. To drive these signals further on to the ATEST outputs, these muxes must be programmed to select these inputs. | RW | 0
9:8 | RCOSCLF_RTUNE_TRIM | Trims the resistance in the RC 32 kHz osc to tune the osc frequency.
Value | ENUM name | Description
0x0 | 7P5MEG | 7.5 MOhm (Default)
0x1 | 7P0MEG | 7.0 MOhm
0x2 | 6P5MEG | 6.5 MOhm
0x3 | 6P0MEG | 6.0 MOhm
| RW | 0x0
7:0 | RCOSCLF_CTUNE_TRIM | Internal field controlled by TI provided startup code | RW | 0x00

### TOP:DDI_0_OSC:RCOSCHFCTL

Address offset | 0x0000 0030
Physical address | 0x400C A030 | Instance | DDI_0_OSC
Description | RCOSCHF Control
Type | RW

Bits | Field Name | Description | Type | Reset
31:16 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text) | RW | 0x0000
15:8 | RCOSCHF_CTRIM | Internal field controlled by TI provided startup code | RW | 0x00
7 | SPARE7 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior | RW | 0
6 | ATEST_VDD_LOCAL_SEL | Selects source of VDD_LOCAL - before or after the buffer 0: Selects buffered VDD_LOCAL 1: Selects unbuffered VDD_LOCAL directly from replica inverter | RW | 0
5 | RCOSCHF_ATEST_EN | Enables ATEST outputs of RCOSC_HF. 0: RCOSC_HF does not drive ATEST signals. 1: RCOSC_HF_CLK drives ATEST1 and ATEST0 output is controlled by ATEST_VDD_LOCAL_SEL This enable causes the RCOSC_HF to drive the signals that go to a mux controlled by ATESTCTL.ATEST_OSC_HF_SEL. To drive these signals further on to the ATEST outputs, that mux must be programmed to select these inputs. | RW | 0
4 | Reserved | Internal | RW | 0
3:0 | RCOSCHF_ITUNE_TRIM | Trim bias current used in local inverter in 500nA steps. This field uses a 2's complement encoding. 1000: 2.000 uA 1111: 5.500 uA 0000: 6.000 uA (default) 0001: 6.500 uA 0111: 9.500 uA Trims rcosc_hf vdd local regulator. | RW | 0x0

### TOP:DDI_0_OSC:STAT0

Address offset | 0x0000 0034
Physical address | 0x400C A034 | Instance | DDI_0_OSC
Description | Status 0 This register contains status signals from OSC_DIG
Type | RO

Bits | Field Name | Description | Type | Reset
31 | Reserved | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) | RO | 0
30:29 | SCLK_LF_SRC | Indicates source for the sclk_lf 00: rcosc_hf_dlf 01: xosc_hf_dlf 10: rcosc_lf 11: xosc_lf | RO | 0x0
28 | SCLK_HF_SRC | Indicates source for the sclk_hf 0: rcosc_hf 1: xosc_hf | RO | 0
27 | BYPASS_OSCDIG | indicates that OSC_DIG is bypassed | RO | 0
26 | BGAP_NEEDED | bgap_needed request from OSC_DIG | RO | 0
25 | BGAP_RDY | bgap_rdy -- input | RO | 0
24 | GBIAS_NEEDED | gbias_needed request from OSC_DIG | RO | 0
23 | GBIAS_RDY | gbias_rdy -- input | RO | 0
22 | RCOSC_HF_EN | RCOSC_HF_EN | RO | 0
21 | RCOSC_LF_EN | RCOSC_LF_EN | RO | 0
20 | XOSC_LF_EN | XOSC_LF_EN | RO | 0
19 | CLK_DCDC_RDY | CLK_DCDC_RDY | RO | 0
18 | CLK_DCDC_RDY_ACK | CLK_DCDC_RDY_ACK | RO | 0
17 | SCLK_HF_LOSS | Indicates sclk_hf is lost | RO | 0
16 | SCLK_LF_LOSS | Indicates sclk_lf is lost | RO | 0
15 | XOSC_HF_EN | Indicates that XOSC_HF is enable if not BAW Mode. Else indicates BAW is active. | RO | 0
14 | XOSC_HF_PEAK_DET_EN | XOSC_HF_PEAK_DET_EN | RO | 0
13 | XB_48M_CLK_EN | Indicates that the 48MHz clock from the BAW or DOUBLER is enabled. If not in BAW Mode, indicates the DOUBLER is enabled. It will be enabled if 24 or 48 MHz chrystal is used (enabled in doulbler bypass for the 48MHz chrystal). If BAW Mode indicates that the 48MHz BAW clock is being used for a 48MHz clock source (SCLK_HF or CLK_DCDC). | RO | 0
12 | ADC_EN | ADC_EN | RO | 0
11 | XOSC_HF_LP_BUF_EN | XOSC_HF_LP_BUF_EN | RO | 0
10 | XOSC_HF_HP_BUF_EN | XOSC_HF_HP_BUF_EN | RO | 0
9 | RADC_DIG_CLRZ | RADC_DIG_CLRZ | RO | 0
8 | ADC_THMET | ADC_THMET | RO | 0
7 | ADC_DATA_READY | indicates when adc_data is ready. | RO | 0
6:1 | ADC_DATA | adc_data | RO | 0x00
0 | PENDINGSCLKHFSWITCHING | Indicates when sclk_hf is ready to be swtiched | RO | 0

### TOP:DDI_0_OSC:STAT1

Address offset | 0x0000 0038
Physical address | 0x400C A038 | Instance | DDI_0_OSC
Description | Status 1 This register contains status signals from OSC_DIG
Type | RO

Bits | Field Name | Description | Type | Reset
31:28 | RAMPSTATE | AMPCOMP FSM State
Value | ENUM name | Description
0x0 | RESET | RESET
0x1 | INITIALIZATION | INITIALIZATION
0x2 | HPM_RAMP1 | HPM_RAMP1
0x3 | HPM_RAMP2 | HPM_RAMP2
0x4 | HPM_RAMP3 | HPM_RAMP3
0x5 | HPM_UPDATE | HPM_UPDATE
0x6 | IDAC_INCREMENT | IDAC_INCREMENT
0x7 | IBIAS_CAP_UPDATE | IBIAS_CAP_UPDATE
0x8 | IBIAS_DEC_W_MEASURE | IBIAS_DECREMENT_WITH_MEASURE
0x9 | LPM_UPDATE | LPM_UPDATE
0xA | IBIAS_INC | IBIAS_INCREMENT
0xB | IDAC_DEC_W_MEASURE | IDAC_DECREMENT_WITH_MEASURE
0xC | DUMMY_TO_INIT_1 | DUMMY_TO_INIT_1
0xD | FAST_START | FAST_START
0xE | FAST_START_SETTLE | FAST_START_SETTLE
| RO | 0x0
27:22 | HMP_UPDATE_AMP | OSC amplitude during HPM_UPDATE state. The vaue is an unsigned interger. It is used for debug only. | RO | 0x00
21:16 | LPM_UPDATE_AMP | OSC amplitude during LPM_UPDATE state The vaue is an unsigned interger. It is used for debug only. | RO | 0x00
15 | FORCE_RCOSC_HF | force_rcosc_hf | RO | 0
14 | SCLK_HF_EN | SCLK_HF_EN | RO | 0
13 | SCLK_MF_EN | SCLK_MF_EN | RO | 0
12 | ACLK_ADC_EN | ACLK_ADC_EN | RO | 0
11 | ACLK_TDC_EN | ACLK_TDC_EN | RO | 0
10 | ACLK_REF_EN | ACLK_REF_EN | RO | 0
9 | CLK_CHP_EN | CLK_CHP_EN | RO | 0
8 | CLK_DCDC_EN | CLK_DCDC_EN | RO | 0
7 | SCLK_HF_GOOD | SCLK_HF_GOOD | RO | 0
6 | SCLK_MF_GOOD | SCLK_MF_GOOD | RO | 0
5 | SCLK_LF_GOOD | SCLK_LF_GOOD | RO | 0
4 | ACLK_ADC_GOOD | ACLK_ADC_GOOD | RO | 0
3 | ACLK_TDC_GOOD | ACLK_TDC_GOOD | RO | 0
2 | ACLK_REF_GOOD | ACLK_REF_GOOD | RO | 0
1 | CLK_CHP_GOOD | CLK_CHP_GOOD | RO | 0
0 | CLK_DCDC_GOOD | CLK_DCDC_GOOD | RO | 0

### TOP:DDI_0_OSC:STAT2

Address offset | 0x0000 003C
Physical address | 0x400C A03C | Instance | DDI_0_OSC
Description | Status 2 This register contains status signals from AMPCOMP FSM
Type | RO

Bits | Field Name | Description | Type | Reset
31:26 | ADC_DCBIAS | DC Bias read by RADC during SAR mode The vaue is an unsigned interger. It is used for debug only. | RO | 0x00
25 | HPM_RAMP1_THMET | Indication of threshhold is met for hpm_ramp1 | RO | 0
24 | HPM_RAMP2_THMET | Indication of threshhold is met for hpm_ramp2 | RO | 0
23 | HPM_RAMP3_THMET | Indication of threshhold is met for hpm_ramp3 | RO | 0
22 | IBIAS_DEC_WITH_MEASURE_DONE | Condition to exit ibias_dec_with_measure is met | RO | 0
21 | IBIAS_WAIT_CNTR_DONE | Condition to exit ibias_wait_cntr is met | RO | 0
20 | IDAC_INCREMENT_DONE | Condition to exit idac_increment is met | RO | 0
19 | IBIAS_CAP_UPDATE_DONE | Condition to exit ibias_cap_updated is met | RO | 0
18 | IDAC_DECREMENT_WITH_MEASURE_DONE | Condition to exit idac_dec_with_measure is met | RO | 0
17 | IBIAS_INCREMENT_DONE | Condition to exit ibias_inc is met | RO | 0
16 | RAMP_DOWN_TO_INIT_DONE | counter for ramp down to initi is done. Use for debug | RO | 0
15:12 | RAMPSTATE | xosc_hf amplitude compensation FSM This is identical to STAT1.RAMPSTATE. See that description for encoding. | RO | 0x0
11:9 | ADCSTATE | ADC FSM State. Used by amplitude compensation FSM.
Value | ENUM name | Description
0x0 | ADC_RESET | ADC_RESET
0x1 | ADC_IDLE | ADC_IDLE
0x2 | ADC_SC | ADC_SC
0x3 | ADC_RDDCB | ADC_RDDCB
0x4 | ADC_RDAMP | ADC_RDAMP
0x5 | ADC_CALC | ADC_CALC
| RO | 0x0
8 | ADC_COMP_P | LDO Status in BAW mode and comparator output in regular mode. Should be ignored in regular mode | RO | 0
7 | ADC_COMP_M | BAW_CLKGOOD in BAW mode and not used in regular mode | RO | 0
6:4 | AMPCOMP_OF_UF | overflow and underflow status in FSM 0x0: No overlow or underflow 0x1: IDAC underflow in HPM_RAMP3 0x2: IDAC underflow in IDAC_DECREMENT_WITH_MEASURE. 0x4: IDAC underflow or overflow in HPM_UPDATE or LPM_UPDATE | RO | 0x0
3 | AMPCOMP_REQ | ampcomp_req | RO | 0
2 | XOSC_HF_AMPGOOD | amplitude of xosc_hf is within the required threshold (set by DDI). Not used for anything just for debug/status | RO | 0
1 | XOSC_HF_FREQGOOD | frequency of xosc_hf is good to use for the digital clocks | RO | 0
0 | XOSC_HF_RF_FREQGOOD | frequency of xosc_hf is within +/- 20 ppm and xosc_hf is good for radio operations. Used for SW to start synthesizer. | RO | 0