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i2c.h
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1 /******************************************************************************
2 * Filename: i2c.h
3 * Revised: 2015-01-14 12:12:44 +0100 (on, 14 jan 2015)
4 * Revision: 42373
5 *
6 * Description: Defines and prototypes for the I2C.
7 *
8 * Copyright (c) 2015, Texas Instruments Incorporated
9 * All rights reserved.
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions are met:
13 *
14 * 1) Redistributions of source code must retain the above copyright notice,
15 * this list of conditions and the following disclaimer.
16 *
17 * 2) Redistributions in binary form must reproduce the above copyright notice,
18 * this list of conditions and the following disclaimer in the documentation
19 * and/or other materials provided with the distribution.
20 *
21 * 3) Neither the name of the ORGANIZATION nor the names of its contributors may
22 * be used to endorse or promote products derived from this software without
23 * specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
26 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
28 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
29 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
35 * POSSIBILITY OF SUCH DAMAGE.
36 *
37 ******************************************************************************/
38
39 //*****************************************************************************
40 //
43 //
44 //*****************************************************************************
45
46 #ifndef __I2C_H__
47 #define __I2C_H__
48
49 //*****************************************************************************
50 //
51 // If building with a C++ compiler, make all of the definitions in this header
52 // have a C binding.
53 //
54 //*****************************************************************************
55 #ifdef __cplusplus
56 extern "C"
57 {
58 #endif
59
60 #include <stdbool.h>
61 #include <stdint.h>
62 #include <inc/hw_types.h>
63 #include <inc/hw_ints.h>
64 #include <inc/hw_memmap.h>
65 #include <inc/hw_i2c.h>
66 #include <inc/hw_sysctl.h>
67 #include <driverlib/debug.h>
68 #include <driverlib/interrupt.h>
69 #include <driverlib/cpu.h>
70
71 //*****************************************************************************
72 //
73 // Support for DriverLib in ROM:
74 // This section renames all functions that are not "static inline", so that
75 // calling these functions will default to implementation in flash. At the end
76 // of this file a second renaming will change the defaults to implementation in
77 // ROM for available functions.
78 //
79 // To force use of the implementation in flash, e.g. for debugging:
80 // - Globally: Define DRIVERLIB_NOROM at project level
81 // - Per function: Use prefix "NOROM_" when calling the function
82 //
83 // Do not define DRIVERLIB_GENERATE_ROM!
84 //
85 //*****************************************************************************
86 #ifndef DRIVERLIB_GENERATE_ROM
87 #define I2CMasterInitExpClk NOROM_I2CMasterInitExpClk
88 #define I2CMasterErr NOROM_I2CMasterErr
89 #define I2CIntRegister NOROM_I2CIntRegister
90 #define I2CIntUnregister NOROM_I2CIntUnregister
91 #endif
92
93 //*****************************************************************************
94 //
95 // I2C Master commands
96 //
97 //*****************************************************************************
98 #define I2C_MASTER_CMD_SINGLE_SEND \
99 0x00000007
100 #define I2C_MASTER_CMD_SINGLE_RECEIVE \
101 0x00000007
102 #define I2C_MASTER_CMD_BURST_SEND_START \
103 0x00000003
104 #define I2C_MASTER_CMD_BURST_SEND_CONT \
105 0x00000001
106 #define I2C_MASTER_CMD_BURST_SEND_FINISH \
107 0x00000005
108 #define I2C_MASTER_CMD_BURST_SEND_ERROR_STOP \
109 0x00000004
110 #define I2C_MASTER_CMD_BURST_RECEIVE_START \
111 0x0000000b
112 #define I2C_MASTER_CMD_BURST_RECEIVE_CONT \
113 0x00000009
114 #define I2C_MASTER_CMD_BURST_RECEIVE_FINISH \
115 0x00000005
116 #define I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP \
117 0x00000004
118
119 //*****************************************************************************
120 //
121 // I2C Master error status
122 //
123 //*****************************************************************************
124 #define I2C_MASTER_ERR_NONE 0
125 #define I2C_MASTER_ERR_ADDR_ACK 0x00000004
126 #define I2C_MASTER_ERR_DATA_ACK 0x00000008
127 #define I2C_MASTER_ERR_ARB_LOST 0x00000010
128
129 //*****************************************************************************
130 //
131 // I2C Slave action requests
132 //
133 //*****************************************************************************
134 #define I2C_SLAVE_ACT_NONE 0
135 #define I2C_SLAVE_ACT_RREQ 0x00000001 // Master has sent data
136 #define I2C_SLAVE_ACT_TREQ 0x00000002 // Master has requested data
137 #define I2C_SLAVE_ACT_RREQ_FBR 0x00000005 // Master has sent first byte
138
139 //*****************************************************************************
140 //
141 // I2C Slave interrupts
142 //
143 //*****************************************************************************
144 #define I2C_SLAVE_INT_STOP 0x00000004 // Stop Condition Interrupt.
145 #define I2C_SLAVE_INT_START 0x00000002 // Start Condition Interrupt.
146 #define I2C_SLAVE_INT_DATA 0x00000001 // Data Interrupt.
147
148 //*****************************************************************************
149 //
150 // API Functions and prototypes
151 //
152 //*****************************************************************************
153
154 #ifdef DRIVERLIB_DEBUG
155 //*****************************************************************************
156 //
167 //
168 //*****************************************************************************
169 static bool
170 I2CBaseValid(uint32_t ui32Base)
171 {
172 return(ui32Base == I2C0_BASE);
173 }
174 #endif
175
176 //*****************************************************************************
177 //
198 //
199 //*****************************************************************************
200 extern void I2CMasterInitExpClk(uint32_t ui32Base, uint32_t ui32I2CClk,
201 bool bFast);
202
203 //*****************************************************************************
204 //
225 //
226 //*****************************************************************************
227 __STATIC_INLINE void
228 I2CMasterControl(uint32_t ui32Base, uint32_t ui32Cmd)
229 {
230 //
231 // Check the arguments.
232 //
233 ASSERT(I2CBaseValid(ui32Base));
234 ASSERT((ui32Cmd == I2C_MASTER_CMD_SINGLE_SEND) ||
235 // (ui32Cmd == I2C_MASTER_CMD_SINGLE_RECEIVE) || -> Equal to SINGLE_SEND
236 (ui32Cmd == I2C_MASTER_CMD_BURST_SEND_START) ||
237 (ui32Cmd == I2C_MASTER_CMD_BURST_SEND_CONT) ||
238 (ui32Cmd == I2C_MASTER_CMD_BURST_SEND_FINISH) ||
239 (ui32Cmd == I2C_MASTER_CMD_BURST_SEND_ERROR_STOP) ||
240 (ui32Cmd == I2C_MASTER_CMD_BURST_RECEIVE_START) ||
241 (ui32Cmd == I2C_MASTER_CMD_BURST_RECEIVE_CONT) ||
242 (ui32Cmd == I2C_MASTER_CMD_BURST_RECEIVE_FINISH) ||
243 (ui32Cmd == I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP));
244
245 //
246 // Send the command.
247 //
248 HWREG(ui32Base + I2C_O_MCTRL) = ui32Cmd;
249
250 //
251 // Delay minimum four cycles in order to asure that the I2C_O_MSTAT
252 // register has been correctly updated before function exit
253 //
254 CPUdelay(2);
255 }
256
257 //*****************************************************************************
258 //
274 //
275 //*****************************************************************************
276 __STATIC_INLINE void
277 I2CMasterSlaveAddrSet(uint32_t ui32Base, uint8_t ui8SlaveAddr,
278 bool bReceive)
279 {
280 //
281 // Check the arguments.
282 //
283 ASSERT(I2CBaseValid(ui32Base));
284 ASSERT(!(ui8SlaveAddr & 0x80));
285
286 //
287 // Set the address of the slave with which the master will communicate.
288 //
289 HWREG(ui32Base + I2C_O_MSA) = (ui8SlaveAddr << 1) | bReceive;
290 }
291
292 //*****************************************************************************
293 //
301 //
302 //*****************************************************************************
303 __STATIC_INLINE void
304 I2CMasterEnable(uint32_t ui32Base)
305 {
306 //
307 // Check the arguments.
308 //
309 ASSERT(I2CBaseValid(ui32Base));
310
311 //
312 // Enable the clock for the master.
313 //
314 HWREG(ui32Base + I2C_O_MCR) |= I2C_MCR_MFE;
315
316 //
317 // Enable the master block.
318 //
319 HWREG(ui32Base + I2C_O_MCTRL) = I2C_MCTRL_RUN;
320 }
321
322 //*****************************************************************************
323 //
331 //
332 //*****************************************************************************
333 __STATIC_INLINE void
334 I2CMasterDisable(uint32_t ui32Base)
335 {
336 //
337 // Check the arguments.
338 //
339 ASSERT(I2CBaseValid(ui32Base));
340
341 //
342 // Disable the master block.
343 //
344 HWREG(ui32Base + I2C_O_MCTRL) = 0;
345
346 //
347 // Disable the clock for the master.
348 //
349 HWREG(ui32Base + I2C_O_MCR) &= ~I2C_MCR_MFE;
350 }
351
352 //*****************************************************************************
353 //
364 //
365 //*****************************************************************************
366 __STATIC_INLINE bool
367 I2CMasterBusy(uint32_t ui32Base)
368 {
369 //
370 // Check the arguments.
371 //
372 ASSERT(I2CBaseValid(ui32Base));
373
374 //
375 // Return the busy status.
376 //
377 if(HWREG(ui32Base + I2C_O_MSTAT) & I2C_MSTAT_BUSY)
378 {
379 return(true);
380 }
381 else
382 {
383 return(false);
384 }
385 }
386
387 //*****************************************************************************
388 //
400 //
401 //*****************************************************************************
402 __STATIC_INLINE bool
403 I2CMasterBusBusy(uint32_t ui32Base)
404 {
405 //
406 // Check the arguments.
407 //
408 ASSERT(I2CBaseValid(ui32Base));
409
410 //
411 // Return the bus busy status.
412 //
413 if(HWREG(ui32Base + I2C_O_MSTAT) & I2C_MSTAT_BUSBSY)
414 {
415 return(true);
416 }
417 else
418 {
419 return(false);
420 }
421 }
422
423 //*****************************************************************************
424 //
433 //
434 //*****************************************************************************
435 __STATIC_INLINE uint32_t
436 I2CMasterDataGet(uint32_t ui32Base)
437 {
438 //
439 // Check the arguments.
440 //
441 ASSERT(I2CBaseValid(ui32Base));
442
443 //
444 // Read a byte.
445 //
446 return(HWREG(ui32Base + I2C_O_MDR));
447 }
448
449 //*****************************************************************************
450 //
459 //
460 //*****************************************************************************
461 __STATIC_INLINE void
462 I2CMasterDataPut(uint32_t ui32Base, uint8_t ui8Data)
463 {
464 //
465 // Check the arguments.
466 //
467 ASSERT(I2CBaseValid(ui32Base));
468
469 //
470 // Write the byte.
471 //
472 HWREG(ui32Base + I2C_O_MDR) = ui8Data;
473 }
474
475 //*****************************************************************************
476 //
489 //
490 //*****************************************************************************
491 extern uint32_t I2CMasterErr(uint32_t ui32Base);
492
493 //*****************************************************************************
494 //
502 //
503 //*****************************************************************************
504 __STATIC_INLINE void
505 I2CMasterIntEnable(uint32_t ui32Base)
506 {
507 //
508 // Check the arguments.
509 //
510 ASSERT(I2CBaseValid(ui32Base));
511
512 //
513 // Enable the master interrupt.
514 //
515 HWREG(ui32Base + I2C_O_MIMR) = I2C_MIMR_IM;
516 }
517
518 //*****************************************************************************
519 //
527 //
528 //*****************************************************************************
529 __STATIC_INLINE void
530 I2CMasterIntDisable(uint32_t ui32Base)
531 {
532 //
533 // Check the arguments.
534 //
535 ASSERT(I2CBaseValid(ui32Base));
536
537 //
538 // Disable the master interrupt.
539 //
540 HWREG(ui32Base + I2C_O_MIMR) = 0;
541 }
542
543 //*****************************************************************************
544 //
563 //
564 //*****************************************************************************
565 __STATIC_INLINE void
566 I2CMasterIntClear(uint32_t ui32Base)
567 {
568 //
569 // Check the arguments.
570 //
571 ASSERT(I2CBaseValid(ui32Base));
572
573 //
574 // Clear the I2C master interrupt source.
575 //
576 HWREG(ui32Base + I2C_O_MICR) = I2C_MICR_IC;
577 }
578
579 //*****************************************************************************
580 //
595 //
596 //*****************************************************************************
597 __STATIC_INLINE bool
598 I2CMasterIntStatus(uint32_t ui32Base, bool bMasked)
599 {
600 //
601 // Check the arguments.
602 //
603 ASSERT(I2CBaseValid(ui32Base));
604
605 //
606 // Return either the interrupt status or the raw interrupt status as
607 // requested.
608 //
609 if(bMasked)
610 {
611 return((HWREG(ui32Base + I2C_O_MMIS)) ? true : false);
612 }
613 else
614 {
615 return((HWREG(ui32Base + I2C_O_MRIS)) ? true : false);
616 }
617 }
618
619 //*****************************************************************************
620 //
628 //
629 //*****************************************************************************
630 __STATIC_INLINE void
631 I2CSlaveEnable(uint32_t ui32Base)
632 {
633 //
634 // Check the arguments.
635 //
636 ASSERT(I2CBaseValid(ui32Base));
637
638 //
639 // Enable the clock to the slave block.
640 //
641 HWREG(ui32Base + I2C_O_MCR) |= I2C_MCR_SFE;
642
643 //
644 // Enable the slave.
645 //
646 HWREG(ui32Base + I2C_O_SCTL) = I2C_SCTL_DA;
647 }
648
649 //*****************************************************************************
650 //
664 //
665 //*****************************************************************************
666 __STATIC_INLINE void
667 I2CSlaveInit(uint32_t ui32Base, uint8_t ui8SlaveAddr)
668 {
669 //
670 // Check the arguments.
671 //
672 ASSERT(I2CBaseValid(ui32Base));
673 ASSERT(!(ui8SlaveAddr & 0x80));
674
675 //
676 // Must enable the device before doing anything else.
677 //
678 I2CSlaveEnable(ui32Base);
679
680 //
681 // Set up the slave address.
682 //
683 HWREG(ui32Base + I2C_O_SOAR) = ui8SlaveAddr;
684 }
685
686 //*****************************************************************************
687 //
696 //
697 //*****************************************************************************
698 __STATIC_INLINE void
699 I2CSlaveAddressSet(uint32_t ui32Base, uint8_t ui8SlaveAddr)
700 {
701 //
702 // Check the arguments.
703 //
704 ASSERT(I2CBaseValid(ui32Base));
705 ASSERT(!(ui8SlaveAddr & 0x80));
706
707 //
708 // Set up the primary slave address.
709 //
710 HWREG(ui32Base + I2C_O_SOAR) = ui8SlaveAddr;
711 }
712
713 //*****************************************************************************
714 //
722 //
723 //*****************************************************************************
724 __STATIC_INLINE void
725 I2CSlaveDisable(uint32_t ui32Base)
726 {
727 //
728 // Check the arguments.
729 //
730 ASSERT(I2CBaseValid(ui32Base));
731
732 //
733 // Disable the slave.
734 //
735 HWREG(ui32Base + I2C_O_SCTL) = 0x0;
736
737 //
738 // Disable the clock to the slave block.
739 //
740 HWREG(ui32Base + I2C_O_MCR) &= ~I2C_MCR_SFE;
741 }
742
743 //*****************************************************************************
744 //
757 //
758 //*****************************************************************************
759 __STATIC_INLINE uint32_t
760 I2CSlaveStatus(uint32_t ui32Base)
761 {
762 //
763 // Check the arguments.
764 //
765 ASSERT(I2CBaseValid(ui32Base));
766
767 //
768 // Return the slave status.
769 //
770 return(HWREG(ui32Base + I2C_O_SSTAT));
771 }
772
773 //*****************************************************************************
774 //
783 //
784 //*****************************************************************************
785 __STATIC_INLINE uint32_t
786 I2CSlaveDataGet(uint32_t ui32Base)
787 {
788 //
789 // Check the arguments.
790 //
791 ASSERT(I2CBaseValid(ui32Base));
792
793 //
794 // Read a byte.
795 //
796 return(HWREG(ui32Base + I2C_O_SDR));
797 }
798
799 //*****************************************************************************
800 //
809 //
810 //*****************************************************************************
811 __STATIC_INLINE void
812 I2CSlaveDataPut(uint32_t ui32Base, uint8_t ui8Data)
813 {
814 //
815 // Check the arguments.
816 //
817 ASSERT(I2CBaseValid(ui32Base));
818
819 //
820 // Write the byte.
821 //
822 HWREG(ui32Base + I2C_O_SDR) = ui8Data;
823 }
824
825 //*****************************************************************************
826 //
841 //
842 //*****************************************************************************
843 __STATIC_INLINE void
844 I2CSlaveIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags)
845 {
846 uint32_t ui32Val;
847
848 //
849 // Check the arguments.
850 //
851 ASSERT(I2CBaseValid(ui32Base));
852 ASSERT(ui32IntFlags & (I2C_SLAVE_INT_STOP | I2C_SLAVE_INT_START |
853 I2C_SLAVE_INT_DATA));
854
855 //
856 // Enable the slave interrupt.
857 //
858 ui32Val = HWREG(ui32Base + I2C_O_SIMR);
859 ui32Val |= ui32IntFlags;
860 HWREG(ui32Base + I2C_O_SIMR) = ui32Val;
861 }
862
863 //*****************************************************************************
864 //
879 //
880 //*****************************************************************************
881 __STATIC_INLINE void
882 I2CSlaveIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags)
883 {
884 uint32_t ui32Val;
885
886 //
887 // Check the arguments.
888 //
889 ASSERT(I2CBaseValid(ui32Base));
890 ASSERT(ui32IntFlags & (I2C_SLAVE_INT_STOP | I2C_SLAVE_INT_START |
891 I2C_SLAVE_INT_DATA));
892
893 //
894 // Disable the slave interrupt.
895 //
896 ui32Val = HWREG(ui32Base + I2C_O_SIMR);
897 ui32Val &= ~ui32IntFlags;
898 HWREG(ui32Base + I2C_O_SIMR) = ui32Val;
899 }
900
901 //*****************************************************************************
902 //
926 //
927 //*****************************************************************************
928 __STATIC_INLINE void
929 I2CSlaveIntClear(uint32_t ui32Base, uint32_t ui32IntFlags)
930 {
931 //
932 // Check the arguments.
933 //
934 ASSERT(I2CBaseValid(ui32Base));
935
936 //
937 // Clear the I2C slave interrupt source.
938 //
939 HWREG(ui32Base + I2C_O_SICR) = ui32IntFlags;
940 }
941
942 //*****************************************************************************
943 //
959
960 //
961 //*****************************************************************************
962 __STATIC_INLINE uint32_t
963 I2CSlaveIntStatus(uint32_t ui32Base, bool bMasked)
964 {
965 //
966 // Check the arguments.
967 //
968 ASSERT(I2CBaseValid(ui32Base));
969
970 //
971 // Return either the interrupt status or the raw interrupt status as
972 // requested.
973 //
974 if(bMasked)
975 {
976 return(HWREG(ui32Base + I2C_O_SMIS));
977 }
978 else
979 {
980 return(HWREG(ui32Base + I2C_O_SRIS));
981 }
982 }
983
984 //*****************************************************************************
985 //
1003 //
1004 //*****************************************************************************
1005 extern void I2CIntRegister(uint32_t ui32Base, void (*pfnHandler)(void));
1006
1007 //*****************************************************************************
1008 //
1021 //
1022 //*****************************************************************************
1023 extern void I2CIntUnregister(uint32_t ui32Base);
1024
1025 //*****************************************************************************
1026 //
1027 // Support for DriverLib in ROM:
1028 // Redirect to implementation in ROM when available.
1029 //
1030 //*****************************************************************************
1031 #ifndef DRIVERLIB_NOROM
1032 #include <driverlib/rom.h>
1033 #ifdef ROM_I2CMasterInitExpClk
1034 #undef I2CMasterInitExpClk
1035 #define I2CMasterInitExpClk ROM_I2CMasterInitExpClk
1036 #endif
1037 #ifdef ROM_I2CMasterErr
1038 #undef I2CMasterErr
1039 #define I2CMasterErr ROM_I2CMasterErr
1040 #endif
1041 #ifdef ROM_I2CIntRegister
1042 #undef I2CIntRegister
1043 #define I2CIntRegister ROM_I2CIntRegister
1044 #endif
1045 #ifdef ROM_I2CIntUnregister
1046 #undef I2CIntUnregister
1047 #define I2CIntUnregister ROM_I2CIntUnregister
1048 #endif
1049 #endif
1050
1051 //*****************************************************************************
1052 //
1053 // Mark the end of the C bindings section for C++ compilers.
1054 //
1055 //*****************************************************************************
1056 #ifdef __cplusplus
1057 }
1058 #endif
1059
1060 #endif // __I2C_H__
1061
1062 //*****************************************************************************
1063 //
1066 //
1067 //*****************************************************************************
I2CSlaveIntEnable
__STATIC_INLINE void I2CSlaveIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags)
Enables individual I2C Slave interrupt sources.
Definition: i2c.h:844
I2C_SLAVE_INT_STOP
#define I2C_SLAVE_INT_STOP
Definition: i2c.h:144
I2CSlaveIntStatus
__STATIC_INLINE uint32_t I2CSlaveIntStatus(uint32_t ui32Base, bool bMasked)
Gets the current I2C Slave interrupt status.
Definition: i2c.h:963
I2CSlaveDisable
__STATIC_INLINE void I2CSlaveDisable(uint32_t ui32Base)
Disables the I2C slave block.
Definition: i2c.h:725
I2C_MASTER_CMD_BURST_SEND_START
#define I2C_MASTER_CMD_BURST_SEND_START
Definition: i2c.h:102
debug.h
I2CMasterControl
__STATIC_INLINE void I2CMasterControl(uint32_t ui32Base, uint32_t ui32Cmd)
Controls the state of the I2C Master module.
Definition: i2c.h:228
I2CMasterDisable
__STATIC_INLINE void I2CMasterDisable(uint32_t ui32Base)
Disables the I2C master block.
Definition: i2c.h:334
I2C_MASTER_CMD_BURST_SEND_ERROR_STOP
#define I2C_MASTER_CMD_BURST_SEND_ERROR_STOP
Definition: i2c.h:108
I2CSlaveEnable
__STATIC_INLINE void I2CSlaveEnable(uint32_t ui32Base)
Enables the I2C Slave block.
Definition: i2c.h:631
I2CSlaveIntClear
__STATIC_INLINE void I2CSlaveIntClear(uint32_t ui32Base, uint32_t ui32IntFlags)
Clears I2C Slave interrupt sources.
Definition: i2c.h:929
ASSERT
#define ASSERT(expr)
Definition: debug.h:65
I2CMasterSlaveAddrSet
__STATIC_INLINE void I2CMasterSlaveAddrSet(uint32_t ui32Base, uint8_t ui8SlaveAddr, bool bReceive)
Sets the address that the I2C Master will place on the bus.
Definition: i2c.h:277
I2C_SLAVE_INT_START
#define I2C_SLAVE_INT_START
Definition: i2c.h:145
I2CMasterInitExpClk
void I2CMasterInitExpClk(uint32_t ui32Base, uint32_t ui32I2CClk, bool bFast)
Initializes the I2C Master block.
Definition: i2c.c:64
I2CSlaveDataGet
__STATIC_INLINE uint32_t I2CSlaveDataGet(uint32_t ui32Base)
Receives a byte that has been sent to the I2C Slave.
Definition: i2c.h:786
I2C_SLAVE_INT_DATA
#define I2C_SLAVE_INT_DATA
Definition: i2c.h:146
I2CMasterIntEnable
__STATIC_INLINE void I2CMasterIntEnable(uint32_t ui32Base)
Enables the I2C Master interrupt.
Definition: i2c.h:505
I2CMasterIntStatus
__STATIC_INLINE bool I2CMasterIntStatus(uint32_t ui32Base, bool bMasked)
Gets the current I2C Master interrupt status.
Definition: i2c.h:598
I2CMasterBusBusy
__STATIC_INLINE bool I2CMasterBusBusy(uint32_t ui32Base)
Indicates whether or not the I2C bus is busy.
Definition: i2c.h:403
I2C_MASTER_CMD_SINGLE_SEND
#define I2C_MASTER_CMD_SINGLE_SEND
Definition: i2c.h:98
I2CSlaveIntDisable
__STATIC_INLINE void I2CSlaveIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags)
Disables individual I2C Slave interrupt sources.
Definition: i2c.h:882
I2C_MASTER_CMD_BURST_RECEIVE_CONT
#define I2C_MASTER_CMD_BURST_RECEIVE_CONT
Definition: i2c.h:112
I2CMasterEnable
__STATIC_INLINE void I2CMasterEnable(uint32_t ui32Base)
Enables the I2C Master block.
Definition: i2c.h:304
I2CMasterIntDisable
__STATIC_INLINE void I2CMasterIntDisable(uint32_t ui32Base)
Disables the I2C Master interrupt.
Definition: i2c.h:530
I2CSlaveStatus
__STATIC_INLINE uint32_t I2CSlaveStatus(uint32_t ui32Base)
Gets the I2C Slave module status.
Definition: i2c.h:760
I2C_MASTER_CMD_BURST_SEND_FINISH
#define I2C_MASTER_CMD_BURST_SEND_FINISH
Definition: i2c.h:106
I2C_MASTER_CMD_BURST_SEND_CONT
#define I2C_MASTER_CMD_BURST_SEND_CONT
Definition: i2c.h:104
interrupt.h
I2C_MASTER_CMD_BURST_RECEIVE_FINISH
#define I2C_MASTER_CMD_BURST_RECEIVE_FINISH
Definition: i2c.h:114
cpu.h
I2CMasterErr
uint32_t I2CMasterErr(uint32_t ui32Base)
Gets the error status of the I2C Master module.
Definition: i2c.c:108
I2CSlaveInit
__STATIC_INLINE void I2CSlaveInit(uint32_t ui32Base, uint8_t ui8SlaveAddr)
Initializes the I2C Slave block.
Definition: i2c.h:667
I2C_MASTER_CMD_BURST_RECEIVE_START
#define I2C_MASTER_CMD_BURST_RECEIVE_START
Definition: i2c.h:110
rom.h
I2CMasterDataGet
__STATIC_INLINE uint32_t I2CMasterDataGet(uint32_t ui32Base)
Receives a byte that has been sent to the I2C Master.
Definition: i2c.h:436
I2CMasterBusy
__STATIC_INLINE bool I2CMasterBusy(uint32_t ui32Base)
Indicates whether or not the I2C Master is busy.
Definition: i2c.h:367
I2CMasterDataPut
__STATIC_INLINE void I2CMasterDataPut(uint32_t ui32Base, uint8_t ui8Data)
Transmits a byte from the I2C Master.
Definition: i2c.h:462
I2CIntRegister
void I2CIntRegister(uint32_t ui32Base, void(*pfnHandler)(void))
Registers an interrupt handler for the I2C module.
Definition: i2c.c:150
I2CSlaveDataPut
__STATIC_INLINE void I2CSlaveDataPut(uint32_t ui32Base, uint8_t ui8Data)
Transmits a byte from the I2C Slave.
Definition: i2c.h:812
I2CSlaveAddressSet
__STATIC_INLINE void I2CSlaveAddressSet(uint32_t ui32Base, uint8_t ui8SlaveAddr)
Sets the I2C slave address.
Definition: i2c.h:699
I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP
#define I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP
Definition: i2c.h:116
CPUdelay
void CPUdelay(uint32_t ui32Count)
Provide a small delay.
Definition: cpu.c:402
I2CMasterIntClear
__STATIC_INLINE void I2CMasterIntClear(uint32_t ui32Base)
Clears I2C Master interrupt sources.
Definition: i2c.h:566
I2CIntUnregister
void I2CIntUnregister(uint32_t ui32Base)
Unregisters an interrupt handler for the I2C module.
Definition: i2c.c:181