CPU_TIPROP

Instance: CPU_TIPROP
Component: CPU_TIPROP
Base address: 0xe00fe000

Cortex-M's TI proprietary registers

Address offset	0x0000 0FF8
Physical address	0xE00F EFF8	Instance	CPU_TIPROP
Description	Mux Selector for SWV or TRACECLK This selector allows user to route SWV or TRACECLK to IO pads. SWV can be used as standalone output. However, TRACECLK should be used together with TRACEDATA (4-bit) which can be routed out to the pads as observation signals. Note: IOC must be configured to route the mux output to the IOs.
Type	RW

Bits

Field Name

Description

Type

Reset

31:1

RESERVED

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

0x0000 0000

TRACECLK_N_SWV

Mux selector for SWV or TRACECLK
This bit is reset when ITM is reset.

Address offset	0x0000 0FFC
Physical address	0xE00F EFFC	Instance	CPU_TIPROP
Description	Clock Gating Scheme Configuration
Type	RW

Bits	Field Name	Description	Type	Reset
31:2	RESERVED	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.	RO	0x0000 0000
1:0	DYN_CG	Clock gating scheme configuration: 0: No clock gating from bus monitor 1: Clock gating as soon as the clock gating conditions are met (most aggressive). 2: Clock gating if the clock gating conditions stays valid more than one cycle. 3: Clock gating if the clock gating conditions stays valid more than two cycles. This field is reset when CPU core is reset.	RW	0x0