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Design Rule Verification Report

Date : 6/2/2015
Time : 10:59:03 AM
Elapsed Time : 00:00:08
Filename : D:\Project Files\TIDA-00498\Design Files\20150602\TIDA-00498_20150602\TIDA-00498.PcbDoc
Warnings : 0
Rule Violations : 28

Summary

Warnings Count
Total 0

Rule Violations Count
Clearance Constraint (Gap=40mil) (InPadClass('MTG')),(InPolygon) 0
Clearance Constraint (Gap=7.9mil) (InPadClass('U5')),(InPadClass('U5')) 0
Clearance Constraint (Gap=12mil) (IsVia),(IsVia) 0
Clearance Constraint (Gap=12mil) (IsVia),(IsSMTPin) 12
Differential Pairs Uncoupled Length using the Gap Constraints (Min=12mil) (Max=12mil) (Preferred=12mil) (InDifferentialPair ('RS485_2')) 0
Width Constraint (Min=10mil) (Max=100mil) (Preferred=10mil) (InDifferentialPair('RS485_2')) 0
Clearance Constraint (Gap=20mil) (InPolygon),(InPolygon) 0
Differential Pairs Uncoupled Length using the Gap Constraints (Min=12mil) (Max=12mil) (Preferred=12mil) (InDifferentialPair ('RS485_1')) 0
Width Constraint (Min=10mil) (Max=100mil) (Preferred=10mil) (InDifferentialPair('RS485_1')) 0
Width Constraint (Min=10mil) (Max=100mil) (Preferred=10mil) (InNetClass('RS485')) 0
Clearance Constraint (Gap=12mil) (InNetClass('RS485')),(InNetClass('RS485')) 0
Minimum Annular Ring (Minimum=5.905mil) (IsVia and InAnyComponent) 0
Routing Via (MinHoleWidth=7.874mil) (MaxHoleWidth=12mil) (PreferredHoleWidth=7.874mil) (MinWidth=19.685mil) (MaxWidth=26mil) (PreferedWidth=19.685mil) (IsVia and InAnyComponent) 0
Net Antennae (Tolerance=0mil) (All) 0
Hole To Hole Clearance (Gap=10mil) (All),(All) 0
Differential Pairs Uncoupled Length using the Gap Constraints (Min=10mil) (Max=100mil) (Preferred=10mil) (All) 0
Hole Size Constraint (Min=7mil) (Max=251mil) (All) 0
Minimum Annular Ring (Minimum=7mil) (All) 0
Un-Routed Net Constraint ( (All) ) 0
Short-Circuit Constraint (Allowed=No) (All),(All) 0
Routing Via (MinHoleWidth=12mil) (MaxHoleWidth=20mil) (PreferredHoleWidth=12mil) (MinWidth=24mil) (MaxWidth=40mil) (PreferedWidth=26mil) (All) 8
Routing Layers(All) 0
Power Plane Connect Rule(Relief Connect )(Expansion=10mil) (Conductor Width=10mil) (Air Gap=10mil) (Entries=4) (All) 0
Width Constraint (Min=6mil) (Max=100mil) (Preferred=10mil) (All) 0
Clearance Constraint (Gap=25mil) (OnCopper and InComponentClass('Mounting Holes')),(IsKeepOut) 7
Clearance Constraint (Gap=25mil) (OnCopper and InPoly),(IsKeepOut) 0
Clearance Constraint (Gap=25mil) (OnCopper and Not InComponentClass('Logo') and not InComponentClass('FiducialMark') and not InRegion(1000,500,4000,800) and Not IsKeepout),(IsKeepOut) 1
Clearance Constraint (Gap=8mil) (All),(All) 0
Clearance Constraint (Gap=15mil) (InPolygon),(All) 0
Clearance Constraint (Gap=12mil) (IsVia),(IsThruPin) 0
Clearance Constraint (Gap=22mil) (InNet('18V')),(All) 0
Total 28


Clearance Constraint (Gap=12mil) (IsVia),(IsSMTPin)
Via (3455mil,1400.134mil) Top Layer to Bottom Layer Pad U5-49(3455mil,1471mil) Top Layer
Via (3427.441mil,1471mil) Top Layer to Bottom Layer Pad U5-49(3455mil,1471mil) Top Layer
Via (3455mil,1443.441mil) Top Layer to Bottom Layer Pad U5-49(3455mil,1471mil) Top Layer
Via (3455mil,1541.866mil) Top Layer to Bottom Layer Pad U5-49(3455mil,1471mil) Top Layer
Via (3482.559mil,1471mil) Top Layer to Bottom Layer Pad U5-49(3455mil,1471mil) Top Layer
Via (3525.866mil,1471mil) Top Layer to Bottom Layer Pad U5-49(3455mil,1471mil) Top Layer
Via (3455mil,1498.559mil) Top Layer to Bottom Layer Pad U5-49(3455mil,1471mil) Top Layer
Via (3384.134mil,1471mil) Top Layer to Bottom Layer Pad U5-49(3455mil,1471mil) Top Layer
Via (1900mil,1252.244mil) Top Layer to Bottom Layer Pad U6-9(1923.622mil,1228.622mil) Top Layer
Via (1900mil,1205mil) Top Layer to Bottom Layer Pad U6-9(1923.622mil,1228.622mil) Top Layer
Via (1947.244mil,1252.244mil) Top Layer to Bottom Layer Pad U6-9(1923.622mil,1228.622mil) Top Layer
Via (1947.244mil,1205mil) Top Layer to Bottom Layer Pad U6-9(1923.622mil,1228.622mil) Top Layer
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Routing Via (MinHoleWidth=12mil) (MaxHoleWidth=20mil) (PreferredHoleWidth=12mil) (MinWidth=24mil) (MaxWidth=40mil) (PreferedWidth=26mil) (All)
Routing Via Style: Via (3525.866mil,1471mil) Top Layer to Bottom Layer
Routing Via Style: Via (3482.559mil,1471mil) Top Layer to Bottom Layer
Routing Via Style: Via (3455mil,1400.134mil) Top Layer to Bottom Layer
Routing Via Style: Via (3455mil,1443.441mil) Top Layer to Bottom Layer
Routing Via Style: Via (3384.134mil,1471mil) Top Layer to Bottom Layer
Routing Via Style: Via (3427.441mil,1471mil) Top Layer to Bottom Layer
Routing Via Style: Via (3455mil,1498.559mil) Top Layer to Bottom Layer
Routing Via Style: Via (3455mil,1541.866mil) Top Layer to Bottom Layer
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Clearance Constraint (Gap=25mil) (OnCopper and InComponentClass('Mounting Holes')),(IsKeepOut)
Track (25mil,1925mil)(25mil,2258mil) Keep-Out Layer Pad H1-1(200mil,1965mil) Multi-Layer
Track (25mil,25mil)(25mil,1925mil) Keep-Out Layer Pad H1-1(200mil,1965mil) Multi-Layer
Track (5095mil,25mil)(5095mil,2258mil) Keep-Out Layer Pad H2-1(4918mil,1750mil) Multi-Layer
Track (25mil,25mil)(25mil,1925mil) Keep-Out Layer Pad H3-1(200mil,200mil) Multi-Layer
Track (25mil,25mil)(5095mil,25mil) Keep-Out Layer Pad H3-1(200mil,200mil) Multi-Layer
Track (5095mil,25mil)(5095mil,2258mil) Keep-Out Layer Pad H4-1(4918mil,200mil) Multi-Layer
Track (25mil,25mil)(5095mil,25mil) Keep-Out Layer Pad H4-1(4918mil,200mil) Multi-Layer
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Clearance Constraint (Gap=25mil) (OnCopper and Not InComponentClass('Logo') and not InComponentClass('FiducialMark') and not InRegion(1000,500,4000,800) and Not IsKeepout),(IsKeepOut)
Area Fill (2979.934mil,1877.45mil) (3150mil,1952.253mil) Top Layer Pad Y2-3(2921.732mil,1915mil) Top Layer
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