Altium

Design Rule Verification Report

Date: 4/28/2016
Time: 11:34:31 AM
Elapsed Time: 00:00:02
Filename: C:\Users\a0223141\Desktop\US Rotation\Design\LM3481\Boost to Battery\LM3481_Design\LM3481 Boost to Battery_PCB.PcbDoc
Warnings: 0
Rule Violations: 51

Summary

Warnings Count
Total 0

Rule Violations Count
Clearance Constraint (Gap=0mil) (((IsTrack Or IsArc) And Not InPoly) And IsFree and IsKeepOut),(((IsTrack Or IsArc) And Not InPoly) And IsFree and IsKeepOut) 0
Clearance Constraint (Gap=25mil) (InPolygon),(All) 0
Clearance Constraint (Gap=7.874mil) (All),(All) 0
Width Constraint (Min=6mil) (Max=100mil) (Preferred=10mil) (All) 0
Power Plane Connect Rule(Relief Connect )(Expansion=10mil) (Conductor Width=10mil) (Air Gap=10mil) (Entries=4) (All) 0
Routing Layers(All) 0
Routing Via (MinHoleWidth=7.874mil) (MaxHoleWidth=12.992mil) (PreferredHoleWidth=7.874mil) (MinWidth=19.685mil) (MaxWidth=23.622mil) (PreferedWidth=19.685mil) (IsVia and InAnyComponent) 0
Routing Via (MinHoleWidth=7.874mil) (MaxHoleWidth=40mil) (PreferredHoleWidth=16mil) (MinWidth=26mil) (MaxWidth=65mil) (PreferedWidth=34mil) (All) 15
Short-Circuit Constraint (Allowed=No) (All),(All) 0
Un-Routed Net Constraint ( (All) ) 0
Minimum Annular Ring (Minimum=5.905mil) (IsVia and InAnyComponent) 0
Minimum Annular Ring (Minimum=8mil) (All) 15
Acute Angle Constraint (Minimum=45.000) (All) 0
Component Clearance Constraint ( Horizontal Gap = 50mil, Vertical Gap = 10mil ) (InComponentClass('Mounting Holes')),(InComponentClass('FiducialMark')) 0
Component Clearance Constraint ( Horizontal Gap = 0mil, Vertical Gap = 0mil ) (InComponentClass('Header')),(InComponentClass('Shunt')) 0
Component Clearance Constraint ( Horizontal Gap = 50mil, Vertical Gap = 10mil ) (InComponentClass('Logo')),(All) 0
Component Clearance Constraint ( Horizontal Gap = 5mil, Vertical Gap = 10mil ) ((HasFootprint('NY PMS 440 0025 PH'))),((HasFootprint('Keystone_1902C'))) 0
Component Clearance Constraint ( Horizontal Gap = 250mil, Vertical Gap = Infinite ) (InComponentClass('Mounting Holes')),(All) 0
Component Clearance Constraint ( Horizontal Gap = 14.961mil, Vertical Gap = 10mil ) (HasFootprint('0201*') or HasFootprint('0402*') or HasFootprint('0508') or HasFootprint('0603*') or HasFootprint('0612') or HasFootprint('0805*') or HasFootprint('0815*') or HasFootprint('0830*') or HasFootprint('1206*') or HasFootprint('1210*') or HasFootprint('1808*') or HasFootprint('1812*') or HasFootprint('1825*') or HasFootprint('2010*') or HasFootprint('2220*') or HasFootprint('2225*') or HasFootprint('2512*') or HasFootprint('2728*') or HasFootprint('3518*')),(HasFootprint('0201*') or HasFootprint('0402*') or HasFootprint('0508') or HasFootprint('0603*') or HasFootprint('0612') or HasFootprint('0805*') or HasFootprint('0815*') or HasFootprint('0830*') or HasFootprint('1206*') or HasFootprint('1210*') or HasFootprint('1808*') or HasFootprint('1812*') or HasFootprint('1825*') or HasFootprint('2010*') or HasFootprint('2220*') or HasFootprint('2225*') or HasFootprint('2512*') or HasFootprint('2728*') or HasFootprint('3518*')) 0
Component Clearance Constraint ( Horizontal Gap = 40mil, Vertical Gap = 30mil ) (IsThruComponent),(IsSMTComponent) 0
Component Clearance Constraint ( Horizontal Gap = 30mil, Vertical Gap = 30mil ) (IsThruComponent),(IsThruComponent) 0
Component Clearance Constraint ( Horizontal Gap = 30mil, Vertical Gap = 10mil ) (All),(All) 0
Hole Size Constraint (Min=7.874mil) (Max=251mil) (All) 0
Pads and Vias to follow the Drill pairs settings 0
Height Constraint (Min=0mil) (Max=1000mil) (Prefered=500mil) (All) 0
Differential Pairs Uncoupled Length using the Gap Constraints (Min=10mil) (Max=100mil) (Prefered=10mil) and Width Constraints (Min=15mil) (Max=15mil) (Prefered=15mil) (All) 0
Hole To Hole Clearance (Gap=10mil) (All),(All) 0
Minimum Solder Mask Sliver (Gap=0.7mil) (InComponentClass('Logo')),(InComponentClass('Logo')) 0
Minimum Solder Mask Sliver (Gap=3.937mil) (All),(All) 0
Silk To Solder Mask (Clearance=5mil) (IsPad and InAnycomponent),(All) 1
Silk To Solder Mask (Clearance=4mil) (All),(All) 20
Silk to Silk (Clearance=0mil) ((HasFootprint('Pb-Free_Overlay_Medium') OR HasFootprint('Pb-Free_Overlay_Small'))),((HasFootprint('Pb-Free_Overlay_Medium') OR HasFootprint('Pb-Free_Overlay_Small'))) 0
Silk to Silk (Clearance=4mil) (All),(All) 0
Net Antennae (Tolerance=0mil) (All) 0
Board Clearance Constraint (Gap=0mil) (OnCopper and InComponentClass('Mounting Holes')) 0
Board Clearance Constraint (Gap=0mil) (OnCopper and InPoly) 0
Board Clearance Constraint (Gap=0mil) (OnCopper and Not InComponentClass('Logo') and not InComponentClass('FiducialMark') and not InRegion(1000,500,4000,800)) 0
Clearance Constraint (Gap=5mil) (IsStitchingVia and InNet('No Net')),((IsVia and (Not IsStitchingVia)) Or IsPad) 0
Total 51

Routing Via (MinHoleWidth=7.874mil) (MaxHoleWidth=40mil) (PreferredHoleWidth=16mil) (MinWidth=26mil) (MaxWidth=65mil) (PreferedWidth=34mil) (All)
Routing Via Style: Via (1280mil,2400mil) from Top Layer to Bottom Layer Actual Size : 20mil Actual Hole Size : 10mil
Routing Via Style: Via (1250mil,2400mil) from Top Layer to Bottom Layer Actual Size : 20mil Actual Hole Size : 10mil
Routing Via Style: Via (1280mil,2430mil) from Top Layer to Bottom Layer Actual Size : 20mil Actual Hole Size : 10mil
Routing Via Style: Via (1250mil,2430mil) from Top Layer to Bottom Layer Actual Size : 20mil Actual Hole Size : 10mil
Routing Via Style: Via (1280mil,2230mil) from Top Layer to Bottom Layer Actual Size : 20mil Actual Hole Size : 10mil
Routing Via Style: Via (1280mil,2200mil) from Top Layer to Bottom Layer Actual Size : 20mil Actual Hole Size : 10mil
Routing Via Style: Via (1250mil,2200mil) from Top Layer to Bottom Layer Actual Size : 20mil Actual Hole Size : 10mil
Routing Via Style: Via (1250mil,2230mil) from Top Layer to Bottom Layer Actual Size : 20mil Actual Hole Size : 10mil
Routing Via Style: Via (900mil,1660mil) from Top Layer to Bottom Layer Actual Size : 20mil Actual Hole Size : 10mil
Routing Via Style: Via (850mil,1600mil) from Top Layer to Bottom Layer Actual Size : 20mil Actual Hole Size : 10mil
Routing Via Style: Via (960mil,1750mil) from Top Layer to Bottom Layer Actual Size : 20mil Actual Hole Size : 10mil
Routing Via Style: Via (1350mil,1970mil) from Top Layer to Bottom Layer Actual Size : 20mil Actual Hole Size : 10mil
Routing Via Style: Via (1130mil,1870mil) from Top Layer to Bottom Layer Actual Size : 20mil Actual Hole Size : 10mil
Routing Via Style: Via (1160mil,1870mil) from Top Layer to Bottom Layer Actual Size : 20mil Actual Hole Size : 10mil
Routing Via Style: Via (3674.41mil,924.409mil) from Top Layer to Bottom Layer Actual Size : 20mil Actual Hole Size : 10mil
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Minimum Annular Ring (Minimum=8mil) (All)
Minimum Annular Ring: (5mil < 8mil) Via (1280mil,2400mil) from Top Layer to Bottom Layer (Annular Ring=5mil) On (Top Layer)
Minimum Annular Ring: (5mil < 8mil) Via (1250mil,2400mil) from Top Layer to Bottom Layer (Annular Ring=5mil) On (Top Layer)
Minimum Annular Ring: (5mil < 8mil) Via (1280mil,2430mil) from Top Layer to Bottom Layer (Annular Ring=5mil) On (Top Layer)
Minimum Annular Ring: (5mil < 8mil) Via (1250mil,2430mil) from Top Layer to Bottom Layer (Annular Ring=5mil) On (Top Layer)
Minimum Annular Ring: (5mil < 8mil) Via (1280mil,2230mil) from Top Layer to Bottom Layer (Annular Ring=5mil) On (Top Layer)
Minimum Annular Ring: (5mil < 8mil) Via (1280mil,2200mil) from Top Layer to Bottom Layer (Annular Ring=5mil) On (Top Layer)
Minimum Annular Ring: (5mil < 8mil) Via (1250mil,2200mil) from Top Layer to Bottom Layer (Annular Ring=5mil) On (Top Layer)
Minimum Annular Ring: (5mil < 8mil) Via (1250mil,2230mil) from Top Layer to Bottom Layer (Annular Ring=5mil) On (Top Layer)
Minimum Annular Ring: (5mil < 8mil) Via (900mil,1660mil) from Top Layer to Bottom Layer (Annular Ring=5mil) On (Top Layer)
Minimum Annular Ring: (5mil < 8mil) Via (850mil,1600mil) from Top Layer to Bottom Layer (Annular Ring=5mil) On (Top Layer)
Minimum Annular Ring: (5mil < 8mil) Via (960mil,1750mil) from Top Layer to Bottom Layer (Annular Ring=5mil) On (Top Layer)
Minimum Annular Ring: (5mil < 8mil) Via (1350mil,1970mil) from Top Layer to Bottom Layer (Annular Ring=5mil) On (Top Layer)
Minimum Annular Ring: (5mil < 8mil) Via (1130mil,1870mil) from Top Layer to Bottom Layer (Annular Ring=5mil) On (Top Layer)
Minimum Annular Ring: (5mil < 8mil) Via (1160mil,1870mil) from Top Layer to Bottom Layer (Annular Ring=5mil) On (Top Layer)
Minimum Annular Ring: (5mil < 8mil) Via (3674.41mil,924.409mil) from Top Layer to Bottom Layer (Annular Ring=5mil) On (Top Layer)
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Silk To Solder Mask (Clearance=5mil) (IsPad and InAnycomponent),(All)
Silk To Solder Mask Clearance Constraint: (1.155mil < 5mil) Between Text "U1" (1300mil,1850mil) on Top Overlay And Pad U1-6(1270.709mil,1900.63mil) on Top Layer [Top Overlay] to [Top Solder] clearance [1.155mil]
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Silk To Solder Mask (Clearance=4mil) (All),(All)
Silk To Solder Mask Clearance Constraint: (1.074mil < 4mil) Between Arc (2459.685mil,2050.63mil) on Top Overlay And Area Fill (2000mil,2010mil) (2480mil,2180mil) on Top Solder [Top Overlay] to [Top Solder] clearance [1.074mil]
Silk To Solder Mask Clearance Constraint: (1.074mil < 4mil) Between Arc (2459.685mil,2529.37mil) on Top Overlay And Area Fill (2000mil,2400mil) (2480mil,2570mil) on Top Solder [Top Overlay] to [Top Solder] clearance [1.074mil]
Silk To Solder Mask Clearance Constraint: (1.074mil < 4mil) Between Arc (2020.315mil,2529.37mil) on Top Overlay And Area Fill (2000mil,2400mil) (2480mil,2570mil) on Top Solder [Top Overlay] to [Top Solder] clearance [1.074mil]
Silk To Solder Mask Clearance Constraint: (1.074mil < 4mil) Between Arc (2020.315mil,2050.63mil) on Top Overlay And Area Fill (2000mil,2010mil) (2480mil,2180mil) on Top Solder [Top Overlay] to [Top Solder] clearance [1.074mil]
Silk To Solder Mask Clearance Constraint: (3.193mil < 4mil) Between Track (1783.307mil,783.19mil)(1783.307mil,936.24mil) on Top Overlay And Area Fill (1790mil,850mil) (1910mil,1130mil) on Top Solder [Top Overlay] to [Top Solder] clearance [3.193mil]
Silk To Solder Mask Clearance Constraint: (3.193mil < 4mil) Between Track (1783.307mil,1043.76mil)(1783.307mil,1196.81mil) on Top Overlay And Area Fill (1790mil,850mil) (1910mil,1130mil) on Top Solder [Top Overlay] to [Top Solder] clearance [3.193mil]
Silk To Solder Mask Clearance Constraint: (3.193mil < 4mil) Between Track (1783.307mil,1233.19mil)(1783.307mil,1386.24mil) on Top Overlay And Area Fill (1790mil,1300mil) (1910mil,1580mil) on Top Solder [Top Overlay] to [Top Solder] clearance [3.193mil]
Silk To Solder Mask Clearance Constraint: (3.193mil < 4mil) Between Track (1783.307mil,1493.76mil)(1783.307mil,1646.81mil) on Top Overlay And Area Fill (1790mil,1300mil) (1910mil,1580mil) on Top Solder [Top Overlay] to [Top Solder] clearance [3.193mil]
Silk To Solder Mask Clearance Constraint: (3.193mil < 4mil) Between Track (3073.19mil,1846.693mil)(3226.24mil,1846.693mil) on Top Overlay And Area Fill (3190mil,1730mil) (3490mil,1840mil) on Top Solder [Top Overlay] to [Top Solder] clearance [3.193mil]
Silk To Solder Mask Clearance Constraint: (Collision < 4mil) Between Track (3404.016mil,1433.307mil)(3486.693mil,1515.984mil) on Top Overlay And Area Fill (3210mil,1450mil) (3470mil,1560mil) on Top Solder [Top Overlay] to [Top Solder] clearance [0mil]
Silk To Solder Mask Clearance Constraint: (Collision < 4mil) Between Track (3486.693mil,1515.984mil)(3486.693mil,1846.737mil) on Top Overlay And Area Fill (3190mil,1730mil) (3490mil,1840mil) on Top Solder [Top Overlay] to [Top Solder] clearance [0mil]
Silk To Solder Mask Clearance Constraint: (3.193mil < 4mil) Between Track (3333.76mil,1846.693mil)(3486.81mil,1846.693mil) on Top Overlay And Area Fill (3190mil,1730mil) (3490mil,1840mil) on Top Solder [Top Overlay] to [Top Solder] clearance [3.193mil]
Silk To Solder Mask Clearance Constraint: (3.193mil < 4mil) Between Track (2623.19mil,1846.693mil)(2776.24mil,1846.693mil) on Top Overlay And Area Fill (2740mil,1730mil) (3040mil,1840mil) on Top Solder [Top Overlay] to [Top Solder] clearance [3.193mil]
Silk To Solder Mask Clearance Constraint: (Collision < 4mil) Between Track (2954.016mil,1433.307mil)(3036.693mil,1515.984mil) on Top Overlay And Area Fill (2760mil,1450mil) (3020mil,1560mil) on Top Solder [Top Overlay] to [Top Solder] clearance [0mil]
Silk To Solder Mask Clearance Constraint: (Collision < 4mil) Between Track (3036.693mil,1515.984mil)(3036.693mil,1846.737mil) on Top Overlay And Area Fill (2740mil,1730mil) (3040mil,1840mil) on Top Solder [Top Overlay] to [Top Solder] clearance [0mil]
Silk To Solder Mask Clearance Constraint: (3.193mil < 4mil) Between Track (2883.76mil,1846.693mil)(3036.81mil,1846.693mil) on Top Overlay And Area Fill (2740mil,1730mil) (3040mil,1840mil) on Top Solder [Top Overlay] to [Top Solder] clearance [3.193mil]
Silk To Solder Mask Clearance Constraint: (3.076mil < 4mil) Between Track (3036.576mil,2133.307mil)(3036.576mil,2340mil) on Top Overlay And Area Fill (2760mil,2143.307mil) (3030mil,2300mil) on Top Solder [Top Overlay] to [Top Solder] clearance [3.076mil]
Silk To Solder Mask Clearance Constraint: (3.193mil < 4mil) Between Track (2896.812mil,2546.693mil)(2963.741mil,2546.693mil) on Top Overlay And Area Fill (2760mil,2380mil) (3020mil,2540mil) on Top Solder [Top Overlay] to [Top Solder] clearance [3.193mil]
Silk To Solder Mask Clearance Constraint: (Collision < 4mil) Between Track (2963.741mil,2546.693mil)(3036.576mil,2473.858mil) on Top Overlay And Area Fill (2760mil,2380mil) (3020mil,2540mil) on Top Solder [Top Overlay] to [Top Solder] clearance [0mil]
Silk To Solder Mask Clearance Constraint: (3.193mil < 4mil) Between Track (2696.025mil,2546.693mil)(2760.985mil,2546.693mil) on Top Overlay And Area Fill (2760mil,2380mil) (3020mil,2540mil) on Top Solder [Top Overlay] to [Top Solder] clearance [3.193mil]
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