Reduction of power consumption makes a device more reliable. The need for devices that consume a minimum amount of power was a major driving force behind the development of CMOS technologies. As a result, CMOS devices are best known for low power consumption.
However, for minimizing the power requirements of a board or a system, simply knowing that CMOS devices may use less power than equivalent devices from other technologies does not help much.
It is important to know not only how to calculate power consumption, but also to understand how factors such as input voltage level, input rise time, power-dissipation capacitance, and output loading affect the power consumption of a device.
This application report addresses the different types of power consumption in a CMOS logic circuit, focusing on calculation of power-dissipation capacitance (Cpd ), and, finally, the determination of total power consumption in a CMOS device.
The main topics discussed are:
* Power-consumption components
* Static power consumption
* Dynamic power consumption
* Power-dissipation capacitance (Cpd ) in CMOS circuits
* Cpd comparison among different families
* Power economy