WEBENCH® Clock Architect

Complete, optimized clock tree solutions in minutes

WEBENCH Clock Architect truly provides a quick and easy clock tree solution optimized for your system requirements. Output clock phase noise simulations match real silicon performance. Pulling from an extensive database of clock generators, jitter cleaners, and buffers, Clock Architect delivers system-level clock tree selection, simulation, and device configuration in minutes.


  • Recommends a system clock tree solution with one or more parts
  • Allows user to customize PLL loop filter design
  • Simulates end-to-end phase noise of the output clocks
  • Cascades noise from a device upstream in the solution to a downstream device


WEBENCH® Designer

TI clock design tool suite

  WEBENCH Clock Architect WEBENCH EasyPLL Clock Design Tool
  Released Phasing Out Phasing Out
Multiple Device Solutions Yes No No
Shows Part Area Yes No No
Shows Cost Yes Yes No
Supports All Products
Yes No No
Approximate Current Calculation Yes No No
Calculates Phase Noise and Integrated Phase Noise Quantities
(Jitter, EVM, etc.)
Yes Yes Yes
Fractional Simulations
(Delta Sigma Modulator Noise, Fractional Spurs)
Coming Yes Yes
Calculates Lock Time Coming Yes No
Calculates Digital VCO calibration Time Coming Yes No
Bode Plot Yes Yes Yes
Passive Loop Filter Design Yes Yes Yes
Active Loop Filter Design Yes Yes No
Interface with EVM Software Coming None None

If you’re interested in programming clocks rather than simulation, download TI’s CodeLoader software for

To find out how to use the NEW features of Clock Architect for your next clock tree design, see the Clock Architect instructions