Clock Jitter Cleaners - improve overall system performance

Industry’s lowest power/jitter JESD204B compliant jitter cleaners

Jitter Cleaner Diagram
  • Ultra low jitter :
  • 65fs typ 12k-20M @ 122.88 MHz
  • 50fs typ 12k-20M @ 1966.08 MHz
  • Ultra low inband phase noise through leading BiCMOS technology
Lower system cost
  • Industry’s first and most popular JESD204B jitter cleaner family LMK0482x
  • Supports JESD204B and non-JESD204B applications with a single device
  • Full SYSREF support reduces SoC complexity and cost
  • Multiple SYSREF frequencies from one device
PLL Jitter Cleaner Diagram
  • PLLATINUM dual phase locked loop (PLL) concept reduces cost and improves performance
  • Generates frequencies up to 3GHz with an integrated high performance VCO
  • Innovative semi-digital PLL technique offers best performance, while integrating PLL loop filter components and supporting <5 Hz loop bandwidth

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  LMK04610 LMK04832 LMK04808 LMK04906 CDCM7005-SP
Description High performance dual loop jitter cleaner Ultra Low Noise 3.2GHz Jitter Cleaner, Clock Generator and Distributor High performance dual loop jitter cleaner High performance dual loop jitter cleaner Space grade single loop jitter cleaner
No. of Outputs 10 to 16 14 14 6 5
Output Frequency (Max ) (MHz ) 2000 3202 3072 2600 1500
No. of Inputs 2 to 4 3 2 3 2
RMS Jitter (fs)
12kHz to 20MHz
65 88 111 100 NA - single loop
Applications Wireless, Industrial Wireless, Industrial Wireless, Industrial Wireless, Industrial Space
Special Features
  • Cascaded PLL
  • SPI
  • Holdover mode
  • 105C PCB temp support
  • JESD204B SYSREF support - Multiple SYSREF frequencies from one device
  • Fully integrated loop filter - Fell control via software, <5Hz loop bandwidth
  • Integrated LDOs for 70dBc PSRR
  • Low power with 0.88W @ 10 outputs running
  • 3.3V Vcc/Vdd
  • JESD204B SYSREF Generation
  • Holdover mode
  • Jitter Cleaner
  • Manual and auto switching between inputs
  • SPI
  • uWire
  • Cascaded PLL
  • SPI/uWire
  • Holdover mode
  • Int. XTAL oscillator on PLL1
  • Cascaded PLL
  • SPI/uWire
  • Holdover mode
  • Int. XTAL oscillator on PLL1
  • Single PLL
  • SPI
  • Rad-Tolerant Class V
  • See all jitter cleaners

    Clock Jitter Cleaners videos

    WEBENCH® Clock Architect

    TI's WEBENCH Clock Architect online design tool makes the designer's life easier by generating complete clock-tree solutions. Multiple solutions are generated, each optimized for performance, cost or board space.

    WEBENCH® Designer

    TI’s high performance jitter cleaners are widely used in applications like wireless base stations, remote radio units (RRU), radar, medical and test equipment. A wide range of on-chip features make it easy to synchronize multiple JESD204B data converters and remove jitter from dirty or recovered reference clock ICs.