The XIO1100 is a PCI Express PHY, compliant with the PCI Express Base Specification Revision 1.1 that interfaces the PCI Express Media Access Layer (MAC) to a PCI Express serial link. It uses a modified version of the “PHY Interface for the PCI Express” (PIPE) interface also referred to as a TI-PIPE interface. The TI-PIPE interface is a pin-configurable interface that can be configured as either a 16-bit or an 8-bit interface.

• The 16-bit TI-PIPE interface is a 125 MHz 16-bit parallel interface, a 16 bits output bus (RXDATA) being clocked by the RXCLK output clock, and a 16-bits Input bus (TXDATA) being clocked by the TXCLK input clock. Both buses are clocked using Single Data Rate (SDR) clocking in which the data transitions are on the rising-edge of the associated clock.
• The 8-bit TI-PIPE interface is a 250 MHz 8-bit parallel interface, an 8-bit output bus (RXDATA) being clocked by the RXCLK output clock, and an 8-bit input bus (TXDATA) being clocked by the TXCLK input clock. Both buses are clocked using Double Data Rate (DDR) clocking where the data transitions on both the clock’s rising-edge and falling-edge.