Most semiconductor devices have lifetimes that extend over many years at normal use. However, we cannot wait years to study a device; we have to increase the applied stress. Applied stresses enhance or accelerate potential fail mechanisms, help identify the root cause, and help TI take actions to prevent the failure mode.
In semiconductor devices, some common accelerants are temperature, humidity, voltage, and current. In most cases, the accelerated testing does not change the physics of the failure, but it does shift the time for observation. The shift between accelerated and use condition is known as ‘derating.’
Highly accelerated testing is a key part of JEDEC based qualification tests. The tests below reflect highly accelerated conditions based on JEDEC spec JESD47. If the product passes these tests, the devices are acceptable for most use cases.
|Qualification Test||JEDEC Reference||Applied Stress / Accelerant|
|HTOL||JESD22-A108||Temperature and voltage|
|Temperature cycle||JESD22-A104||Temperature and rate of temp change|
|Temp humidity bias||JESD22-A110||Temperature, voltage, and moisture|
|uHAST||JESD22-A118||Temperature and moisture|
When a static charge moves from one surface to another, it becomes Electrostatic Discharge (ESD) and moves between the two surfaces in a form of a miniature lightning bolt.
When a static charge moves, it becomes a current that can damage or destroy gate oxide, metal layers, and junctions.
JEDEC tests ESD in two different ways:
A component level stress developed to simulate the action of a human body discharging accumulated static charge through a device to ground.
A component level stress that simulates charging and discharging events that occur in production equipment and processes, per the JEDEC JESD22-C101 specification.