System-Level ESD has become increasingly demanding with silicon technology scaling towards lower voltages and the need for designing cost-effective and ultra-low power components. This application report addresses three different ESD topics to help board designers and OEMs understand and design robust system-level designs:
(1) Component-level ESD testing and system-level ESD testing, their differences and why component-level ESD rating does not ensure system-level robustness.
(2) General design guidelines for system-level ESD protection at different levels including enclosures, cables, PCB layout, and on-board ESD protection devices.
(3) Introduction to System Efficient ESD Design (SEED - a co-design methodology of on-board and on-chip ESD protection to achieve system-level ESD robustness) with example simulations and test results.
A few real-world system-level ESD protection design examples and their results are also discussed.