Processors

C55X Core Benchmarks

The benchmarks in the table below are for a C55x DSP core running C55x DSPLIB routines.

All benchmarks measured with code and data in internal memory
1 FFT HW accelerator is used
2 Assumes even number of elements
3 Number of elements can be even or odd

Processor core C55x DSP Core
Hardware platform used C5535/C5545 eZdsp™ Board
Devices featuring benchmarked core C5545
C553x
C5514/C5515/C5517
C5504/C5505
Function benchmarked C55x execution time C55x power consumption in mW C55x DSPLIB routine
C55x cycles C55x μS @ 100MHz
Complex FFT (256 pts, 16- bit) using HW accelerator 1136 11.36 20.70 NONE1
Complex FFT (256 pts, 16- bit) with scaling 5366 53.66 23.40 CFFT
Bit reversal 521 5.21 23.42 Bitrev
Real FIR filter (even elements): 256 tap, 32 16-bit samples2 4247 42.47 19.40 FIR2
Real FIR filter (even or odd elements): 256 tap, 32 16-bit samples3 8309 83.09 17.58 FIR
Real Convolution: 80 taps, 80 16-bit samples 3285 32.85 19.00 Convol2
Real Auto-correlation: 80 taps, 80 values 3456 34.56 18.46 Acor
Delayed LMS filter: 32 taps, 64 values, step = 327 4474 44.74 23.21 DLMS
Delayed LMS filter (fast version): 32 taps, 64 values, step = 327 4372 43.72 21.67 DLMS fast
Real Vector max value only (not index): 100 values 77 0.77 17.94 maxval
Real Vector max value and index: 100 values 322 3.22 17.09 maxvec

Download the TI DSP Benchmarking application note to learn how to reproduce these benchmarks on TI hardware.

C55x power in mW