SPRS932E December 2015  – June 2017 66AK2G01 , 66AK2G02

ADVANCE INFORMATION for pre-production products; subject to change without notice. 

  1. 1Device Overview
    1. 1.1Features
    2. 1.2Applications
    3. 1.3 Description
    4. 1.4Functional Block Diagram
  2. 2Revision History
  3. 3Device Comparison
    1. 3.1Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1Pin Diagram
    2. 4.2Pin Attributes
    3. 4.3Signal Descriptions
      1. 4.3.1 DSS
      2. 4.3.2 DDR EMIF
      3. 4.3.3 GPMC
      4. 4.3.4 Timers
      5. 4.3.5 I2C
      6. 4.3.6 UART
      7. 4.3.7 SPI
      8. 4.3.8 QSPI
      9. 4.3.9  McASP
      10. 4.3.10USB
      11. 4.3.11PCIESS
      12. 4.3.12DCAN
      13. 4.3.13EMAC
      14. 4.3.14MLB
      15. 4.3.15McBSP
      16. 4.3.16MMC/SD
      17. 4.3.17GPIO
      18. 4.3.18ePWM
      19. 4.3.19PRU-ICSS
      20. 4.3.20Emulation and Debug Subsystem
      21. 4.3.21System and Miscellaneous
        1. 4.3.21.1Boot Mode Configuration
        2. 4.3.21.2Reset
        3. 4.3.21.3Oscillator Reference Clocks and Clock Generator
        4. 4.3.21.4Miscellaneous
        5. 4.3.21.5Interrupt Controllers (INTC)
        6. 4.3.21.6Power Supplies
    4. 4.4Pin Multiplexing
    5. 4.5Connections for Unused Pins
  5. 5Specifications
    1. 5.1Absolute Maximum Ratings
    2. 5.2ESD Ratings
    3. 5.3Power-On-Hour (POH) Limits
    4. 5.4Recommended Operating Conditions
    5. 5.5Operating Performance Points
    6. 5.6Power Consumption Summary
    7. 5.7Electrical Characteristics
      1. 5.7.1USB0_PHY and USB1_PHY DC Electrical Characteristics
      2. 5.7.2SERDES/CML DC Electrical Characteristics
    8. 5.8Thermal Resistance Characteristics for ZBB Package
    9. 5.9Timing and Switching Characteristics
      1. 5.9.1Power Supply Sequencing
      2. 5.9.2Reset Timing
        1. 5.9.2.1Reset Electrical Data/Timing
      3. 5.9.3Clock Specifications
        1. 5.9.3.1Input Clocks / Oscillators
          1. 5.9.3.1.1OSC0 External Crystal
          2. 5.9.3.1.2External Single-ended Input Clock
          3. 5.9.3.1.3External Differential Input Clock
        2. 5.9.3.2Output Clocks
        3. 5.9.3.3PLLs
          1. 5.9.3.3.1DDR_PLL Settings
          2. 5.9.3.3.2DLL Characteristics
        4. 5.9.3.4System Clocks Operating Frequency Ranges
        5. 5.9.3.5Device Inputs and Outputs Module Clocks Frequencies
        6. 5.9.3.6Recommended Clock and Control Signal Transition Behavior
        7. 5.9.3.7Interface Clock Specifications
          1. 5.9.3.7.1Interface Clock Terminology
          2. 5.9.3.7.2Interface Clock Frequency
      4. 5.9.4Peripherals
        1. 5.9.4.1 DCAN
        2. 5.9.4.2 DSS
        3. 5.9.4.3 DDR EMIF
        4. 5.9.4.4 EMAC
          1. 5.9.4.4.1EMAC MDIO Interface Timings
          2. 5.9.4.4.2EMAC MII Timings
          3. 5.9.4.4.3EMAC RMII Timings
          4. 5.9.4.4.4EMAC RGMII Timings
        5. 5.9.4.5 GPMC
          1. 5.9.4.5.1GPMC and NOR Flash—Synchronous Mode
          2. 5.9.4.5.2GPMC and NOR Flash—Asynchronous Mode
          3. 5.9.4.5.3GPMC and NAND Flash—Asynchronous Mode
        6. 5.9.4.6 I2C
        7. 5.9.4.7 McASP
        8. 5.9.4.8 McBSP
        9. 5.9.4.9 MLB
        10. 5.9.4.10MMC/SD
        11. 5.9.4.11PCIESS
        12. 5.9.4.12PRU-ICSS
          1. 5.9.4.12.1Programmable Real-Time Unit (PRU-ICSS PRU)
            1. 5.9.4.12.1.1PRU-ICSS PRU Direct Input/Output Mode Electrical Data and Timing
            2. 5.9.4.12.1.2PRU-ICSS PRU Parallel Capture Mode Electrical Data and Timing
            3. 5.9.4.12.1.3 PRU-ICSS PRU Shift Mode Electrical Data and Timing
          2. 5.9.4.12.2 PRU-ICSS EtherCAT (PRU-ICSS ECAT)
            1. 5.9.4.12.2.1PRU-ICSS ECAT Electrical Data and Timing
          3. 5.9.4.12.3PRU-ICSS MII_RT and Switch
            1. 5.9.4.12.3.1PRU-ICSS MDIO Electrical Data and Timing
            2. 5.9.4.12.3.2PRU-ICSS MII_RT Electrical Data and Timing
          4. 5.9.4.12.4PRU-ICSS Universal Asynchronous Receiver Transmitter (PRU-ICSS UART)
          5. 5.9.4.12.5 PRU-ICSS PRU Sigma Delta and EnDAT Modes
        13. 5.9.4.13QSPI
        14. 5.9.4.14SPI
          1. 5.9.4.14.1SPI—Slave Mode
          2. 5.9.4.14.2SPI—Master Mode
        15. 5.9.4.15Timers
        16. 5.9.4.16UART
        17. 5.9.4.17USB
      5. 5.9.5Emulation and Debug Subsystem
        1. 5.9.5.1IEEE 1149.1 Standard-Test-Access Port (JTAG)
          1. 5.9.5.1.1JTAG Electrical Data and Timing
  6. 6Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 ARM A15
    4. 6.4 C66x DSP Subsystem
    5. 6.5 C66x Cache Subsystem
    6. 6.6 PRU-ICSS
    7. 6.7 Memory Subsystem
      1. 6.7.1MSMC
      2. 6.7.2DDR EMIF
      3. 6.7.3GPMC
      4. 6.7.4ELM
    8. 6.8 Interprocessor Communication
      1. 6.8.1MSGMGR
      2. 6.8.2SEM
    9. 6.9 EDMA
    10. 6.10Peripherals
      1. 6.10.1 DCAN
      2. 6.10.2 DSS
      3. 6.10.3 eCAP
      4. 6.10.4 ePWM
      5. 6.10.5 eQEP
      6. 6.10.6 GPIO
      7. 6.10.7 I2C
      8. 6.10.8 McASP
      9. 6.10.9 McBSP
      10. 6.10.10MLB
      11. 6.10.11MMC/SD
      12. 6.10.12NSS
      13. 6.10.13PCIESS
      14. 6.10.14QSPI
      15. 6.10.15SPI
      16. 6.10.16Timers
      17. 6.10.17UART
      18. 6.10.18USB
  7. 7Applications, Implementation, and Layout
    1. 7.1DDR3L Board Design and Layout Guidelines
      1. 7.1.1DDR3L General Board Layout Guidelines
      2. 7.1.2DDR3L Board Design and Layout Guidelines
        1. 7.1.2.1 Board Designs
        2. 7.1.2.2 DDR3L Device Combinations
        3. 7.1.2.3 DDR3L Interface Schematic
          1. 7.1.2.3.132-Bit DDR3L Interface
          2. 7.1.2.3.216-Bit DDR3L Interface
        4. 7.1.2.4 Compatible JEDEC DDR3L Devices
        5. 7.1.2.5 PCB Stackup
        6. 7.1.2.6 Placement
        7. 7.1.2.7 DDR3L Keepout Region
        8. 7.1.2.8 Bulk Bypass Capacitors
        9. 7.1.2.9 High-Speed Bypass Capacitors
          1. 7.1.2.9.1Return Current Bypass Capacitors
        10. 7.1.2.10Net Classes
        11. 7.1.2.11DDR3L Signal Termination
        12. 7.1.2.12VREF_DDR Routing
        13. 7.1.2.13VTT
        14. 7.1.2.14CK and ADDR_CTRL Topologies and Routing Definition
          1. 7.1.2.14.1Four DDR3L Devices
            1. 7.1.2.14.1.1CK and ADDR_CTRL Topologies, Four DDR3L Devices
            2. 7.1.2.14.1.2CK and ADDR_CTRL Routing, Four DDR3L Devices
          2. 7.1.2.14.2One DDR3L Device
            1. 7.1.2.14.2.1CK and ADDR_CTRL Topologies, One DDR3L Device
            2. 7.1.2.14.2.2CK and ADDR/CTRL Routing, One DDR3L Device
        15. 7.1.2.15Data Topologies and Routing Definition
          1. 7.1.2.15.1DQS and DQ/DM Topologies, Any Number of Allowed DDR3L Devices
          2. 7.1.2.15.2DQS and DQ/DM Routing, Any Number of Allowed DDR3L Devices
        16. 7.1.2.16Routing Specification
          1. 7.1.2.16.1CK and ADDR_CTRL Routing Specification
          2. 7.1.2.16.2DQS and DQ Routing Specification
    2. 7.2High Speed Differential Signal Routing Guidance
    3. 7.3Power Distribution Network Implementation Guidance
    4. 7.4Single-Ended Interfaces
      1. 7.4.1General Routing Guidelines
    5. 7.5Clock Routing Guidelines
      1. 7.5.1Oscillator Routing
      2. 7.5.2Oscillator Ground Connection
  8. 8Device and Documentation Support
    1. 8.1Device Nomenclature
    2. 8.2Tools and Software
    3. 8.3Documentation Support
    4. 8.4Related Links
    5. 8.5Receiving Notification of Documentation Updates
    6. 8.6Community Resources
    7. 8.7Trademarks
    8. 8.8Electrostatic Discharge Caution
    9. 8.9Glossary
  9. 9Mechanical Packaging and Orderable Information

Device Overview

Features

  • Processor Cores:
  • ARM® Cortex®-A15 Microprocessor Unit (ARM A15) Subsystem at up to 600 MHz
    • Supports Full Implementation of ARMv7-A Architecture Instruction Set
    • Integrated SIMDv2 (NEON™ Technology) and VFPv4 (Vector Floating Point)
    • 32KB of L1 Program Memory
    • 32KB of L1 Data Memory
    • 512KB of L2 Memory
    • Error Correction Code (ECC) Protection for L1 Data Memory ECC for L2 Memory
    • Parity Protection for L1 Program Memory
    • Global Timebase Counter (GTC)
      • 64-Bit Free-Running Counter That Provides Timebase for ARM A15 Internal Timers
      • Compliant to ARM V7 MPCore Architecture for Generic Timers
  • C66x Fixed- and Floating-Point VLIW DSP Subsystem at up to 600 MHz
    • Fully Object-Code Compatible With C67x+ and C64x+ Cores
    • 32KB of L1 Program Memory
    • 32KB of L1 Data Memory
    • 1024KB of L2 Configurable as L2 RAM or Cache
    • Error Detection for L1 Program Memory
    • ECC for L1 Data Memory
    • ECC for L2 Data Memory
  • Industrial Subsystem:
  • Up to Two Programmable Real-Time Unit and Industrial Communication Subsystems (PRU-ICSS), Each Supports:
    • Two Programmable Real-Time Units (PRUs) With Enhanced Multiplier and Accumulator, Each PRU Supports:
      • 16KB of Program Memory With ECC
      • 8KB of Data Memory With ECC
      • CRC32 and CRC16 Hardware Accelerator
      • 20 × Enhanced GPIO
      • Serial Capture Unit (SCU), Supporting Direct Connection, 16-bit Parallel Capture, 28-bit Shift, MII_RT, EnDat 2.2 Protocol and Sigma-Delta Demodulation
      • Scratch Pad and XFR Direct Connect
    • 64KB of General-Purpose Memory With ECC
    • One Ethernet MII_RT Module with Two MII Ports Configurable for Connection With Each PRU; Support Multiple Industrial Communication Protocols
    • Industrial Ethernet Peripheral (IEP) to Manage and Generate Industrial Ethernet Functions
    • Built-In Universal Asynchronous Receiver and Transmitter (UART) 16550, With a Dedicated 192-MHz Clock to Support 12-Mbps PROFIBUS®
    • Built-In Industrial Ethernet 64-Bit Timer
    • Built-In Enhanced Capture Module (eCAP)
  • Memory Subsystem:
  • Multicore Shared Memory Controller (MSMC) With 1024KB of Shared L2 RAM
    • Provides High-Performance Interconnect to Internal Shared SRAM and DDR EMIF for Both ARM A15 and C66x Access
    • Supports ARM I/O Coherency Where ARM A15 is Cache Coherent to Other System Masters Accessing the MSMC-SRAM or DDR EMIF
    • Supports ECC on SRAM
  • Up to 36-Bit DDR External Memory Interface (EMIF)
    • Supports DDR3L at up to 800 MT/s
    • Supports 4-GB Memory Address Range
    • Supports 32-Bit SDRAM Data Bus With 4-bit ECC
    • Supports 16-Bit and 32-Bit SDRAM Data Bus Without ECC
  • General-Purpose Memory Controller (GPMC)
    • Flexible 8- and 16-Bit Asynchronous Memory Interface With up to Four Chip Selects
    • Supports NAND, NOR, Muxed-NOR, SRAM
    • Supports General-Purpose Memory-Port Expansion With the Following Modes:
      • Asynchronous Read and Write Access
      • Asynchronous Read Page Access (4-, 8-, 16-Word16)
      • Synchronous Read and Write Access
      • Synchronous Read Burst Access Without Wrap Capability (4-, 8-, 16-Word16)
    • Up to 16-Bit ECC Support for NAND Flash Using BCH Code (t = 4, 8, or 16) or Hamming Code
  • Error Location Module (ELM)
    • Used With the GPMC to Locate Addresses of Data Errors From Syndrome Polynomials Generated Using a BCH Algorithm
    • Supports 4-Bit, 8-Bit and 16-Bit per 512-Byte Block Error Location Based on BCH Algorithms
    • Provides ECC Calculation (Up to 16 bits) for NAND Support
  • Network Subsystem (NSS):
  • Ethernet MAC Subsystem (EMAC)
    • One-Port Gigabit Ethernet: RMII, MII, RGMII
    • Supports 10-, 100-, 1000-Mbps Full Duplex
    • Supports 10-, 100-Mbps Half Duplex
    • Supports Ethernet Audio Video Bridging (eAVB)
    • Maximum Frame Size 2016 Bytes (2020 Bytes With VLAN)
    • Eight Priority Level QOS Support (802.1p)
    • IEEE 1588v2 (2008 Annex D, Annex E, and
      Annex F) to Facilitate Audio Video Bridging 802.1AS Precision Time Protocol
    • CPTS Module With Timestamping Support for IEEE 1588v2
    • DSCP Priority Mapping (IPv4 and IPv6)
    • MDIO Module for PHY Management
    • Enhanced Statistics Collection
  • Navigator Subsystem (NAVSS)
    • Built-In Packet DMA Controller for Optimized Network Processing
    • Built-In Queue Manager (QM) for Optimized Network Processing
      • Supports up to 128 Queues
      • 2048 Buffers Supported in Internal Queue RAM
  • Crypto Engine (SA) Supports:
    • Crypto Function Library for AES, DES, 3DES, SHA1, MD5, SHA2-224 and SHA2-256 Operations
    • Block Data Encryption Supported Through Hardware Cores
      • AES With 128-, 192-, and 256-Bit Key Supports
      • DES and 3DES With 1, 2, or 3 Different Key Support
    • Programmable Mode Control Engine (MCE)
    • Public Key Accelerator (PKA) With Elliptic Curve Cryptography
    • Elliptic Curve Diffie–Hellman (ECDH) Based Key Exchange and Digital Signature (ECDSA) Applications
    • Authentication for SHA1, MD5, SHA2-224 and SHA2-256
    • Keyed HMAC Operation Through Hardware Core
    • True Random Number Generator (TRNG)
  • Display Subsystem:
  • Supports One Video Pipe With In-Loop Scaling, Color Space
  • Conversion and Background Color Overlay
  • Input Data Format: BITMAP, RGB16, RGB24, RGB32, ARGB16, ARGB32, YUV420, YUV422, and RGB565-A8
  • Supported Display Interfaces:
    • MIPI® DPI 2.0 Parallel Interface
    • RFBI (MIPI-DBI 2.0) up to QVGA at 30fps
    • BT.656 4:2:2
    • BT.1120 4:2:2 up to 1920 × 1080 at 30fps
  • In-Loop Scaling Capability
  • LCD Display Interface Supports:
    • Active Matrix (TFT)
    • Passive Matrix (STN)
    • Grayscale
    • TDM
    • AC Bias Control
    • Dither
    • CPR
  • High-Speed Serial Interfaces:
  • PCI Express® 2.0 Port with Integrated PHY:
    • Single Lane Gen2-Compliant Port
    • Root Complex (RC) and End Point (EP) Modes
  • Up to Two USB 2.0 High-Speed Dual-Role Ports With Integrated PHYs, Support:
    • Dual-role-device (DRD) Capability With:
      • USB 2.0 Peripheral (or Device) at
        HS (480Mbps) and FS (12Mbps) Speeds
      • USB 2.0 Host at HS (480Mbps),
        FS (12Mbps), and LS (1.5Mbps) Speeds
      • USB 2.0 Static Peripheral and Static Host Operations
    • xHCI Controller With the Following Features:
      • Compatible to the xHCI Specification (revision 1.1) in Host Mode
      • All Modes of Transfer (Control, Bulk, Interrupt, and Isochronous)
      • 15 Transmit (TX), 15 Receive (RX) Endpoints (EPs), and One Bidirectional EP0 Endpoint
  • Flash Media Interfaces:
  • QSPI™ With XIP and up to Four Chip Selects, Supports:
    • Memory-Mapped Direct Mode of Operation for Performing FLASH Data Transfers and Executing Code From FLASH Memory (XIP)
    • Supports up to 96 MHz
    • Internal SRAM Buffer With ECC
    • High Speed Read Data Capture Mechanism
  • Two Multimedia Card (MMC) and Secure Digital (SD) Ports
    • Supports JEDEC JESD84 v4.5-A441 and SD3.0 Physical Layer With SDA3.00 Standards
    • MMC0 Supports 3.3-V I/O for:
      • SD DS and HS Mode
      • eMMC Mode HS-SDR and DDR
        up to 48 MHz
    • MMC1 Supports 1.8-V I/O Modes for eMMC, Including HS-SDR and DDR at up to 48 MHz With 4- and 8-Bit Bus Width
  • Audio Peripherals:
  • Three Multichannel Audio Serial Port (McASP) Peripherals
    • Transmit and Receive Clocks up to 50 MHz
    • Two Independent Clock Zones and Independent Transmit and Receive Clocks per McASP
    • Up to 16-, 10-, 6-Serial Data Pins for McASP0, McASP1, and McASP2, Respectively
    • Supports TDM, I2S, and Similar Formats
    • Supports DIT Mode
    • Built-In FIFO Buffers for Optimized System Traffic
  • Multichannel Buffered Serial Port (McBSP)
    • Transmit and Receive Clocks up to 50 MHz
    • Two Clock Zones and Two Serial-Data Pins
    • Supports TDM, I2S, and Similar Formats
  • Automotive Peripherals:
  • Two Controller Area Network (CAN) Ports
    • Supports CAN v2.0 Part A, B (ISO 11898-1) Protocol
    • Bit Rates up to 1 Mbps
    • Dual Clock Source
    • ECC Protection for Message RAM
  • One Media Local Bus (MLB)
    • Supports Both 3-Pin (Up to MOST50, 1024 × Fs) and 6-Pin (Up to MOST150, 2048 × Fs) Versions of MediaLB® Physical Layer Specification v4.2
    • Supports All Types of Data Transfer Over 64 Logical Channels (Synchronous Stream, Isochronous, Asynchronous Packet, Control Message)
    • Supports 3-Wire MOST 150 Protocol
  • Real-Time Control Interfaces:
  • Six Enhanced High Resolution Pulse Width Modulation (eHRPWM) Modules, Each Counter Supports:
    • Dedicated 16-Bit Time-Base With Period and Frequency Control
    • Two Independent PWM Outputs With Single Edge Operation
    • Two Independent PWM Outputs With Dual-Edge Symmetric Operation
    • One Independent PWM Output With Dual-Edge Asymmetric Operation
  • Two 32-Bit Enhanced Capture Modules (eCAP):
    • Supports One Capture Input or One Auxiliary PWM Output Configuration Options
    • 4-Event Time-Stamp Registers (Each 32-Bits)
    • Interrupt on Either of the Four Events
  • Three 32-Bit Enhanced Quadrature Pulse Encoder Modules (eQEP), Each Supports:
    • Quadrature Decoding
    • Position Counter and Control Unit for Position Measurement
    • Unit Time Base for Speed and Frequency Measurement
  • General Connectivity:
  • Three Inter-Integrated Circuit (I2C) Interfaces, Each Supports:
    • Standard (up to 100 kHz) and
      Fast (up to 400 kHz) Modes
    • 7-Bit Addressing Mode
    • Supports EEPROM Size Up to 4Mbit
  • Four Serial Peripheral Interfaces (SPI), Each Supports:
    • Operates at up to 50 MHz in Master Mode and 25 MHz in Slave Mode
    • Two Chip Selects
  • Three UART Interfaces
    • All UARTs are 16C750-Compatible and Operate at Up to 3M Baud
    • UART0 Supports 8 Pins With Full Modem Control, With DSR, DTR, DCD, and RI Signals
    • UART1 and UART2 are 4-Pin Interfaces
  • General-Purpose I/O (GPIO)
    • Up to 212 GPIOs Muxed With Other Interfaces
    • Can be Configured as Interrupt Pins
  • Timers and Miscellaneous Modules:
  • Seven 64-Bit Timers:
    • Two 64-Bit Timers Dedicated to ARM A15 and DSP Cores (One Timer per Core)
      • Watchdog and General-Purpose (GP)
    • Four 64-Bit Timers are Shared for General Purposes
    • Each 64-Bit Timer Can be Configured as Two Individual 32-Bit Timers
    • One 64-Bit Timer Dedicated for PMMC
    • Two Timers Input/Output Pin Pairs
  • Interprocessor Communication With:
    • Message Manager to Facilitate Multiprocessor Access to the PMMC:
      • Provides Hardware Acceleration for Pushing and Popping Messages to/from Logical Queues
      • Supports Up to 64 Queues and 128 Messages
    • Semaphore Module With Up to 64 Independent Semaphores and 16 Masters (device cores)
  • EDMA With 128 (2 × 64) Channels and
    1024 (2 × 512) PaRAM Entries
  • Keystone II System on Chip (SoC) Architecture:
  • Security
    • Supports General-Purpose (GP) and High-Secure (HS) Devices
    • Supports Secure Boot
    • Supports Customer Secondary Keys
    • 4KB of One-Time Programmable (OTP) ROM for Customer Keys
  • Power Management
    • Integrated Power Management Microcontroller (PMMC) Technology
  • Supports Primary Boot From UART, I2C, SPI, GPMC, SD or eMMC, USB Device Firmware Upgrade v1.1, PCIe®, and Ethernet Interfaces
  • Keystone II Debug Architecture With Integrated ARM CoreSight™ Support and Trace Capability
  • Operating Temperature (TJ):
  • –40°C to 125°C (Automotive)
  • –40°C to 105°C (Extended)
  • 0°C to 90°C (Commercial)

Applications

  • Industrial Communications and Controls
  • Automotive Audio Amplifiers
  • Home Audio
  • Professional Audio
  • Power Protection
  • Other Embedded Systems

Description

66AK2G0x is a family of heterogeneous multicore System-on-Chip (SoC) devices based on TI’s field-proven Keystone II (KS2) architecture. These devices address applications that require both DSP and ARM performance, with integration of high-speed peripheral and memory interfaces, hardware acceleration for network and cryptography functions, and high-level operating systems (HLOS) support.

Similar to existing KS2-based SoC devices, the 66AK2G0x enables both the DSP and ARM cores to master all memory and peripherals in the system. This architecture facilitates maximum software flexibility where either DSP- or ARM-centric system designs can be achieved.

The 66AK2G0x significantly improves device reliability by extensively implementing error correction code (ECC) in processor cores, shared memory, embedded memory in modules, and external memory interfaces. Full analysis of soft error rate (SER) and power-on-hours (POH) shows that the designated 66AK2G0x parts satisfy a wide range of industrial and automotive requirements.

Accompanied by the new Processor SDK, the 66AK2G0x development platform enables unprecedented ease-of-use with main line open source Linux, CCS 6.x, a wide range of OS-independent device drivers, as well as TI-RTOS that enables seamless task management across processor cores. The device also features advanced debug and trace technology with the latest innovations from TI and ARM, such as system trace and seamless integration of the ARM CoreSight components.

Secure boot can also be made available for anticloning and illegal software update protection. For more information about secure boot, contact your TI sales representative.

Table 1-1 Device Information(1)

PART NUMBERPACKAGEBODY SIZE
66AK2G02NFBGA (625)21.0 mm × 21.0 mm
66AK2G01NFBGA (625)21.0 mm × 21.0 mm
  1. For more information, see Section 9, Mechanical Packaging and Orderable Information.

Functional Block Diagram

Figure 1-1 is a block diagram of the device.

66AK2G02 66AK2G01 intro_sprs932-001.gif Figure 1-1 Functional Block Diagram