SPRS866G November 2012  – October 2017 66AK2H06 , 66AK2H12 , 66AK2H14

PRODUCTION DATA. 

  1. Device Overview
    1. 1.1Features
    2. 1.2Applications
    3. 1.3Description
      1. 1.3.1Enhancements in KeyStone II
    4. 1.4Functional Block Diagram
  2. Revision History
  3. Device Comparison
    1. 3.1Related Products
  4. Terminal Configuration and Functions
    1. 4.1Package Terminals
    2. 4.2Pin Map
    3. 4.3Terminal Functions
    4. 4.4Pullup/Pulldown Resistors
  5. Specifications
    1. 5.1Absolute Maximum Ratings
    2. 5.2ESD Ratings
    3. 5.3Recommended Operating Conditions
    4. 5.4Power Consumption Summary
    5. 5.5Electrical Characteristics
    6. 5.6Thermal Resistance Characteristics for PBGA Package [AAW]
    7. 5.7Power Supply to Peripheral I/O Mapping
  6. C66x CorePac
    1. 6.1C66x DSP CorePac
    2. 6.2Memory Architecture
      1. 6.2.1L1P Memory
      2. 6.2.2L1D Memory
      3. 6.2.3L2 Memory
      4. 6.2.4Multicore Shared Memory SRAM
      5. 6.2.5L3 Memory
    3. 6.3Memory Protection
    4. 6.4Bandwidth Management
    5. 6.5Power-Down Control
    6. 6.6C66x CorePac Revision
    7. 6.7C66x CorePac Register Descriptions
  7. ARM CorePac
    1. 7.1Features
    2. 7.2System Integration
    3. 7.3ARM Cortex-A15 Processor
      1. 7.3.1Overview
      2. 7.3.2Features
      3. 7.3.3ARM Interrupt Controller
      4. 7.3.4Endianess
    4. 7.4CFG Connection
    5. 7.5Main TeraNet Connection
    6. 7.6Clocking and Reset
      1. 7.6.1Clocking
      2. 7.6.2Reset
  8. Memory, Interrupts, and EDMA for 66AK2Hxx
    1. 8.1Memory Map Summary for 66AK2Hxx
    2. 8.2Memory Protection Unit (MPU) for 66AK2Hxx
      1. 8.2.1MPU Registers
        1. 8.2.1.1MPU Register Map
        2. 8.2.1.2Device-Specific MPU Registers
          1. 8.2.1.2.1Configuration Register (CONFIG)
      2. 8.2.2MPU Programmable Range Registers
        1. 8.2.2.1Programmable Range n Start Address Register (PROGn_MPSAR)
        2. 8.2.2.2Programmable Range n - End Address Register (PROGn_MPEAR)
        3. 8.2.2.3Programmable Range n Memory Protection Page Attribute Register (PROGn_MPPAR)
    3. 8.3Interrupts for 66AK2Hxx
      1. 8.3.1Interrupt Sources and Interrupt Controller
      2. 8.3.2CIC Registers
        1. 8.3.2.1CIC0 Register Map
        2. 8.3.2.2CIC1 Register Map
        3. 8.3.2.3CIC2 Register Map
      3. 8.3.3Inter-Processor Register Map
      4. 8.3.4NMI and LRESET
    4. 8.4Enhanced Direct Memory Access (EDMA3) Controller for 66AK2Hxx
      1. 8.4.1EDMA3 Device-Specific Information
      2. 8.4.2EDMA3 Channel Controller Configuration
      3. 8.4.3EDMA3 Transfer Controller Configuration
      4. 8.4.4EDMA3 Channel Synchronization Events
  9. System Interconnect
    1. 9.1Internal Buses and Switch Fabrics
    2. 9.2Switch Fabric Connections Matrix - Data Space
    3. 9.3TeraNet Switch Fabric Connections Matrix - Configuration Space
    4. 9.4Bus Priorities
  10. 10Device Boot and Configuration
    1. 10.1Device Boot
      1. 10.1.1Boot Sequence
      2. 10.1.2Boot Modes Supported
        1. 10.1.2.1Boot Device Field
        2. 10.1.2.2Device Configuration Field
          1. 10.1.2.2.1Sleep Boot Mode Configuration
          2. 10.1.2.2.2I2C Boot Device Configuration
            1. 10.1.2.2.2.1I2C Passive Mode
            2. 10.1.2.2.2.2I2C Master Mode
          3. 10.1.2.2.3SPI Boot Device Configuration
          4. 10.1.2.2.4EMIF Boot Device Configuration
          5. 10.1.2.2.5NAND Boot Device Configuration
        3. 10.1.2.3Serial Rapid I/O Boot Device Configuration
        4. 10.1.2.4Ethernet (SGMII) Boot Device Configuration
          1. 10.1.2.4.1PCIe Boot Device Configuration
          2. 10.1.2.4.2HyperLink Boot Device Configuration
          3. 10.1.2.4.3UART Boot Device Configuration
        5. 10.1.2.5Boot Parameter Table
          1. 10.1.2.5.1 EMIF16 Boot Parameter Table
          2. 10.1.2.5.2  SRIO Boot Parameter Table
          3. 10.1.2.5.3 Ethernet Boot Parameter Table
          4. 10.1.2.5.4 PCIe Boot Parameter Table
          5. 10.1.2.5.5 I2C Boot Parameter Table
          6. 10.1.2.5.6 SPI Boot Parameter Table
          7. 10.1.2.5.7 HyperLink Boot Parameter Table
          8. 10.1.2.5.8 UART Boot Parameter Table
          9. 10.1.2.5.9 NAND Boot Parameter Table
          10. 10.1.2.5.10DDR3 Configuration Table
        6. 10.1.2.6Second-Level Bootloaders
      3. 10.1.3SoC Security
      4. 10.1.4System PLL Settings
        1. 10.1.4.1ARM CorePac System PLL Settings
    2. 10.2Device Configuration
      1. 10.2.1Device Configuration at Device Reset
      2. 10.2.2Peripheral Selection After Device Reset
      3. 10.2.3Device State Control Registers
        1. 10.2.3.1 Device Status (DEVSTAT) Register
        2. 10.2.3.2 Device Configuration Register
        3. 10.2.3.3 JTAG ID (JTAGID) Register Description
        4. 10.2.3.4 Kicker Mechanism (KICK0 and KICK1) Register
        5. 10.2.3.5 DSP Boot Address Register (DSP_BOOT_ADDRn)
        6. 10.2.3.6 LRESETNMI PIN Status (LRSTNMIPINSTAT) Register
        7. 10.2.3.7 LRESETNMI PIN Status Clear (LRSTNMIPINSTAT_CLR) Register
        8. 10.2.3.8 Reset Status (RESET_STAT) Register
        9. 10.2.3.9 Reset Status Clear (RESET_STAT_CLR) Register
        10. 10.2.3.10Boot Complete (BOOTCOMPLETE) Register
        11. 10.2.3.11Power State Control (PWRSTATECTL) Register
        12. 10.2.3.12NMI Event Generation to C66x CorePac (NMIGRx) Register
        13. 10.2.3.13IPC Generation (IPCGRx) Registers
        14. 10.2.3.14IPC Acknowledgment (IPCARx) Registers
        15. 10.2.3.15IPC Generation Host (IPCGRH) Register
        16. 10.2.3.16IPC Acknowledgment Host (IPCARH) Register
        17. 10.2.3.17Timer Input Selection Register (TINPSEL)
        18. 10.2.3.18Timer Output Selection Register (TOUTPSEL)
        19. 10.2.3.19Reset Mux (RSTMUXx) Register
        20. 10.2.3.20Device Speed (DEVSPEED) Register
        21. 10.2.3.21ARM Endian Configuration Register 0 (ARMENDIAN_CFGr_0), r=0..7
        22. 10.2.3.22ARM Endian Configuration Register 1 (ARMENDIAN_CFGr_1), r=0..7
        23. 10.2.3.23ARM Endian Configuration Register 2 (ARMENDIAN_CFGr_2), r=0..7
        24. 10.2.3.24Chip Miscellaneous Control (CHIP_MISC_CTL0) Register
        25. 10.2.3.25Chip Miscellaneous Control (CHIP_MISC_CTL1) Register
        26. 10.2.3.26System Endian Status Register (SYSENDSTAT)
        27. 10.2.3.27SYNECLK_PINCTL Register
        28. 10.2.3.28USB PHY Control (USB_PHY_CTLx) Registers
  11. 1166AK2Hxx Peripheral Information
    1. 11.1 Recommended Clock and Control Signal Transition Behavior
    2. 11.2 Power Supplies
      1. 11.2.1Power-Up Sequencing
        1. 11.2.1.1Core-Before-IO Power Sequencing
        2. 11.2.1.2IO-Before-Core Power Sequencing
        3. 11.2.1.3Prolonged Resets
        4. 11.2.1.4Clocking During Power Sequencing
      2. 11.2.2Power-Down Sequence
      3. 11.2.3Power Supply Decoupling and Bulk Capacitor
      4. 11.2.4SmartReflex
    3. 11.3 Power Sleep Controller (PSC)
      1. 11.3.1Power Domains
      2. 11.3.2Clock Domains
      3. 11.3.3PSC Register Memory Map
    4. 11.4 Reset Controller
      1. 11.4.1Power-on Reset
      2. 11.4.2Hard Reset
      3. 11.4.3Soft Reset
      4. 11.4.4Local Reset
      5. 11.4.5ARM CorePac Reset
      6. 11.4.6Reset Priority
      7. 11.4.7Reset Controller Register
      8. 11.4.8Reset Electrical Data and Timing
    5. 11.5 Main PLL, ARM PLL, DDR3A PLL, DDR3B PLL, PASS PLL and the PLL Controllers
      1. 11.5.1Main PLL Controller Device-Specific Information
        1. 11.5.1.1Internal Clocks and Maximum Operating Frequencies
        2. 11.5.1.2Local Clock Dividers
        3. 11.5.1.3Module Clock Input
        4. 11.5.1.4Main PLL Controller Operating Modes
        5. 11.5.1.5Main PLL Stabilization, Lock, and Reset Times
      2. 11.5.2PLL Controller Memory Map
        1. 11.5.2.1PLL Secondary Control Register (SECCTL)
        2. 11.5.2.2PLL Controller Divider Register (PLLDIV3 and PLLDIV4)
        3. 11.5.2.3 PLL Controller Clock Align Control Register (ALNCTL)
        4. 11.5.2.4 PLLDIV Divider Ratio Change Status Register (DCHANGE)
        5. 11.5.2.5SYSCLK Status Register (SYSTAT)
        6. 11.5.2.6Reset Type Status Register (RSTYPE)
        7. 11.5.2.7Reset Control Register (RSTCTRL)
        8. 11.5.2.8Reset Configuration Register (RSTCFG)
        9. 11.5.2.9Reset Isolation Register (RSISO)
      3. 11.5.3Main PLL Control Registers
      4. 11.5.4 ARM PLL Control Registers
      5. 11.5.5Main PLL Controller, ARM, SRIO, HyperLink, PCIe, USB Clock Input Electrical Data and Timing
    6. 11.6 DDR3A PLL and DDR3B PLL
      1. 11.6.1DDR3A PLL and DDR3B PLL Control Registers
      2. 11.6.2DDR3A PLL and DDR3B PLL Device-Specific Information
      3. 11.6.3DDR3 PLL Input Clock Electrical Data and Timing
    7. 11.7 PASS PLL
      1. 11.7.1PASS PLL Local Clock Dividers
      2. 11.7.2 PASS PLL Control Registers
      3. 11.7.3PASS PLL Device-Specific Information
      4. 11.7.4PASS PLL Input Clock Electrical Data and Timing
    8. 11.8 External Interrupts
      1. 11.8.1External Interrupts Electrical Data and Timing
    9. 11.9 DDR3A and DDR3B Memory Controllers
      1. 11.9.1DDR3 Memory Controller Device-Specific Information
      2. 11.9.2DDR3 Slew Rate Control
      3. 11.9.3DDR3 Memory Controller Electrical Data and Timing
    10. 11.10I2C Peripheral
      1. 11.10.1I2C Device-Specific Information
      2. 11.10.2I2C Peripheral Register Description
      3. 11.10.3I2C Electrical Data and Timing
    11. 11.11SPI Peripheral
      1. 11.11.1SPI Electrical Data and Timing
    12. 11.12HyperLink Peripheral
    13. 11.13UART Peripheral
    14. 11.14PCIe Peripheral
    15. 11.15Packet Accelerator
    16. 11.16Security Accelerator
    17. 11.17Network Coprocessor Gigabit Ethernet (GbE) Switch Subsystem
    18. 11.18SGMII and XFI Management Data Input/Output (MDIO)
    19. 11.19Ten-Gigabit Ethernet (10GbE) Switch Subsystem
      1. 11.19.110GbE Supported Features
    20. 11.20Timers
      1. 11.20.1Timers Device-Specific Information
      2. 11.20.2Timers Electrical Data and Timing
    21. 11.21Serial RapidIO (SRIO) Port
      1. 11.21.1 Serial RapidIO Device-Specific Information
    22. 11.22General-Purpose Input/Output (GPIO)
      1. 11.22.1GPIO Device-Specific Information
      2. 11.22.2GPIO Peripheral Register Description
      3. 11.22.3GPIO Electrical Data and Timing
    23. 11.23Semaphore2
    24. 11.24Universal Serial Bus 3.0 (USB 3.0)
    25. 11.25EMIF16 Peripheral
      1. 11.25.1EMIF16 Electrical Data and Timing
    26. 11.26Emulation Features and Capability
      1. 11.26.1Chip-Level Features
        1. 11.26.1.1ARM Subsystem Features
        2. 11.26.1.2DSP Features
      2. 11.26.2ICEPick Module
        1. 11.26.2.1ICEPick Dynamic Tap Insertion
    27. 11.27Debug Port (EMUx)
      1. 11.27.1Concurrent Use of Debug Port
      2. 11.27.2Master ID for Hardware and Software Messages
      3. 11.27.3SoC Cross-Triggering Connection
      4. 11.27.4Peripherals-Related Debug Requirement
      5. 11.27.5Advanced Event Triggering (AET)
      6. 11.27.6Trace
        1. 11.27.6.1Trace Electrical Data and Timing
      7. 11.27.7IEEE 1149.1 JTAG
        1. 11.27.7.1IEEE 1149.1 JTAG Compatibility Statement
        2. 11.27.7.2JTAG Electrical Data and Timing
  12. 12Device and Documentation Support
    1. 12.1Device Nomenclature
    2. 12.2Tools and Software
    3. 12.3Documentation Support
    4. 12.4Related Links
    5. 12.5Community Resources
    6. 12.6Trademarks
    7. 12.7Electrostatic Discharge Caution
    8. 12.8Glossary
  13. 13Mechanical, Packaging, and Orderable Information
    1. 13.1Packaging Information

Device Overview

Features

  • Eight TMS320C66x DSP Core Subsystems (C66x CorePacs), Each With
    • 1.0 GHz or 1.2 GHz C66x Fixed- and Floating-Point DSP Core
      • 38.4 GMacs/Core for Fixed Point @ 1.2 GHz
      • 19.2 GFlops/Core for Floating Point @ 1.2 GHz
    • Memory
      • 32-KB L1P Per CorePac
      • 32-KB L1D Per CorePac
      • 1024-KB Local L2 Per CorePac
  • ARM CorePac
    • Four ARM® Cortex®-A15 MPCore™ Processors at up to 1.4 GHz
    • 4MB of L2 Cache Memory Shared by Four ARM Cores
    • Full Implementation of ARMv7-A Architecture Instruction Set
    • 32-KB L1 Instruction and Data Caches per Core
    • AMBA 4.0 AXI Coherency Extension (ACE) Master Port, Connected to MSMC for Low-Latency Access to Shared MSMC SRAM
  • Multicore Shared Memory Controller (MSMC)
    • 6MB of MSM SRAM Memory Shared by Eight DSP CorePacs and One ARM CorePac
    • Memory Protection Unit (MPU) for Both MSM SRAM and DDR3_EMIF
  • Multicore Navigator
    • 16k Multipurpose Hardware Queues With Queue Manager
    • Packet-Based DMA for Zero-Overhead Transfers
  • Network Coprocessor
    • Packet Accelerator Enables Support for
      • Transport Plane IPsec, GTP-U, SCTP, PDCP
      • L2 User Plane PDCP (RoHC, Air Ciphering)
      • 1-Gbps Wire Speed Throughput at 1.5 MPackets Per Second
    • Security Accelerator Engine Enables Support for
      • IPSec, SRTP, 3GPP, and WiMAX Air Interface, and SSL/TLS Security
      • ECB, CBC, CTR, F8, A5/3, CCM, GCM, HMAC, CMAC, GMAC, AES, DES, 3DES, Kasumi, SNOW 3G, SHA-1, SHA-2 (256-Bit Hash), MD5
      • Up to 2.4 Gbps IPSec and 2.4 Gbps Air Ciphering
    • Ethernet Subsystem
      • Five-Port Switch (Four SGMII Ports)
  • Peripherals
    • Four Lanes of SRIO 2.1
      • Supports up to 5 GBaud
      • Supports Direct I/O, Message Passing
    • Two Lanes PCIe Gen2
      • Supports up to 5 GBaud
    • Two HyperLinks
      • Supports Connections to Other KeyStone™ Architecture Devices Providing Resource Scalability
      • Supports up to 50 GBaud
    • 10-Gigabit Ethernet (10-GbE) Switch Subsystem (66AK2H14 Only)
      • Two XFI Ports
      • IEEE 1588 Support
    • Five Enhanced Direct Memory Access (EDMA) Modules
    • Two 72-Bit DDR3/DDR3L Interfaces With Speeds up to 1600 MHz
    • EMIF16 Interface
    • USB 3.0
    • Two UART Interfaces
    • Three I2C Interfaces
    • 32 GPIO Pins
    • Three SPI Interfaces
    • Semaphore Module
    • 64-Bit Timers
      • Twenty 64-Bit Timers for 66AK2H14 and 66AK2H12
      • Fourteen 64-Bit Timers for 66AK2H06
    • Five On-Chip PLLs
  • Commercial Case Temperature:
    • 0ºC to 85ºC
  • Extended Case Temperature:
    • –40ºC to 100ºC

Applications

  • Mission Critical
  • Computing
  • Communications
  • Audio
  • Video Infrastructure
  • Imaging
  • Analytics
  • Networking
  • Media Processing

Description

The 66AK2Hxx platform combines the quad ARM Cortex-A15 processor with up to eight TMS320C66x high-performance DSPs using the KeyStone II architecture. The 66AK2H14/12/06 device provides up to 5.6 GHz of ARM and 9.6 GHz of DSP processing coupled with security, packet processing, and Ethernet switching at lower power than multichip solutions. The 66AK2H14/12/06 device is optimal for embedded infrastructure applications like cloud computing, media processing, high-performance computing, transcoding, security, gaming, analytics, and virtual desktop.

The C66x core combines fixed-point and floating-point computational capability in the processor without sacrificing speed, size, or power consumption. The raw computational performance is 38.4 GMACS/core and 19.2 Gflops/core (@ 1.2 GHz operating frequency). The C66x is also 100% backward compatible with software for C64x+ devices. The C66x core incorporates 90 new instructions targeted for floating point (FPi) and vector math oriented (VPi) processing.

The 66AK2H14/12/06 device has a complete set of development tools that includes: a C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows® debugger interface for visibility into source code execution.

Enhancements in KeyStone II

The KeyStone II architecture provides many major enhancements over the previous KeyStone I generation of devices. The KeyStone II architecture integrates a Cortex-A15 processor quad-core cluster. The external memory bandwidth has been doubled with the integration of dual DDR3 1600 EMIFs. MSMC internal memory bandwidth is quadrupled with MSMC architecture improvements such as cache coherency. MSMC also enbles memories to operate at the speed of the processor cores, which reduces latency and contention while providing high-bandwidth interconnections between processor cores and shared internal and external memory. Multicore Navigator supports twice the number of queues, descriptors, and packet DMA, four times the number of micro RISC engines, and a significant increase in the number of push/pops per second compared to the previous generation. The new peripherals that have been added include the USB 3.0 controller, and asynchronous EMIF controller for NAND/NOR memory access. The 3-port Gigabit Ethernet switch in KeyStone I has been replaced with a 5-port Gigabit Ethernet switch in KeyStone II. Time synchronization support has been enhanced to reduce software workload and support additional standards like IEEE 1588 Annex D/E and SyncE. The number of GPIOs and serial interface peripherals, like I2C and SPI, have been increased to enable more board-level control functionality.

Device Information(1)

PART NUMBERPACKAGEBODY SIZE
66AK2H14AAW40.0 mm × 40.0 mm
66AK2H12AAW40.0 mm × 40.0 mm
66AK2H06AAW40.0 mm × 40.0 mm
For more information, see Section 13, Mechanical, Packaging, and Orderable Information.

Functional Block Diagram

Figure 1-1, Figure 1-2, and Figure 1-3 show the functional block diagrams of the devices.

66AK2H14 66AK2H12 66AK2H06 Functional_Block_Diagram_66AK2H14.gif Figure 1-1 Functional Block Diagram for 66AK2H14
66AK2H14 66AK2H12 66AK2H06 Functional_Block_Diagram_66AK2H12.gif Figure 1-2 Functional Block Diagram for 66AK2H12
66AK2H14 66AK2H12 66AK2H06 Functional_Block_Diagram_66AK2H06.gif Figure 1-3 Functional Block Diagram for 66AK2H06