66AK2H12 (ACTIVE)

Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

Description

The 66AK2Hxx platform combines the quad ARM Cortex-A15 processor with up to eight TMS320C66x high-performance DSPs using the KeyStone II architecture. The 66AK2H14/12/06 device provides up to 5.6 GHz of ARM and 9.6 GHz of DSP processing coupled with security, packet processing, and Ethernet switching at lower power than multichip solutions. The 66AK2H14/12/06 device is optimal for embedded infrastructure applications like cloud computing, media processing, high-performance computing, transcoding, security, gaming, analytics, and virtual desktop.

The C66x core combines fixed-point and floating-point computational capability in the processor without sacrificing speed, size, or power consumption. The raw computational performance is 38.4 GMACS/core and 19.2 Gflops/core (@ 1.2 GHz operating frequency). The C66x is also 100% backward compatible with software for C64x+ devices. The C66x core incorporates 90 new instructions targeted for floating point (FPi) and vector math oriented (VPi) processing.

The 66AK2H14/12/06 device has a complete set of development tools that includes: a C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows® debugger interface for visibility into source code execution.

Features

  • Eight TMS320C66x DSP Core Subsystems (C66x CorePacs), Each With
    • 1.0 GHz or 1.2 GHz C66x Fixed- and Floating-Point DSP Core
      • 38.4 GMacs/Core for Fixed Point @ 1.2 GHz
      • 19.2 GFlops/Core for Floating Point @ 1.2 GHz
    • Memory
      • 32-KB L1P Per CorePac
      • 32-KB L1D Per CorePac
      • 1024-KB Local L2 Per CorePac
  • ARM CorePac
    • Four ARM® Cortex®-A15 MPCore™ Processors at up to 1.4 GHz
    • 4MB of L2 Cache Memory Shared by Four ARM Cores
    • Full Implementation of ARMv7-A Architecture Instruction Set
    • 32-KB L1 Instruction and Data Caches per Core
    • AMBA 4.0 AXI Coherency Extension (ACE) Master Port, Connected to MSMC for Low-Latency Access to Shared MSMC SRAM
  • Multicore Shared Memory Controller (MSMC)
    • 6MB of MSM SRAM Memory Shared by Eight DSP CorePacs and One ARM CorePac
    • Memory Protection Unit (MPU) for Both MSM SRAM and DDR3_EMIF
  • Multicore Navigator
    • 16k Multipurpose Hardware Queues With Queue Manager
    • Packet-Based DMA for Zero-Overhead Transfers
  • Network Coprocessor
    • Packet Accelerator Enables Support for
      • Transport Plane IPsec, GTP-U, SCTP, PDCP
      • L2 User Plane PDCP (RoHC, Air Ciphering)
      • 1-Gbps Wire Speed Throughput at 1.5 MPackets Per Second
    • Security Accelerator Engine Enables Support for
      • IPSec, SRTP, 3GPP, and WiMAX Air Interface, and SSL/TLS Security
      • ECB, CBC, CTR, F8, A5/3, CCM, GCM, HMAC, CMAC, GMAC, AES, DES, 3DES, Kasumi, SNOW 3G, SHA-1, SHA-2 (256-Bit Hash), MD5
      • Up to 2.4 Gbps IPSec and 2.4 Gbps Air Ciphering
    • Ethernet Subsystem
      • Five-Port Switch (Four SGMII Ports)
  • Peripherals
    • Four Lanes of SRIO 2.1
      • Supports up to 5 GBaud
      • Supports Direct I/O, Message Passing
    • Two Lanes PCIe Gen2
      • Supports up to 5 GBaud
    • Two HyperLinks
      • Supports Connections to Other KeyStone™ Architecture Devices Providing Resource Scalability
      • Supports up to 50 GBaud
    • 10-Gigabit Ethernet (10-GbE) Switch Subsystem (66AK2H14 Only)
      • Two XFI Ports
      • IEEE 1588 Support
    • Five Enhanced Direct Memory Access (EDMA) Modules
    • Two 72-Bit DDR3/DDR3L Interfaces With Speeds up to 1600 MHz
    • EMIF16 Interface
    • USB 3.0
    • Two UART Interfaces
    • Three I2C Interfaces
    • 32 GPIO Pins
    • Three SPI Interfaces
    • Semaphore Module
    • 64-Bit Timers
      • Twenty 64-Bit Timers for 66AK2H14 and 66AK2H12
      • Fourteen 64-Bit Timers for 66AK2H06
    • Five On-Chip PLLs
  • Commercial Case Temperature:
    • 0ºC to 85ºC
  • Extended Case Temperature:
    • –40ºC to 100ºC

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Parametrics Compare all products in C6000 DSP + Arm

 
Approx. Price (US$)
Applications
Operating Systems
Arm MHz (Max.)
Arm CPU
DSP
On-Chip L2 Cache/RAM
Other On-Chip Memory
EMAC
DRAM
PCI/PCIe
USB
SPI
I2C
UART (SCI)
Operating Temperature Range (C)
Rating
66AK2H12 66AK2H06 66AK2H14
427.45 | 1ku     321.88 | 1ku     661.26 | 1ku    
Automation and Process,Avionics & Defense, Communications and Telecom, Consumer Electronics, Industrial, Medical, Security, Space     Automation and Process,Avionics & Defense, Communications and Telecom, Consumer Electronics, Industrial, Medical, Security, Space     Automation and Process,Avionics & Defense, Communications and Telecom, Consumer Electronics, Industrial, Medical, Security, Space    
Integrity
Linux
SYS/BIOS
VxWorks    
Integrity
Linux
SYS/BIOS
VxWorks    
Integrity
Linux
SYS/BIOS
VxWorks    
1200
1400    
1200
1400    
1200
1400    
4 ARM Cortex-A15     2 ARM Cortex-A15     4 ARM Cortex-A15    
8 C66x     4 C66x     8 C66x    
4096 KB (ARM Cluster)
1024 KB (per C66x DSP core)    
4096 KB (ARM Cluster)
1024 KB (per C66x DSP core)    
4096 KB (ARM Cluster)
1024 KB (per C66x DSP core)    
6144 KB     6144 KB     6144 KB    
4-port 1Gb Switch     4-port 1Gb Switch     10G Ethernet    
DDR3
DDR3L    
DDR3
DDR3L    
DDR3
DDR3L    
2 PCIe Gen2     2 PCIe Gen2     2 PCIe Gen2    
1     1     1    
3     3     3    
3     3     3    
2     2     2    
-40 to 100
0 to 85    
-40 to 100
0 to 85    
-40 to 100
0 to 85    
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