This device contains two independent positive-edge-triggered D-type flip-flops. A low level at the preset () or clear () input sets or resets the outputs regardless of the levels of the other inputs. When and are inactive (high), data at the data (D) input that meets the setup-time requirements are transferred to the outputs on the low-to-high transition of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input may be changed without affecting the levels at the outputs.
The 74AC11074 is characterized for operation from -40°C to 85°C.
EPIC is a trademark of Texas Instruments Incorporated.
|Part number||Order||Technology Family||Input type||Output type||VCC (Min) (V)||VCC (Max) (V)||Channels (#)||Clock Frequency (Max) (MHz)||ICC (uA)||IOL (Max) (mA)||IOH (Max) (mA)||Features||Rating||Package Group|
High speed (tpd 10-50ns)
Positive input clamp diode
PDIP | 14
SOIC | 14
TSSOP | 14