ADC08D500 8-Bit, Dual 500-MSPS or Single 1.0-GSPS Analog-to-Digital Converter (ADC) | TI.com

ADC08D500 (ACTIVE)

8-Bit, Dual 500-MSPS or Single 1.0-GSPS Analog-to-Digital Converter (ADC)

 

Description

The ADC08D500 is a dual, low power, high performance CMOS analog-to-digital converter that digitizes signals to 8 bits resolution at sampling rates up to 500 MSPS. Consuming a typical 1.4 Watts at 500 MSPS from a single 1.9 Volt supply, this device is ensured to have no missing codes over the full operating temperature range. The unique folding and interpolating architecture, the fully differential comparator design, the innovative design of the internal sample-and-hold amplifier and the self-calibration scheme enable a very flat response of all dynamic parameters beyond Nyquist, producing a high 7.5 ENOB with a 250 MHz input signal and a 500 MHz sample rate while providing a 10-18 B.E.R. Output formatting is offset binary and the LVDS digital outputs are compatible with IEEE 1596.3-1996, with the exception of an adjustable common mode voltage between 0.8V and 1.2V.

Each converter has a 1:2 demultiplexer that feeds two LVDS buses and reduces the output data rate on each bus to half the sampling rate. The two converters can be interleaved and used as a single 1 GSPS ADC.

The converter typically consumes less than 3.5 mW in the Power Down Mode and is available in a 128-lead, thermally enhanced exposed pad HLQFP and operates over the Industrial (-40°C ≤ TA ≤ +85°C) temperature range.

Features

  • Internal Sample-and-Hold
  • Single +1.9V ±0.1V Operation
  • Choice of SDR or DDR Output Clocking
  • Interleave Mode for 2x Sampling Rate
  • Multiple ADC Synchronization Capability
  • Ensured No Missing Codes
  • Serial Interface for Extended Control
  • Fine Adjustment of Input Full-Scale Range and Offset
  • Duty Cycle Corrected Sample Clock

Key Specifications

  • Resolution 8 Bits
  • Max Conversion Rate 500 MSPS (min)
  • Bit Error Rate 10-18 (typ)
  • ENOB @ 250 MHz Input 7.5 Bits (typ)
  • DNL ±0.15 LSB (typ)
  • Power Consumption
    • Operating 1.4 W (typ)
    • Power Down Mode 3.5 mW (typ)

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Parametrics

Compare all products in High-speed ADCs (>10MSPS) Email Download to Excel
Part number Order Sample rate (Max) (MSPS) Features Resolution (Bits) Number of input channels SNR (dB) ENOB (Bits) SFDR (dB) Power consumption (Typ) (mW) Input range (Vp-p) Interface Operating temperature range (C) Analog input BW (MHz) Input buffer Package Group Package size: mm2:W x L (PKG) Rating Architecture
ADC08D500 Order now 500
1000    
Low Power     8     2
1    
48     7.5     55     1400     0.87     Parallel LVDS     -40 to 85     1700     Yes     HLQFP | 128     128HLQFP: 484 mm2: 22 x 22 (HLQFP | 128)     Catalog     Folding Interpolating    
ADC081500 Order now 1500     Ultra High Speed     8     1     47     7.4     56     1200     0.87     Parallel LVDS     -40 to 85     1700     Yes     HLQFP | 128     128HLQFP: 484 mm2: 22 x 22 (HLQFP | 128)     Catalog     Folding Interpolating    
ADC083000 Order now 3000     Ultra High Speed     8     1     45.3     7.2     57     1900     0.82     Parallel LVDS     -40 to 85     3000     Yes     HLQFP | 128     128HLQFP: 484 mm2: 22 x 22 (HLQFP | 128)     Catalog     Folding Interpolating    
ADC08500 Order now 500     Low Power     8     1     47.5     7.5     56     800     0.87     Parallel LVDS     -40 to 85     1700     Yes     HLQFP | 128     128HLQFP: 484 mm2: 22 x 22 (HLQFP | 128)     Catalog     Folding Interpolating    
ADC08B3000 Order now 3000     Ultra High Speed     8     1     45.3     7.2     55.4     1600     0.81     Parallel CMOS     -40 to 85     3000     Yes