8-Bit, Dual 500-MSPS or Single 1.0-GSPS Analog-to-Digital Converter (ADC) - ADC08D500

ADC08D500 (ACTIVE)

8-Bit, Dual 500-MSPS or Single 1.0-GSPS Analog-to-Digital Converter (ADC)

 

Description

The ADC08D500 is a dual, low power, high performance CMOS analog-to-digital converter that digitizes signals to 8 bits resolution at sampling rates up to 500 MSPS. Consuming a typical 1.4 Watts at 500 MSPS from a single 1.9 Volt supply, this device is ensured to have no missing codes over the full operating temperature range. The unique folding and interpolating architecture, the fully differential comparator design, the innovative design of the internal sample-and-hold amplifier and the self-calibration scheme enable a very flat response of all dynamic parameters beyond Nyquist, producing a high 7.5 ENOB with a 250 MHz input signal and a 500 MHz sample rate while providing a 10-18 B.E.R. Output formatting is offset binary and the LVDS digital outputs are compatible with IEEE 1596.3-1996, with the exception of an adjustable common mode voltage between 0.8V and 1.2V.

Each converter has a 1:2 demultiplexer that feeds two LVDS buses and reduces the output data rate on each bus to half the sampling rate. The two converters can be interleaved and used as a single 1 GSPS ADC.

The converter typically consumes less than 3.5 mW in the Power Down Mode and is available in a 128-lead, thermally enhanced exposed pad HLQFP and operates over the Industrial (-40°C ≤ TA ≤ +85°C) temperature range.

Features

  • Internal Sample-and-Hold
  • Single +1.9V ±0.1V Operation
  • Choice of SDR or DDR Output Clocking
  • Interleave Mode for 2x Sampling Rate
  • Multiple ADC Synchronization Capability
  • Ensured No Missing Codes
  • Serial Interface for Extended Control
  • Fine Adjustment of Input Full-Scale Range and Offset
  • Duty Cycle Corrected Sample Clock

Key Specifications

  • Resolution 8 Bits
  • Max Conversion Rate 500 MSPS (min)
  • Bit Error Rate 10-18 (typ)
  • ENOB @ 250 MHz Input 7.5 Bits (typ)
  • DNL ±0.15 LSB (typ)
  • Power Consumption
    • Operating 1.4 W (typ)
    • Power Down Mode 3.5 mW (typ)

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Parametrics Compare all products in High Speed ADCs (>10MSPS)

 
Resolution (Bits)
Sample Rate (Max) (MSPS)
# Input Channels
SNR (dB)
ENOB (Bits)
SFDR (dB)
Power Consumption (Typ) (mW)
Input Range (Vp-p)
Interface
Operating Temperature Range (C)
Analog Input BW (MHz)
Input Buffer
Package Group
Package Size: mm2:W x L (PKG)
Rating
SINAD (dB)
Architecture
DNL (Typ) (+/-LSB)
INL (Typ) (+/-LSB)
Reference Mode
ADC08D500 ADC081500 ADC083000 ADC08500 ADC08B3000 ADC08D1020 ADC08D1520 ADC08D502 ADC08DL502
8    8    8    8    8    8    8    8    8   
500
1000   
1500    3000    500    3000    1000
2000   
1500
3000   
500    500   
2
1   
1    1    1    1    2
1   
2
1   
2    2   
48    47    45.3    47.5    45.3    46.8    46.8    48    48.5   
7.5    7.4    7.2    7.5    7.2    7.4    7.4    7.5    7.6   
55    56    57    56    55.4    58    58    55    59.1   
1400    1200    1900    800    1600    1600    2000    1400    1250   
0.87    0.87    0.82    0.87    0.81    0.87    0.87    0.87    0.84   
Parallel LVDS    Parallel LVDS    Parallel LVDS    Parallel LVDS    Parallel CMOS    Parallel LVDS    Parallel LVDS    Parallel LVDS    Parallel LVDS   
-40 to 85    -40 to 85    -40 to 85    -40 to 85    -40 to 85    -40 to 85    -40 to 85    -40 to 85    -40 to 70   
1700    1700    3000    1700    3000    2000    2000    1700    2000   
Yes    Yes    Yes    Yes    Yes    Yes    Yes    No    Yes   
HLQFP    HLQFP    HLQFP    HLQFP    HLQFP    HLQFP    HLQFP    HLQFP    LQFP   
128HLQFP: 484 mm2: 22 x 22(HLQFP)    128HLQFP: 484 mm2: 22 x 22(HLQFP)    128HLQFP: 484 mm2: 22 x 22(HLQFP)    128HLQFP: 484 mm2: 22 x 22(HLQFP)    128HLQFP: 484 mm2: 22 x 22(HLQFP)    128HLQFP: 484 mm2: 22 x 22(HLQFP)    128HLQFP: 484 mm2: 22 x 22(HLQFP)    128HLQFP: 484 mm2: 22 x 22(HLQFP)    144LQFP: 484 mm2: 22 x 22(LQFP)   
Catalog    Catalog    Catalog    Catalog    Catalog    Catalog    Catalog    Catalog    Catalog   
47    46.3    45    47    44.5    46.5    46.5    47    47.6   
Folding Interpolating    Folding Interpolating    Folding Interpolating    Folding Interpolating    Folding Interpolating    Folding Interpolating    Folding Interpolating    Folding Interpolating    Folding Interpolating   
0.15    0.15    0.2    0.15    0.2    0.15    0.15    0.15    0.15   
0.3    0.3    0.35    0.3    0.35    0.3    0.3    0.3    0.3   
Int    Int    Int    Int    Int    Int    Int    Int    Int   

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