ADC08L060 8-Bit, 60-MSPS, Ultra-Low Power Analog-to-Digital Converter (ADC) | TI.com

ADC08L060
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8-Bit, 60-MSPS, Ultra-Low Power Analog-to-Digital Converter (ADC)

 

Description

The ADC08L060 is a low-power, 8-bit, monolithic analog-to-digital converter with an on-chip track-and-hold circuit. Optimized for low cost, low power, small size and ease of use, this product operates at conversion rates of 10 MSPS to 60 MSPS while consuming just 0.65 mW per MHz of clock frequency, or 39 mW at 60 MSPS. Raising the PD pin puts the ADC08L060 into a Power Down mode where it consumes about 1 mW.

The unique architecture achieves 7.6 Effective Bits. The ADC08L060 is resistant to latch-up and the outputs are short-circuit proof. The top and bottom of the ADC08L060s reference ladder are available for connections, enabling a wide range of input possibilities. The digital outputs are TTL/CMOS compatible with a separate output power supply pin to support interfacing with 1.8V to 3V logic. The output coding is straight binary and the digital inputs (CLK and PD) are TTL/CMOS compatible.

The ADC08L060 is offered in a 24-lead plastic package (TSSOP) and is specified over the industrial temperature range of −40°C to +85°C.

Features

  • Single-ended input
  • Internal sample-and-hold function
  • Low voltage (single +3V) operation
  • Small package
  • Power-down feature

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Key Specifications

  • Resolution 8 bits
  • Conversion rate 60 MSPS
  • DNL ±0.25 LSB (typ)
  • INL +0.5/−0.2 LSB (typ)
  • SNR (10.1 MHz) 48 dB (typ)
  • ENOB (10.1 MHz) 7.6 bits (typ)
  • THD (10.1 MHz) −57 dB (typ)
  • Latency 5 Clock Cycles
  • No missing codes Ensured
  • Power Consumption
    • Operating 0.65 mW/MSPS (typ)
    • Power Down Mode 1.0 mW (typ)

Parametrics

Compare all products in High-speed ADCs (>10MSPS) Email Download to Excel
Part number Order Sample rate (Max) (MSPS) Features Resolution (Bits) Number of input channels SNR (dB) ENOB (Bits) SFDR (dB) Power consumption (Typ) (mW) Input range (Vp-p) Interface Operating temperature range (C) Analog input BW (MHz) Input buffer Package Group Package size: mm2:W x L (PKG) Rating Architecture
ADC08L060 Order now 60     Low Power     8     1     48     7.6     59.1     53     1.6     Parallel CMOS
TTL    
-40 to 85     270     No     TSSOP | 24     24TSSOP: 34 mm2: 4.4 x 7.8 (TSSOP | 24)     Catalog     Pipeline    
ADC08060 Order now 60     Low Power     8     1     47     7.6     64     88     1.6     Parallel CMOS
TTL    
-40 to 85     200     No     TSSOP | 24     24TSSOP: 34 mm2: 4.4 x 7.8 (TSSOP | 24)     Catalog     Pipeline    
ADC08100 Order now 100     Low Power     8     1     47     7.5     63     126     1.6     Parallel CMOS
TTL    
-40 to 85     200     No     TSSOP | 24     24TSSOP: 34 mm2: 4.4 x 7.8 (TSSOP | 24)     Catalog     Pipeline    
ADC08200 Order now 200     Low Power     8     1     47     7.5     60     210     1.6     Parallel CMOS
TTL    
-40 to 85     500     No     TSSOP | 24     24TSSOP: 34 mm2: 4.4 x 7.8 (TSSOP | 24)     Catalog     Pipeline