ADC10040 10-Bit, 40-MSPS Analog-to-Digital Converter (ADC) | TI.com

ADC10040 (ACTIVE) 10-Bit, 40-MSPS Analog-to-Digital Converter (ADC)

 

Description

The ADC10040 is a monolithic CMOS analog-to-digital converter capable of converting analog input signals into 10-bit digital words at 40 Megasamples per second (MSPS). This converter uses a differential, pipeline architecture with digital error correction and an on-chip sample-and-hold circuit to provide a complete conversion solution, and to minimize power consumption, while providing excellent dynamic performance. A unique sample-and-hold stage yields a full-power bandwidth of 400 MHz. Operating on a single 3.0V power supply, this device consumes just 55.5 mW at 40 MSPS, including the reference current. The Standby feature reduces power consumption to just 13.5 mW.

The differential inputs provide a full scale selectable input swing of 2.0 VP-P, 1.5 VP-P, 1.0 VP-P, with the possibility of a single-ended input. Full use of the differential input is recommended for optimum performance. An internal +1.2V precision bandgap reference is used to set the ADC full-scale range, and also allows the user to supply a buffered referenced voltage for those applications requiring increased accuracy. The output data format is user choice of offset binary or two’s complement.

The ADC10040Q runs on an Automotive Grade Flow and is AEC-Q100 Grade 3 Qualified.

This device is available in the 28-lead TSSOP package and will operate over the industrial temperature range of −40°C to +85°C.

Features

  • Single +3.0V Operation
  • Selectable 2.0 VP-P, 1.5 VP-P, or 1.0 VP-P full-scale input swing
  • 400 MHz −3 dB Input Bandwidth
  • Low Power Consumption
  • Standby Mode
  • On-Chip Reference and Sample-and-Hold Amplifier
  • Offset Binary or Two’s Complement Data Format
  • Separate Adjustable Output Driver Supply to Accommodate 2.5V and 3.3V Logic Families
  • AEC-Q100 Grade 3 Qualified
  • 28-Pin TSSOP Package

Key Specifications

  • Resolution: 10 Bits
  • Conversion Rate: 40 MSPS
  • Full Power Bandwidth: 400 MHz
  • DNL: ±0.3 LSB typ)
  • SNR (fIN = 11 MHz): 59.6 dB (typ)
  • SFDR (fIN = 11 MHz): -80 dB (typ)
  • Power Consumption, 40 MHz: 55.5 mW

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Parametrics

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Part number Order Sample rate (Max) (MSPS) Features Resolution (Bits) Number of input channels SNR (dB) ENOB (Bits) SFDR (dB) Power consumption (Typ) (mW) Input range (Vp-p) Interface Operating temperature range (C) Analog input BW (MHz) Input buffer Package Group Package size: mm2:W x L (PKG) Rating Architecture
ADC10040 Order now 40     Low Power     10     1     59.6     9.6     80     55.5     2     Parallel CMOS
TTL    
-40 to 85     400     No     TSSOP | 28     28TSSOP: 62 mm2: 6.4 x 9.7 (TSSOP | 28)     Catalog     Pipeline    
ADC10040-Q1 Order now 40     Low Power     10     1     58.7     9.6     80     55.5     2     Parallel CMOS
TTL    
-40 to 85     400     No     TSSOP | 28     28TSSOP: 62 mm2: 6.4 x 9.7 (TSSOP | 28)     Automotive     Pipeline    
ADC10065 Order now 65     Low Power     10     1     59.6     9.6     80     68.4     2     Parallel CMOS
TTL    
-40 to 85     400     No     TSSOP | 28     28TSSOP: 62 mm2: 6.4 x 9.7 (TSSOP | 28)     Catalog     Pipeline    
ADC10080 Order now 80     Low Power     10     1     59.5     9.5     78.8     78.6     2     Parallel CMOS
TTL    
-40 to 85     400     No     TSSOP | 28     28TSSOP: 62 mm2: 6.4 x 9.7 (TSSOP | 28)     Catalog     Pipeline