SNAS298G August   2005  – January 2015 ADC128S102

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Specifications
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 ADC128S102 Operation
      2. 7.3.2 ADC128S102 Transfer Function
      3. 7.3.3 Analog Inputs
      4. 7.3.4 Digital Inputs and Outputs
    4. 7.4 Device Functional Modes
    5. 7.5 Programming
      1. 7.5.1 Serial Interface
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
    1. 9.1 Power Supply Sequence
    2. 9.2 Power Supply Noise Considerations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Specification Definitions
    2. 11.2 Trademarks
    3. 11.3 Electrostatic Discharge Caution
    4. 11.4 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

PW Package
16-Pin TSSOP
Top View
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Pin Functions

PIN I/O DESCRIPTION
NO. NAME
3 AGND Supply The ground return for the analog supply and signals.
1 CS IN Chip select. On the falling edge of CS, a conversion process begins. Conversions continue as long as CS is held low.
12 DGND Supply The ground return for the digital supply and signals.
14 DIN IN Digital data input. The ADC128S102's Control Register is loaded through this pin on rising edges of the SCLK pin.
15 DOUT OUT Digital data output. The output samples are clocked out of this pin on the falling edges of the SCLK pin.
4 - 11 IN0 to IN7 IN Analog inputs. These signals can range from 0 V to VREF.
16 SCLK IN Digital clock input. The ensured performance range of frequencies for this input is 8 MHz to 16 MHz. This clock directly controls the conversion and readout processes.
2 VA Supply Positive analog supply pin. This voltage is also used as the reference voltage. This pin should be connected to a quiet +2.7-V to +5.25-V source and bypassed to GND with 1-µF and 0.1-µF monolithic ceramic capacitors located within 1 cm of the power pin.
13 VD Supply Positive digital supply pin. This pin should be connected to a +2.7 V to VA supply, and bypassed to GND with a 0.1-µF monolithic ceramic capacitor located within 1 cm of the power pin.