ADC12D1800 12-bit, dual 1.8GSPS or single 3.6GSPS analog-to-digital converter (ADC) | TI.com

ADC12D1800 (ACTIVE) 12-bit, dual 1.8GSPS or single 3.6GSPS analog-to-digital converter (ADC)

 

Description

The 12-bit, 3.6 GSPS ADC12D1800 is the latest advance in TI’s Ultra-High-Speed ADC family and builds upon the features, architecture and functionality of the 10-bit GHz family of ADCs.

The ADC12D1800 provides a flexible LVDS interface which has multiple SPI programmable options to facilitate board design and FPGA/ASIC data capture. The LVDS outputs are compatible with IEEE 1596.3-1996 and supports programmable common mode voltage.

The product is packaged in a leaded or lead-free 292-ball thermally enhanced BGA package over the rated industrial temperature range of –40°C to +85°C.

To achieve full rated performance for fCLK > 1.6 GHz, write the maximum power settings one time to Register 6h through the serial interface; see Section 5.6.1 for more information.

Features

  • Configurable to Either 3.6 GSPS Interleaved or 1.8 GSPS Dual ADC
  • Pin-Compatible with ADC10D1000/1500 and ADC12D1000/1600
  • Internally Terminated, Buffered, Differential Analog Inputs
  • Interleaved Timing Automatic and Manual Skew Adjust
  • Test Patterns at Output for System Debug
  • Programmable 15-bit Gain and 12-bit Plus Sign Offset
  • Programmable tAD Adjust Feature
  • 1:1 Non-Demuxed or 1:2 Demuxed LVDS Outputs
  • AutoSync Feature for Multi-Chip Systems
  • Single 1.9-V ± 0.1-V Power Supply
  • Key Specifications
    • Resolution: 12 Bits
    • Interleaved 3.6 GSPS ADC
      • Noise Floor Density –153.5 dBm/Hz (typ)
      • IMD3 –61 dBFS (typ)
      • Noise Power Ratio 48.5 dB (typ)
      • Power 4.4 W (typ)
      • Full Power Bandwidth 1.75 GHz (typ)
    • Dual 1.8 GSPS ADC, Fin = 125MHz
      • ENOB: 9.4 (typ)
      • SNR 58.5 dB (typ)
      • SFDR 73 dBc (typ)
      • Power 4.4 W (typ)
      • Full Power Bandwidth 2.8 GHz (typ)

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Parametrics

Compare all products in High-speed ADCs (>10MSPS) Email Download to Excel
Part number Order Sample rate (Max) (MSPS) Features Resolution (Bits) Number of input channels SNR (dB) ENOB (Bits) SFDR (dB) Power consumption (Typ) (mW) Input range (Vp-p) Interface Operating temperature range (C) Analog input BW (MHz) Input buffer Package Group Package size: mm2:W x L (PKG) Rating Architecture
ADC12D1800 Order now 1800
3600    
Ultra High Speed     12     2
1    
58.6     9.4     73     4180     0.8     Parallel LVDS     -40 to 85     2800     Yes     BGA | 292     292BGA: 729 mm2: 27 x 27 (BGA | 292)     Catalog     Folding Interpolating    
ADC12D1000 Samples not available 1000
2000    
Ultra High Speed     12     2
1    
59.2     9.6     71     3380     0.8     Parallel LVDS     -40 to 85     2800     Yes     BGA | 292     292BGA: 729 mm2: 27 x 27 (BGA | 292)     Catalog     Folding Interpolating    
ADC12D1000RF Samples not available 1000
2000    
Ultra High Speed     12     2
1    
60.1     9.6     75     3510     0.8     Parallel LVDS     -40 to 85     2700     Yes     BGA | 292     292BGA: 729 mm2: 27 x 27 (BGA | 292)     Catalog     Folding Interpolating    
ADC12D1600 Samples not available 1600
3200    
Ultra High Speed     12     2
1    
60.2     9.6     71     3880     0.8     Parallel LVDS     -40 to 85     2800     Yes     BGA | 292     292BGA: 729 mm2: 27 x 27 (BGA | 292)     Catalog     Folding Interpolating    
ADC12D1600RF Samples not available 1600
3200    
Ultra High Speed     12     2
1    
60.1     9.6     75     3880     0.8     Parallel LVDS     -40 to 85     2700