Product details

Sample rate (max) (Msps) 3200, 6400 Resolution (Bits) 12 Number of input channels 1, 2 Interface type DDR LVDS, Parallel LVDS Analog input BW (MHz) 8000 Features Ultra High Speed Rating Catalog Peak-to-peak input voltage range (V) 0.8 Power consumption (typ) (mW) 3150 Architecture Folding Interpolating SNR (dB) 57.9 ENOB (bit) 9 SFDR (dB) 78 Operating temperature range (°C) -40 to 85 Input buffer Yes
Sample rate (max) (Msps) 3200, 6400 Resolution (Bits) 12 Number of input channels 1, 2 Interface type DDR LVDS, Parallel LVDS Analog input BW (MHz) 8000 Features Ultra High Speed Rating Catalog Peak-to-peak input voltage range (V) 0.8 Power consumption (typ) (mW) 3150 Architecture Folding Interpolating SNR (dB) 57.9 ENOB (bit) 9 SFDR (dB) 78 Operating temperature range (°C) -40 to 85 Input buffer Yes
FCBGA (ACF) 256 289 mm² 17 x 17 FCBGA (ALJ) 256 289 mm² 17 x 17
  • ADC Core:
    • 12-Bit Resolution
    • Up to 6.4 GSPS in Single-Channel Mode
    • Up to 3.2 GSPS in Dual-Channel Mode
  • Internal Dither for Low-Magnitude, High-Order Harmonics
  • Low-Latency LVDS Interface:
    • Total Latency: < 10 ns
    • Up to 48 Data Pairs at 1.6 Gbps
    • Four DDR Data Clocks
    • Strobe Signals Simplify Synchronization
  • Noise Floor (No Input, V FS = 1.0 V PP-DIFF):
    • Dual-Channel Mode: –151.1 dBFS/Hz
    • Single-Channel Mode: –154.3 dBFS/Hz
  • Buffered Analog Inputs With V CMI of 0 V:
    • Analog Input Bandwidth (–3 dB): 8.0 GHz
    • Usable Input Frequency Range: > 10 GHz
    • Full-Scale Input Voltage (V FS, Default): 0.8 V PP
  • Noiseless Aperture Delay (T AD) Adjustment:
    • Precise Sampling Control: 19-fs Step
    • Simplifies Synchronization and Interleaving
    • Temperature and Voltage Invariant Delays
  • Easy-to-Use Synchronization Features:
    • Automatic SYSREF Timing Calibration
    • Timestamp for Sample Marking
  • Power Consumption: 3.15 W
  • ADC Core:
    • 12-Bit Resolution
    • Up to 6.4 GSPS in Single-Channel Mode
    • Up to 3.2 GSPS in Dual-Channel Mode
  • Internal Dither for Low-Magnitude, High-Order Harmonics
  • Low-Latency LVDS Interface:
    • Total Latency: < 10 ns
    • Up to 48 Data Pairs at 1.6 Gbps
    • Four DDR Data Clocks
    • Strobe Signals Simplify Synchronization
  • Noise Floor (No Input, V FS = 1.0 V PP-DIFF):
    • Dual-Channel Mode: –151.1 dBFS/Hz
    • Single-Channel Mode: –154.3 dBFS/Hz
  • Buffered Analog Inputs With V CMI of 0 V:
    • Analog Input Bandwidth (–3 dB): 8.0 GHz
    • Usable Input Frequency Range: > 10 GHz
    • Full-Scale Input Voltage (V FS, Default): 0.8 V PP
  • Noiseless Aperture Delay (T AD) Adjustment:
    • Precise Sampling Control: 19-fs Step
    • Simplifies Synchronization and Interleaving
    • Temperature and Voltage Invariant Delays
  • Easy-to-Use Synchronization Features:
    • Automatic SYSREF Timing Calibration
    • Timestamp for Sample Marking
  • Power Consumption: 3.15 W

The ADC12DL3200 is an RF-sampling, giga-sample, analog-to-digital converter (ADC) that can directly sample input frequencies from DC to above 10 GHz. In dual-channel mode, the ADC12DL3200 can sample up to 3200 MSPS and in single-channel mode up to 6400 MSPS. Programmable tradeoffs in channel count (dual-channel mode) and Nyquist bandwidth (single-channel mode) allow development of flexible hardware that meets the needs of both high-channel count or wide instantaneous signal bandwidth applications. Full-power input bandwidth (–3 dB) of 8.0 GHz and a useable frequency range allows direct RF sampling of L-band, S-band, C-band, and X-band for frequency agile systems.

The ADC12DL3200 uses a low-latency, low-voltage differential signaling (LVDS) interface for latency sensitive applications or when the simplicity of LVDS is preferred. The interface uses up to 48 data pairs, four double data rate (DDR) clocks, and four strobe signals arranged in four 12-bit data buses. The interface supports signaling rates of up to 1.6 Gbps. Strobe signals simplify synchronization across buses and between multiple devices. The strobe is generated internally and can be reset at a deterministic time by the SYSREF input. Multi-device synchronization is further eased by innovative synchronization features such as noiseless aperture delay (T AD) adjustment and SYSREF windowing.

The ADC12DL3200 is an RF-sampling, giga-sample, analog-to-digital converter (ADC) that can directly sample input frequencies from DC to above 10 GHz. In dual-channel mode, the ADC12DL3200 can sample up to 3200 MSPS and in single-channel mode up to 6400 MSPS. Programmable tradeoffs in channel count (dual-channel mode) and Nyquist bandwidth (single-channel mode) allow development of flexible hardware that meets the needs of both high-channel count or wide instantaneous signal bandwidth applications. Full-power input bandwidth (–3 dB) of 8.0 GHz and a useable frequency range allows direct RF sampling of L-band, S-band, C-band, and X-band for frequency agile systems.

The ADC12DL3200 uses a low-latency, low-voltage differential signaling (LVDS) interface for latency sensitive applications or when the simplicity of LVDS is preferred. The interface uses up to 48 data pairs, four double data rate (DDR) clocks, and four strobe signals arranged in four 12-bit data buses. The interface supports signaling rates of up to 1.6 Gbps. Strobe signals simplify synchronization across buses and between multiple devices. The strobe is generated internally and can be reset at a deterministic time by the SYSREF input. Multi-device synchronization is further eased by innovative synchronization features such as noiseless aperture delay (T AD) adjustment and SYSREF windowing.

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* Data sheet ADC12DL3200 6.4-GSPS Single-Channel or 3.2-GSPS Dual-Channel, 12-Bit Analog-to-Digital Converter (ADC) With LVDS Interface datasheet (Rev. C) PDF | HTML 23 May 2023
EVM User's guide ADC12DLXX00 Evaluation Module User's Guide (Rev. A) PDF | HTML 07 Dec 2023
EVM User's guide TSW14DL3200EVM High-Speed LVDS Data Capture and Pattern Generator User's Guide 15 May 2018

Design & development

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Evaluation board

ADC12DL3200EVM — ADC12DL3200 12-bit, dual 3.2-GSPS or single 6.4-GSPS, RF-sampling ADC evaluation module

The ADC12DL3200 evaluation module (EVM) is used to evaluate the ADC12DL3200, which is a 12-bit, dual 3.2-GSPS or single 6.4-GSPS, RF-sampling analog-to-digital converter (ADC) with an LVDS interface. The EVM has single-ended AC-coupled analog inputs, onboard ADC clock generation, and (...)

User guide: PDF | HTML
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Firmware

SLVC814 TSW14DL3200 ADC12DL3200 Reference Design Firmware

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Supported products & hardware

Supported products & hardware

Products
High-speed ADCs (≥10 MSPS)
ADC12DL3200 12-bit, dual 3.2-GSPS or single 6.4-GSPS, RF-sampling analog-to-digital converter (LVDS interface)
Hardware development
Evaluation board
TSW14DL3200EVM Data capture/pattern generator: data converter evaluation module with 48 LVDS lanes up to 1.6Gbps
GUI for evaluation module (EVM)

SLVC719 ADC12DLxx00EVM GUI

lock = Requires export approval (1 minute)
Supported products & hardware

Supported products & hardware

Products
High-speed ADCs (≥10 MSPS)
ADC12DL3200 12-bit, dual 3.2-GSPS or single 6.4-GSPS, RF-sampling analog-to-digital converter (LVDS interface)
Hardware development
Evaluation board
ADC12DL3200EVM ADC12DL3200 12-bit, dual 3.2-GSPS or single 6.4-GSPS, RF-sampling ADC evaluation module
Plug-in

ABACO-3P-FMC172 — Abaco Systems® wideband low-latency high-speed ADC/DAC module mezzanine card

The Abaco FMC172 module highlights the Texas Instruments low-latency ADC12DL3200 one-channel 6.4-GSPS analog-to-digital converter (ADC) in a daughtercard with an FPGA mezzanine card (FMC) connector. The combination of FMC172 >6-GHz bandwidth, high sample rate, and low latency is ideal (...)
Simulation model

ADC12DL3200 IBIS Model

SLVMCP2.ZIP (53 KB) - IBIS Model
Simulation model

ADC12DL3200 IBIS Model (Rev. A)

SLVMCP2A.ZIP (68 KB) - IBIS Model
Gerber file

ADC12DL3200EVM Design File

SLVC726.ZIP (12398 KB)
Simulation tool

PSPICE-FOR-TI — PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
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