The ADC14155 is a high-performance CMOS analog-to-digital converter capable of converting analog input signals into 14-bit digital words at rates up to 155 Mega Samples Per Second (MSPS). This converter uses a differential, pipelined architecture with digital error correction and an on-chip sample-and-hold circuit to minimize power consumption and the external component count, while providing excellent dynamic performance. A unique sample-and-hold stage yields a full-power bandwidth of 1.1 GHz. The ADC14155 operates from dual +3.3V and +1.8V power supplies and consumes 967 mW of power at 155 MSPS.
The separate +1.8V supply for the digital output interface allows lower power operation with reduced noise. A power-down feature reduces the power consumption to 5 mW with the clock input disabled, while still allowing fast wake-up time to full operation.
The differential inputs provide a full scale differential input swing equal to 2 times the reference voltage. A stable 1.0V internal voltage reference is provided, or the ADC14155 can be operated with an external reference.
The Clock mode (differential versus single-ended) and output data format (offset binary versus 2's complement) are pin-selectable. A duty cycle stabilizer maintains performance over a wide range of clock duty cycles.
The ADC14155 is available in a 48-lead thermally ehanced mult-layer ceramic quad package and operates over the military temperature range of -55°C to +125°C.
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|Sample Rate (max) (SPS)|
|# Input Channels|
|INL (Max) (+/-LSB)|
|Power Consumption (Typ) (mW)|
|Analog Voltage AVDD (Min) (V)|
|Analog Voltage AVDD (Max) (V)|
|Digital Supply (Min) (V)|
|Digital Supply (Max) (V)|
|Operating Temperature Range (C)|
|Package Size: mm2:W x L (PKG)|
|1|| 2 |
|Parallel CMOS||Parallel LVDS|
| -55 to 125 |
| -55 to 125 |
|See datasheet (CFP)||See datasheet (CFP)|
| Int |
|Order Now||Order Now|