ADC14155QML-SP 14-Bit, 155-MSPS, 1.1-GHz Input Bandwidth Analog-to-Digital Converter (ADC) | TI.com

ADC14155QML-SP (ACTIVE)

14-Bit, 155-MSPS, 1.1-GHz Input Bandwidth Analog-to-Digital Converter (ADC)

14-Bit, 155-MSPS, 1.1-GHz Input Bandwidth Analog-to-Digital Converter (ADC) - ADC14155QML-SP
 

Recommended alternative parts

  • ADC08D1520QML-SP  -  Space Qualified 8-bit Single Channel 3 GSPS Or Dual Channel 1.5 GSPS ADC
  • ADC10D1000QML-SP  -  Space Qualified 10-bit Single Channel 2 GSPS Or Dual Channel 1 GSPS ADC

Description

The ADC14155 is a high-performance CMOS analog-to-digital converter capable of converting analog input signals into 14-bit digital words at rates up to 155 Mega Samples Per Second (MSPS). This converter uses a differential, pipelined architecture with digital error correction and an on-chip sample-and-hold circuit to minimize power consumption and the external component count, while providing excellent dynamic performance. A unique sample-and-hold stage yields a full-power bandwidth of 1.1 GHz. The ADC14155 operates from dual 3.3-V and 1.8-V power supplies and consumes 967 mW of power at 155 MSPS.

The separate 1.8-V supply for the digital output interface allows lower power operation with reduced noise. A power-down feature reduces the power consumption to 5 mW with the clock input disabled, while still allowing fast wake-up time to full operation.

The differential inputs provide a full scale differential input swing equal to 2 times the reference voltage. A stable 1-V internal voltage reference is provided, or the ADC14155 can be operated with an external reference.

The Clock mode (differential versus single-ended) and output data format (offset binary versus 2’s complement) are pin-selectable. A duty cycle stabilizer maintains performance over a wide range of clock duty cycles.

The ADC14155 is available in a 48-lead thermally enhanced multi-layer ceramic quad package and operates over the military temperature range of –55°C to +125°C.

Features

  • Total Ionizing Dose (TID) 100 krad(Si)
  • Single Event Latch-up 120 MeV-cm2/mg
  • 1.1-GHz Full-Power Bandwidth
  • Internal Sample-and-Hold Circuit
  • Low-Power Consumption
  • Internal Precision 1-V Reference
  • Single-Ended or Differential Clock Modes
  • Data Ready Output Clock
  • Clock Duty Cycle Stabilizer
  • Dual 3.3-V and 1.8-V Supply Operation (±10%)
  • Power-Down Mode
  • Offset Binary or 2’s Complement Output Data Format
  • 48-pin CFP Package (11.5-mm × 11.5-mm, 0.635-mm Pin-Pitch)
  • Key Specifications
    • Resolution 14 Bits
    • Conversion Rate 155 MSPS
    • SNR (fIN = 70 MHz) 70.1 dBFS (typ)
    • SFDR (fIN = 70 MHz) 82.3 dBFS (typ)
    • ENOB (fIN = 70 MHz) 11.3 Bits (typ)
    • Full-Power Bandwidth 1.1 GHz (typ)
    • Power Consumption 967 mW (typ)

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Parametrics Compare all products in Analog to Digital Converters

 
Resolution (Bits)
# Input Channels
INL (Max) (+/-LSB)
SNR (dB)
SFDR (dB)
Power Consumption (Typ) (mW)
Interface
Architecture
Analog Voltage AVDD (Min) (V)
Analog Voltage AVDD (Max) (V)
ENOB (Bits)
Digital Supply (Min) (V)
Digital Supply (Max) (V)
Operating Temperature Range (C)
Rating
Package Size: mm2:W x L (PKG)
Package Group
Reference Mode
ADC14155QML-SP ADC08D1520QML-SP
14     8    
1     2
1    
2.3     6    
70.1     47    
82.3     55.5    
967     2000    
Parallel CMOS     Parallel LVDS    
Pipeline     Folding Interpolating    
-0.3     1.8    
4.2     2.0    
11.3     7.4    
-0.3      
4.2      
-55 to 125
25    
-55 to 125
25    
Space     Space    
See datasheet (CFP)     See datasheet (CFP)    
CFP     CFP    
Int
Ext    
Int    

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