SBAS844 May 2017 ADC32RF42

PRODUCTION DATA. 

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Device Family Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1Absolute Maximum Ratings
    2. 7.2ESD Ratings
    3. 7.3Recommended Operating Conditions
    4. 7.4Thermal Information
    5. 7.5Electrical Characteristics
    6. 7.6AC Performance Characteristics
    7. 7.7Digital Requirements
    8. 7.8Timing Requirements
    9. 7.9Typical Characteristics
  8. Parameter Measurement Information
    1. 8.1Input Clock Diagram
  9. Detailed Description
    1. 9.1Overview
    2. 9.2Functional Block Diagram
    3. 9.3Feature Description
      1. 9.3.1 Analog Inputs
        1. 9.3.1.1Input Clamp Circuit
      2. 9.3.2 Clock Input
      3. 9.3.3 SYSREF Input
        1. 9.3.3.1Using SYSREF
        2. 9.3.3.2Frequency of the SYSREF Signal
      4. 9.3.4 DDC Block
        1. 9.3.4.1Operating Mode: Receiver
        2. 9.3.4.2Operating Mode: Wide-Bandwidth Observation Receiver
        3. 9.3.4.3Decimation Filters
          1. 9.3.4.3.1Divide-by-4
          2. 9.3.4.3.2Divide-by-6
          3. 9.3.4.3.3Divide-by-8
          4. 9.3.4.3.4Divide-by-9
          5. 9.3.4.3.5Divide-by-10
          6. 9.3.4.3.6Divide-by-12
          7. 9.3.4.3.7Divide-by-16
        4. 9.3.4.4Digital Multiplexer (MUX)
        5. 9.3.4.5Numerically-Controlled Oscillators (NCOs) and Mixers
      5. 9.3.5 NCO Switching
      6. 9.3.6 SerDes Transmitter Interface
      7. 9.3.7 Eye Diagrams
      8. 9.3.8 Alarm Outputs: Power Detectors for AGC Support
        1. 9.3.8.1Absolute Peak Power Detector
        2. 9.3.8.2Crossing Detector
        3. 9.3.8.3RMS Power Detector
        4. 9.3.8.4GPIO AGC MUX
      9. 9.3.9 Power-Down Mode
      10. 9.3.10ADC Test Pattern
        1. 9.3.10.1Digital Block
        2. 9.3.10.2Transport Layer
        3. 9.3.10.3Link Layer
    4. 9.4Device Functional Modes
      1. 9.4.1Device Configuration
      2. 9.4.2JESD204B Interface
        1. 9.4.2.1JESD204B Initial Lane Alignment (ILA)
        2. 9.4.2.2JESD204B Frame Assembly
        3. 9.4.2.3JESD204B Frame Assembly in Bypass Mode
        4. 9.4.2.4JESD204B Frame Assembly with Decimation (Single-Band DDC): Complex Output
        5. 9.4.2.5JESD204B Frame Assembly with Decimation (Single-Band DDC): Real Output
        6. 9.4.2.6JESD204B Frame Assembly with Decimation (Single-Band DDC): Real Output
        7. 9.4.2.7JESD204B Frame Assembly with Decimation (Dual-Band DDC): Complex Output
        8. 9.4.2.8JESD204B Frame Assembly with Decimation (Dual-Band DDC): Real Output
      3. 9.4.3Serial Interface
        1. 9.4.3.1Serial Register Write: Analog Bank
        2. 9.4.3.2Serial Register Readout: Analog Bank
        3. 9.4.3.3Serial Register Write: Digital Bank
        4. 9.4.3.4Serial Register Readout: Digital Bank
        5. 9.4.3.5Serial Register Write: Decimation Filter and Power Detector Pages
    5. 9.5Register Maps
      1. 9.5.1 Example Register Writes
      2. 9.5.2 Register Descriptions
        1. 9.5.2.1General Registers
          1. 9.5.2.1.1Register 000h (address = 000h), General Registers
          2. 9.5.2.1.2Register 002h (address = 002h), General Registers
          3. 9.5.2.1.3Register 003h (address = 003h), General Registers
          4. 9.5.2.1.4Register 004h (address = 004h), General Registers
          5. 9.5.2.1.5Register 010h (address = 010h), General Registers
          6. 9.5.2.1.6Register 011h (address = 011h), General Registers
          7. 9.5.2.1.7Register 012h (address = 012h), General Registers
      3. 9.5.3 Master Page (M = 0)
        1. 9.5.3.1Register 020h (address = 020h), Master Page
        2. 9.5.3.2Register 032h (address = 032h), Master Page
        3. 9.5.3.3Register 039h (address = 039h), Master Page
        4. 9.5.3.4Register 03Ch (address = 03Ch), Master Page
        5. 9.5.3.5Register 05Ah (address = 05Ah), Master Page
        6. 9.5.3.6Register 03Dh (address = 3Dh), Master Page
        7. 9.5.3.7Register 057h (address = 057h), Master Page
        8. 9.5.3.8Register 058h (address = 058h), Master Page
      4. 9.5.4 ADC Page (FFh, M = 0)
        1. 9.5.4.1Register 03Fh (address = 03Fh), ADC Page
        2. 9.5.4.2Register 042h (address = 042h), ADC Page
      5. 9.5.5 Offset Corr Page Channel A (610000h, M = 1)
        1. 9.5.5.1Register 068h (address = 068h), Offset Corr Page Channel A
      6. 9.5.6 Offset Corr Page Channel B (610100h, M = 1)
        1. 9.5.6.1Register 068h (address = 068h), Offset Corr Page Channel B
      7. 9.5.7 Digital Gain Page (610005h, M = 1 for Channel A and 610105h, M = 1 for Channel B)
        1. 9.5.7.1Register 0A6h (address = 0A6h), Digital Gain Page
      8. 9.5.8 Main Digital Page Channel A (680000h, M = 1)
        1. 9.5.8.1Register 000h (address = 000h), Main Digital Page Channel A
        2. 9.5.8.2Register 0A2h (address = 0A2h), Main Digital Page Channel A
      9. 9.5.9 Main Digital Page Channel B (680100h, M = 1)
        1. 9.5.9.1Register 0A2h (address = 0A2h), Main Digital Page Channel B
      10. 9.5.10JESD Digital Page (690000h, M = 1)
        1. 9.5.10.1 Register 001h (address = 001h), JESD Digital Page
        2. 9.5.10.2 Register 002h (address = 002h ), JESD Digital Page
        3. 9.5.10.3 Register 003h (address = 003h), JESD Digital Page
        4. 9.5.10.4 Register 004h (address = 004h), JESD Digital Page
        5. 9.5.10.5 Register 006h (address = 006h), JESD Digital Page
        6. 9.5.10.6 Register 007h (address = 007h), JESD Digital Page
        7. 9.5.10.7 Register 016h (address = 016h), JESD Digital Page
        8. 9.5.10.8 Register 017h (address = 017h), JESD Digital Page
        9. 9.5.10.9 Register 032h-035h (address = 032h-035h), JESD Digital Page
        10. 9.5.10.10Register 036h (address = 036h), JESD Digital Page
        11. 9.5.10.11Register 037h (address = 037h), JESD Digital Page
        12. 9.5.10.12Register 03Ch (address = 03Ch), JESD Digital Page
        13. 9.5.10.13Register 03Eh (address = 03Eh), JESD Digital Page
      11. 9.5.11Special Page Channel A
        1. 9.5.11.1Register 019h (address = 019h), Special Page Channel A
      12. 9.5.12Special Page Channel B
        1. 9.5.12.1Register 019h (address = 019h), Special Page Channel B
      13. 9.5.13Decimation Filter Page
        1. 9.5.13.1 Register 000h (address = 000h), Decimation Filter Page
        2. 9.5.13.2 Register 001h (address = 001h), Decimation Filter Page
        3. 9.5.13.3 Register 002h (address = 2h), Decimation Filter Page
        4. 9.5.13.4 Register 005h (address = 005h), Decimation Filter Page
        5. 9.5.13.5 Register 006h (address = 006h), Decimation Filter Page
        6. 9.5.13.6 Register 007h (address = 007h), Decimation Filter Page
        7. 9.5.13.7 Register 008h (address = 008h), Decimation Filter Page
        8. 9.5.13.8 Register 009h (address = 009h), Decimation Filter Page
        9. 9.5.13.9 Register 00Ah (address = 00Ah), Decimation Filter Page
        10. 9.5.13.10Register 00Bh (address = 00Bh), Decimation Filter Page
        11. 9.5.13.11Register 00Ch (address = 00Ch), Decimation Filter Page
        12. 9.5.13.12Register 00Dh (address = 00Dh), Decimation Filter Page
        13. 9.5.13.13Register 00Eh (address = 00Eh), Decimation Filter Page
        14. 9.5.13.14Register 00Fh (address = 00Fh), Decimation Filter Page
        15. 9.5.13.15Register 010h (address = 010h), Decimation Filter Page
        16. 9.5.13.16Register 011h (address = 011h), Decimation Filter Page
        17. 9.5.13.17Register 014h (address = 014h), Decimation Filter Page
        18. 9.5.13.18Register 016h (address = 016h), Decimation Filter Page
        19. 9.5.13.19Register 01Eh (address = 01Eh), Decimation Filter Page
        20. 9.5.13.20Register 01Fh (address = 01Fh), Decimation Filter Page
        21. 9.5.13.21Register 020h (address = 020h), Decimation Filter Page
        22. 9.5.13.22Register 033h-036h (address = 033h-036h), Decimation Filter Page
        23. 9.5.13.23Register 037h (address = 037h), Decimation Filter Page
        24. 9.5.13.24Register 038h (address = 038h), Decimation Filter Page
        25. 9.5.13.25Register 039h (address = 039h), Decimation Filter Page
        26. 9.5.13.26Register 03Ah (address = 03Ah), Decimation Filter Page
      14. 9.5.14Power Detector Page
        1. 9.5.14.1 Register 000h (address = 000h), Power Detector Page
        2. 9.5.14.2 Register 001h-002h (address = 001h-002h), Power Detector Page
        3. 9.5.14.3 Register 003h (address = 003h), Power Detector Page
        4. 9.5.14.4 Register 007h-00Ah (address = 007h-00Ah), Power Detector Page
        5. 9.5.14.5 Register 00Bh-00Ch (address = 00Bh-00Ch), Power Detector Page
        6. 9.5.14.6 Register 00Dh (address = 00Dh), Power Detector Page
        7. 9.5.14.7 Register 00Eh (address = 00Eh), Power Detector Page
        8. 9.5.14.8 Register 00Fh, 010h-012h, and 016h-019h (address = 00Fh, 010h-012h, and 016h-019h), Power Detector Page
        9. 9.5.14.9 Register 013h-01Ah (address = 013h-01Ah), Power Detector Page
        10. 9.5.14.10Register 01Dh-01Eh (address = 01Dh-01Eh), Power Detector Page
        11. 9.5.14.11Register 020h (address = 020h), Power Detector Page
        12. 9.5.14.12Register 021h (address = 021h), Power Detector Page
        13. 9.5.14.13Register 022h-025h (address = 022h-025h), Power Detector Page
        14. 9.5.14.14Register 027h (address = 027h), Power Detector Page
        15. 9.5.14.15Register 02Bh (address = 02Bh), Power Detector Page
        16. 9.5.14.16Register 037h (address = 037h), Power Detector Page
        17. 9.5.14.17Register 038h (address = 038h), Power Detector Page
        18. 9.5.14.18Power Detector Page (Direct Addressing, 16-Bit Address, 5400h)
          1. 9.5.14.18.1Register 032h-035h (address = 032h-035h), Power Detector Page
  10. 10Application and Implementation
    1. 10.1Application Information
      1. 10.1.1Start-Up Sequence
      2. 10.1.2Hardware Reset
      3. 10.1.3SNR and Clock Jitter
        1. 10.1.3.1External Clock Phase Noise Consideration
      4. 10.1.4Power Consumption in Different Modes
      5. 10.1.5Using DC Coupling in the ADC32RF42
        1. 10.1.5.1Bypassing the Offset Corrector Block
          1. 10.1.5.1.1Effect of Temperature
    2. 10.2Typical Application
      1. 10.2.1Design Requirements
        1. 10.2.1.1Transformer-Coupled Circuits
      2. 10.2.2Detailed Design Procedure
      3. 10.2.3Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1Layout Guidelines
    2. 12.2Layout Example
  13. 13Device and Documentation Support
    1. 13.1Documentation Support
      1. 13.1.1Related Documentation
    2. 13.2Receiving Notification of Documentation Updates
    3. 13.3Community Resources
    4. 13.4Trademarks
    5. 13.5Electrostatic Discharge Caution
    6. 13.6Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Features

  • 14-Bit, Dual-Channel, 1.5-GSPS ADC
  • Noise Floor: –151.8 dBFS/Hz
  • RF Input Supports Up to 4 GHz
  • Aperture Jitter: 90 fS
  • Channel Isolation: 95 dB at fIN = 1.8 GHz
  • Spectral Performance (fIN = 950 MHz, –2 dBFS):
    • SNR: 61.1 dBFS
    • SFDR: 67-dBc HD2, HD3
  • Spectral Performance (fIN = 1.85 GHz, –2 dBFS):
    • SNR: 58.9 dBFS
    • SFDR: 64-dBc HD2, HD3
  • On-Chip Digital Down-Converters:
    • Up to 4 DDCs (Dual-Band Mode)
    • Up to 3 Independent NCOs per DDC
  • On-Chip Input Clamp for Overvoltage Protection
  • Programmable On-Chip Power Detectors With Alarm Pins for AGC Support
  • On-Chip Dither
  • On-Chip Input Termination
  • Input Full-Scale: 1.35 VPP
  • Support for Multi-Chip Synchronization
  • JESD204B Interface:
    • Subclass 1-Based Deterministic Latency
    • 4 Lanes Per Channel Up to 12.5 Gbps
  • Power Dissipation: 2 W/Ch at 1.5 GSPS
  • 72-Pin VQFN Package (10 mm × 10 mm)

Applications

  • Multi-Band, Multi-Mode 2G, 3G, 4G Cellular Receivers
  • Phased Array Radars
  • Electronic Warfare
  • Cable Infrastructure
  • Broadband Wireless
  • High-Speed Digitizers
  • Software-Defined Radios
  • Communications Test Equipment
  • Microwave and Millimeter Wave Receivers

Description

The ADC32RF42 device is a 14-bit, 1.5-GSPS, dual-channel, analog-to-digital converter (ADC) that supports RF sampling with input frequencies up to 4 GHz and beyond. Designed for high signal-to-noise ratio (SNR), the ADC32RF42 delivers a noise spectral density of –151.8 dBFS/Hz as well as dynamic range and channel isolation over a large input frequency range. The buffered analog input with on-chip termination provides uniform input impedance across a wide frequency range and minimizes sample-and-hold glitch energy.

Each ADC channel can be connected to a dual-band, digital down-converter (DDC) with up to three independent, 16-bit numerically-controlled oscillators (NCOs) per DDC for phase-coherent frequency hopping. Additionally, the ADC is equipped with front-end peak and RMS power detectors and alarm functions to support external automatic gain control (AGC) algorithms.

The ADC32RF42 supports the JESD204B serial interface with subclass 1-based deterministic latency using data rates up to 12.5 Gbps with up to four lanes per ADC. The device is offered in a 72-pin VQFN package (10 mm × 10 mm) and supports the industrial temperature range (–40°C to +85°C).

Device Information(1)

PART NUMBERPACKAGEBODY SIZE (NOM)
ADC32RF42 VQFN (72)10.00 mm × 10.00 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.

Simplified Block Diagram

ADC32RF42 frontpage_sbas844.gif

Revision History

DATEREVISIONNOTES
May 2017*Initial release.