SBAS869 September 2017 ADC32RF82

PRODUCTION DATA. 

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 AC Performance Characteristics: fS = 2457.6 MSPS
    7. 6.7 AC Performance Characteristics: fS = 2211.84 MSPS
    8. 6.8 AC Performance Characteristics: fS = 1966.08 MSPS
    9. 6.9 Digital Requirements
    10. 6.10Timing Requirements
    11. 6.11Typical Characteristics
  7. Parameter Measurement Information
    1. 7.1Input Clock Diagram
  8. Detailed Description
    1. 8.1Overview
    2. 8.2Functional Block Diagram
    3. 8.3Feature Description
      1. 8.3.1 Analog Inputs
        1. 8.3.1.1Input Clamp Circuit
      2. 8.3.2 Clock Input
      3. 8.3.3 SYSREF Input
        1. 8.3.3.1Using SYSREF
        2. 8.3.3.2Frequency of the SYSREF Signal
      4. 8.3.4 DDC Block
        1. 8.3.4.1Operating Mode: Receiver
        2. 8.3.4.2Operating Mode: Wide-Bandwidth Observation Receiver
        3. 8.3.4.3Decimation Filters
          1. 8.3.4.3.1 Divide-by-4
          2. 8.3.4.3.2 Divide-by-6
          3. 8.3.4.3.3 Divide-by-8
          4. 8.3.4.3.4 Divide-by-9
          5. 8.3.4.3.5 Divide-by-10
          6. 8.3.4.3.6 Divide-by-12
          7. 8.3.4.3.7 Divide-by-16
          8. 8.3.4.3.8 Divide-by-18
          9. 8.3.4.3.9 Divide-by-20
          10. 8.3.4.3.10Divide-by-24
          11. 8.3.4.3.11Divide-by-32
          12. 8.3.4.3.12Latency with Decimation Options
        4. 8.3.4.4Digital Multiplexer (MUX)
        5. 8.3.4.5Numerically-Controlled Oscillators (NCOs) and Mixers
      5. 8.3.5 NCO Switching
      6. 8.3.6 SerDes Transmitter Interface
      7. 8.3.7 Eye Diagrams
      8. 8.3.8 Alarm Outputs: Power Detectors for AGC Support
        1. 8.3.8.1Absolute Peak Power Detector
        2. 8.3.8.2Crossing Detector
        3. 8.3.8.3RMS Power Detector
        4. 8.3.8.4GPIO AGC MUX
      9. 8.3.9 Power-Down Mode
      10. 8.3.10ADC Test Pattern
        1. 8.3.10.1Digital Block
        2. 8.3.10.2Transport Layer
        3. 8.3.10.3Link Layer
    4. 8.4Device Functional Modes
      1. 8.4.1Device Configuration
      2. 8.4.2JESD204B Interface
        1. 8.4.2.1JESD204B Initial Lane Alignment (ILA)
        2. 8.4.2.2JESD204B Frame Assembly
        3. 8.4.2.3JESD204B Frame Assembly with Decimation (Single-Band DDC): Complex Output
        4. 8.4.2.4JESD204B Frame Assembly with Decimation (Single-Band DDC): Real Output
        5. 8.4.2.5JESD204B Frame Assembly with Decimation (Single-Band DDC): Real Output
        6. 8.4.2.6JESD204B Frame Assembly with Decimation (Dual-Band DDC): Complex Output
        7. 8.4.2.7JESD204B Frame Assembly with Decimation (Dual-Band DDC): Real Output
      3. 8.4.3Serial Interface
        1. 8.4.3.1Serial Register Write: Analog Bank
        2. 8.4.3.2Serial Register Readout: Analog Bank
        3. 8.4.3.3Serial Register Write: Digital Bank
        4. 8.4.3.4Serial Register Readout: Digital Bank
        5. 8.4.3.5Serial Register Write: Decimation Filter and Power Detector Pages
    5. 8.5Register Maps
      1. 8.5.1 Example Register Writes
      2. 8.5.2 Register Descriptions
        1. 8.5.2.1General Registers
          1. 8.5.2.1.1Register 000h (address = 000h), General Registers
          2. 8.5.2.1.2Register 002h (address = 002h), General Registers
          3. 8.5.2.1.3Register 003h (address = 003h), General Registers
          4. 8.5.2.1.4Register 004h (address = 004h), General Registers
          5. 8.5.2.1.5Register 010h (address = 010h), General Registers
          6. 8.5.2.1.6Register 011h (address = 011h), General Registers
          7. 8.5.2.1.7Register 012h (address = 012h), General Registers
      3. 8.5.3 Master Page (M = 0)
        1. 8.5.3.1Register 020h (address = 020h), Master Page
        2. 8.5.3.2Register 032h (address = 032h), Master Page
        3. 8.5.3.3Register 039h (address = 039h), Master Page
        4. 8.5.3.4Register 03Ch (address = 03Ch), Master Page
        5. 8.5.3.5Register 05Ah (address = 05Ah), Master Page
        6. 8.5.3.6Register 03Dh (address = 3Dh), Master Page
        7. 8.5.3.7Register 057h (address = 057h), Master Page
        8. 8.5.3.8Register 058h (address = 058h), Master Page
      4. 8.5.4 ADC Page (FFh, M = 0)
        1. 8.5.4.1Register 03Fh (address = 03Fh), ADC Page
        2. 8.5.4.2Register 042h (address = 042h), ADC Page
      5. 8.5.5 Digital Function Page (610000h, M = 1 for Channel A and 610100h, M = 1 for Channel B)
        1. 8.5.5.1Register A6h (address = 0A6h), Digital Function Page
      6. 8.5.6 Offset Corr Page Channel A (610000h, M = 1)
        1. 8.5.6.1Register 034h (address = 034h), Offset Corr Page Channel A
        2. 8.5.6.2Register 068h (address = 068h), Offset Corr Page Channel A
      7. 8.5.7 Offset Corr Page Channel B (610000h, M = 1)
        1. 8.5.7.1Register 068h (address = 068h), Offset Corr Page Channel B
      8. 8.5.8 Digital Gain Page (610005h, M = 1 for Channel A and 610105h, M = 1 for Channel B)
        1. 8.5.8.1Register 0A6h (address = 0A6h), Digital Gain Page
      9. 8.5.9 Main Digital Page Channel A (680000h, M = 1)
        1. 8.5.9.1Register 000h (address = 000h), Main Digital Page Channel A
        2. 8.5.9.2Register 0A2h (address = 0A2h), Main Digital Page Channel A
      10. 8.5.10Register 0A5h (address = 0A5h) Main Digital Page Channel A
      11. 8.5.11Register 0A9h (address = 0A9h) Main Digital Page Channel A
      12. 8.5.12Register 0B0h (address = 0B0h) Main Digital Page Channel A
      13. 8.5.13Register 0B1h (address = 0B1h) Main Digital Page Channel A
      14. 8.5.14Register 0B2h (address = 0B2h) Main Digital Page Channel A
      15. 8.5.15Register 0B3h (address = 0B3h) Main Digital Page Channel A
      16. 8.5.16Register 0B4h (address = 0B4h) Main Digital Page Channel A
      17. 8.5.17Register 0B5h (address = 0B5h) Main Digital Page Channel A
      18. 8.5.18Register 0B6h (address = 0B6h) Main Digital Page Channel A
      19. 8.5.19Register 0B7h (address = 0B7h) Main Digital Page Channel A
      20. 8.5.20Register 0B8h (address = 0B8h) Main Digital Page Channel A
      21. 8.5.21Register 0B9h (address = 0B9h) Main Digital Page Channel A
      22. 8.5.22Register 0BAh (address = 0BAh) Main Digital Page Channel A
      23. 8.5.23Register 0BBh (address = 0BBh) Main Digital Page Channel A
      24. 8.5.24Main Digital Page Channel B (680001h, M = 1)
        1. 8.5.24.1 Register 000h (address = 000h), Main Digital Page Channel B
        2. 8.5.24.2 Register 0A2h (address = 0A2h), Main Digital Page Channel B
        3. 8.5.24.3 Register 0B0h (address = 0B0h) Main Digital Page Channel B
        4. 8.5.24.4 Register 0B1h (address = 0B1h) Main Digital Page Channel B
        5. 8.5.24.5 Register 0B2h (address = 0B2h) Main Digital Page Channel B
        6. 8.5.24.6 Register 0B3h (address = 0B3h) Main Digital Page Channel B
        7. 8.5.24.7 Register 0B4h (address = 0B4h) Main Digital Page Channel B
        8. 8.5.24.8 Register 0B5h (address = 0B5h) Main Digital Page Channel B
        9. 8.5.24.9 Register 0B6h (address = 0B6h) Main Digital Page Channel B
        10. 8.5.24.10Register 0B7h (address = 0B7h) Main Digital Page Channel B
        11. 8.5.24.11Register 0B8h (address = 0B8h) Main Digital Page Channel B
        12. 8.5.24.12Register 0B9h (address = 0B9h) Main Digital Page Channel B
        13. 8.5.24.13Register 0BAh (address = 0BAh) Main Digital Page Channel B
        14. 8.5.24.14Register 0BBh (address = 0BBh) Main Digital Page Channel B
      25. 8.5.25JESD Digital Page (6900h, M = 1)
        1. 8.5.25.1 Register 001h (address = 001h), JESD Digital Page
        2. 8.5.25.2 Register 002h (address = 002h ), JESD Digital Page
        3. 8.5.25.3 Register 003h (address = 003h), JESD Digital Page
        4. 8.5.25.4 Register 004h (address = 004h), JESD Digital Page
        5. 8.5.25.5 Register 006h (address = 006h), JESD Digital Page
        6. 8.5.25.6 Register 007h (address = 007h), JESD Digital Page
        7. 8.5.25.7 Register 016h (address = 016h), JESD Digital Page
        8. 8.5.25.8 Register 017h (address = 017h), JESD Digital Page
        9. 8.5.25.9 Register 032h-035h (address = 032h-035h), JESD Digital Page
        10. 8.5.25.10Register 036h (address = 036h), JESD Digital Page
        11. 8.5.25.11Register 037h (address = 037h), JESD Digital Page
        12. 8.5.25.12Register 03Ch (address = 03Ch), JESD Digital Page
        13. 8.5.25.13Register 03Eh (address = 03Eh), JESD Digital Page
      26. 8.5.26Decimation Filter Page
        1. 8.5.26.1 Register 000h (address = 000h), Decimation Filter Page
        2. 8.5.26.2 Register 001h (address = 001h), Decimation Filter Page
        3. 8.5.26.3 Register 002h (address = 2h), Decimation Filter Page
        4. 8.5.26.4 Register 005h (address = 005h), Decimation Filter Page
        5. 8.5.26.5 Register 006h (address = 006h), Decimation Filter Page
        6. 8.5.26.6 Register 007h (address = 007h), Decimation Filter Page
        7. 8.5.26.7 Register 008h (address = 008h), Decimation Filter Page
        8. 8.5.26.8 Register 009h (address = 009h), Decimation Filter Page
        9. 8.5.26.9 Register 00Ah (address = 00Ah), Decimation Filter Page
        10. 8.5.26.10Register 00Bh (address = 00Bh), Decimation Filter Page
        11. 8.5.26.11Register 00Ch (address = 00Ch), Decimation Filter Page
        12. 8.5.26.12Register 00Dh (address = 00Dh), Decimation Filter Page
        13. 8.5.26.13Register 00Eh (address = 00Eh), Decimation Filter Page
        14. 8.5.26.14Register 00Fh (address = 00Fh), Decimation Filter Page
        15. 8.5.26.15Register 010h (address = 010h), Decimation Filter Page
        16. 8.5.26.16Register 011h (address = 011h), Decimation Filter Page
        17. 8.5.26.17Register 014h (address = 014h), Decimation Filter Page
        18. 8.5.26.18Register 016h (address = 016h), Decimation Filter Page
        19. 8.5.26.19Register 01Eh (address = 01Eh), Decimation Filter Page
        20. 8.5.26.20Register 01Fh (address = 01Fh), Decimation Filter Page
        21. 8.5.26.21Register 033h-036h (address = 033h-036h), Decimation Filter Page
        22. 8.5.26.22Register 037h (address = 037h), Decimation Filter Page
        23. 8.5.26.23Register 038h (address = 038h), Decimation Filter Page
        24. 8.5.26.24Register 039h (address = 039h), Decimation Filter Page
        25. 8.5.26.25Register 03Ah (address = 03Ah), Decimation Filter Page
      27. 8.5.27Power Detector Page
        1. 8.5.27.1 Register 000h (address = 000h), Power Detector Page
        2. 8.5.27.2 Register 001h-002h (address = 001h-002h), Power Detector Page
        3. 8.5.27.3 Register 003h (address = 003h), Power Detector Page
        4. 8.5.27.4 Register 007h-00Ah (address = 007h-00Ah), Power Detector Page
        5. 8.5.27.5 Register 00Bh-00Ch (address = 00Bh-00Ch), Power Detector Page
        6. 8.5.27.6 Register 00Dh (address = 00Dh), Power Detector Page
        7. 8.5.27.7 Register 00Eh (address = 00Eh), Power Detector Page
        8. 8.5.27.8 Register 00Fh, 010h-012h, and 016h-019h (address = 00Fh, 010h-012h, and 016h-019h), Power Detector Page
        9. 8.5.27.9 Register 013h-01Ah (address = 013h-01Ah), Power Detector Page
        10. 8.5.27.10Register 01Dh-01Eh (address = 01Dh-01Eh), Power Detector Page
        11. 8.5.27.11Register 020h (address = 020h), Power Detector Page
        12. 8.5.27.12Register 021h (address = 021h), Power Detector Page
        13. 8.5.27.13Register 022h-025h (address = 022h-025h), Power Detector Page
        14. 8.5.27.14Register 027h (address = 027h), Power Detector Page
        15. 8.5.27.15Register 02Bh (address = 02Bh), Power Detector Page
        16. 8.5.27.16Register 032h-035h (address = 032h-035h), Power Detector Page
        17. 8.5.27.17Register 037h (address = 037h), Power Detector Page
        18. 8.5.27.18Register 038h (address = 038h), Power Detector Page
  9. Application and Implementation
    1. 9.1Application Information
      1. 9.1.1Start-Up Sequence
      2. 9.1.2Hardware Reset
      3. 9.1.3SNR and Clock Jitter
        1. 9.1.3.1External Clock Phase Noise Consideration
      4. 9.1.4Power Consumption in Different Modes
      5. 9.1.5Using DC Coupling in the ADC32RF82
        1. 9.1.5.1Bypassing the Offset Corrector Block
          1. 9.1.5.1.1Effect of Temperature
    2. 9.2Typical Application
      1. 9.2.1Design Requirements
        1. 9.2.1.1Transformer-Coupled Circuits
      2. 9.2.2Detailed Design Procedure
      3. 9.2.3Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1Layout Guidelines
    2. 11.2Layout Example
  12. 12Device and Documentation Support
    1. 12.1Documentation Support
      1. 12.1.1Related Documentation
    2. 12.2Receiving Notification of Documentation Updates
    3. 12.3Community Resources
    4. 12.4Trademarks
    5. 12.5Electrostatic Discharge Caution
    6. 12.6Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Features

  • 14-Bit, Dual-Channel, 2457.6-MSPS ADC
  • Noise Floor: –154.1 dBFS/Hz
  • RF Input Supports Up to 4.0 GHz
  • Aperture Jitter: 90 fS
  • Channel Isolation: 95 dB at fIN = 1.8 GHz
  • Spectral Performance (fIN = 900 MHz, –2 dBFS):
    • SNR: 61.2 dBFS
    • SFDR: 67-dBc HD2, HD3
    • SFDR: 81-dBc Worst Spur
  • Spectral Performance (fIN = 1.85 GHz, –2 dBFS):
    • SNR: 58.7 dBFS
    • SFDR: 71-dBc HD2, HD3
    • SFDR: 76-dBc Worst Spur
  • On-Chip Digital Down-Converters:
    • Up to 4 DDCs (Dual-Band Mode)
    • Up to 3 Independent NCOs per DDC
  • On-Chip Input Clamp for Overvoltage Protection
  • Programmable On-Chip Power Detectors with Alarm Pins for AGC Support
  • On-Chip Dither
  • On-Chip Input Termination
  • Input Full-Scale: 1.35 VPP
  • Support for Multi-Chip Synchronization
  • JESD204B Interface:
    • Subclass 1-Based Deterministic Latency
    • 4 Lanes Per Channel at 12.5 Gbps
  • Power Dissipation: 3.0 W/Ch at 2457.6 MSPS
  • 72-Pin VQFN Package (10 mm × 10 mm)

Applications

  • Multi-Carrier GSM Cellular Infrastructure Base Stations
  • Telecommunications Receivers
  • DPD Observation Receivers
  • Backhaul Receivers
  • RF Repeaters and Distributed Antenna Systems

Description

The ADC32RF82 is a 14-bit, 2457.6-MSPS, dual-channel telecom receiver and feedback device family that supports RF sampling with input frequencies up to 4 GHz and beyond. Designed for high signal-to-noise ratio (SNR), the ADC32RF82 delivers a noise spectral density of –154.1 dBFS/Hz as well as dynamic range and channel isolation over a large input frequency range. The buffered analog input with on-chip termination provides uniform input impedance across a wide frequency range and minimizes sample-and-hold glitch energy.

Each channel can be connected to a dual-band, digital down-converter (DDC) with up to three independent, 16-bit numerically-controlled oscillators (NCOs) per DDC for phase-coherent frequency hopping. Additionally, the ADC is equipped with front-end peak and RMS power detectors and alarm functions to support external automatic gain control (AGC) algorithms.

The ADC32RF82 supports the JESD204B serial interface with subclass 1-based deterministic latency using data rates up to 12.5 Gbps with up to four lanes per ADC. The device is offered in a 72-pin VQFN package (10 mm × 10 mm) and supports the industrial temperature range (–40°C to +85°C).

Device Information(1)

PART NUMBERPACKAGEBODY SIZE (NOM)
ADC32RF82 VQFN (72)10.00 mm × 10.00 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.

Simplified Block Diagram

ADC32RF82 fbd_sbas774.gif

Revision History

DATEREVISIONNOTES
September 2017*Initial release.