Product details

Sample rate (max) (Msps) 50 Resolution (Bits) 12 Number of input channels 4 Interface type Serial LVDS Analog input BW (MHz) 540 Features Low Power Rating Catalog Peak-to-peak input voltage range (V) 2 Power consumption (typ) (mW) 228 Architecture Pipeline SNR (dB) 71 ENOB (bit) 11.5 SFDR (dB) 95 Operating temperature range (°C) -40 to 85 Input buffer No
Sample rate (max) (Msps) 50 Resolution (Bits) 12 Number of input channels 4 Interface type Serial LVDS Analog input BW (MHz) 540 Features Low Power Rating Catalog Peak-to-peak input voltage range (V) 2 Power consumption (typ) (mW) 228 Architecture Pipeline SNR (dB) 71 ENOB (bit) 11.5 SFDR (dB) 95 Operating temperature range (°C) -40 to 85 Input buffer No
VQFN (RTQ) 56 64 mm² 8 x 8
  • Quad Channel
  • 12-Bit Resolution
  • Single Supply: 1.8 V
  • Serial LVDS Interface
  • Flexible Input Clock Buffer with Divide-by-1, -2, -4
  • SNR = 70.2 dBFS, SFDR = 87 dBc at
    fIN = 70 MHz
  • Ultra-Low Power Consumption:
    • 98 mW/Ch at 125 MSPS
  • Channel Isolation: 105 dB
  • Internal Dither and Chopper
  • Support for Multi-Chip Synchronization
  • Pin-to-Pin Compatible with 14-Bit Version
  • Package: VQFN-56 (8 mm × 8 mm)
  • Quad Channel
  • 12-Bit Resolution
  • Single Supply: 1.8 V
  • Serial LVDS Interface
  • Flexible Input Clock Buffer with Divide-by-1, -2, -4
  • SNR = 70.2 dBFS, SFDR = 87 dBc at
    fIN = 70 MHz
  • Ultra-Low Power Consumption:
    • 98 mW/Ch at 125 MSPS
  • Channel Isolation: 105 dB
  • Internal Dither and Chopper
  • Support for Multi-Chip Synchronization
  • Pin-to-Pin Compatible with 14-Bit Version
  • Package: VQFN-56 (8 mm × 8 mm)

The ADC342x are a high-linearity, ultra-low power, quad-channel, 12-bit, 25-MSPS to 125-MSPS, analog-to-digital converter (ADC) family. The devices are designed specifically to support demanding, high input frequency signals with large dynamic range requirements. An input clock divider allows more flexibility for system clock architecture design and the SYSREF input enables complete system synchronization. The ADC342x family supports serial low-voltage differential signaling (LVDS) in order to reduce the number of interface lines, thus allowing for high system integration density. The serial LVDS interface is two-wire, where each ADC data are serialized and output over two LVDS pairs. An internal phase-locked loop (PLL) multiplies the incoming ADC sampling clock to derive the bit clock that is used to serialize the 12-bit output data from each channel. In addition to the serial data streams, the frame and bit clocks are also transmitted as LVDS outputs.

The ADC342x are a high-linearity, ultra-low power, quad-channel, 12-bit, 25-MSPS to 125-MSPS, analog-to-digital converter (ADC) family. The devices are designed specifically to support demanding, high input frequency signals with large dynamic range requirements. An input clock divider allows more flexibility for system clock architecture design and the SYSREF input enables complete system synchronization. The ADC342x family supports serial low-voltage differential signaling (LVDS) in order to reduce the number of interface lines, thus allowing for high system integration density. The serial LVDS interface is two-wire, where each ADC data are serialized and output over two LVDS pairs. An internal phase-locked loop (PLL) multiplies the incoming ADC sampling clock to derive the bit clock that is used to serialize the 12-bit output data from each channel. In addition to the serial data streams, the frame and bit clocks are also transmitted as LVDS outputs.

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Type Title Date
* Data sheet ADC342x Quad-Channel, 12-Bit, 25-MSPS to 125-MSPS, Analog-to-Digital Converter datasheet (Rev. A) PDF | HTML 30 Sep 2015
EVM User's guide ADC3xxxEVM and ADC3xJxxEVM User's Guide (Rev. D) 24 Aug 2018

Design & development

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Simulation model

ADC3444 IBIS Model

SLAM232.ZIP (36 KB) - IBIS Model
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ADC3xxx Pspice Model

SLAM228.ZIP (15 KB) - PSpice Model
Simulation model

ADC3xxx TINA Model

SLAM226.ZIP (3 KB) - TINA-TI Spice Model
Simulation model

ADC3xxx TINA Reference Design

SLAM227.TSC (1083 KB) - TINA-TI Reference Design
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PSPICE-FOR-TI — PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Reference designs

TIDA-00799 — Quad-Channel, 12-Bit, 50-MSPS ADC Reference Design With Low Noise, Low Distortion, DC and AC Inputs

This reference design demonstrates how to implement a single-ended-to-differential input path, which can be AC-coupled or DC-coupled for an ADC3422. It also explains how to design a high-input impedance, DC-coupled input path. The reference design can be used for applications such as low-power (...)
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VQFN (RTQ) 56 View options

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