ADC34J45
- Quad Channel
- 14-Bit Resolution
- Single 1.8-V Supply
- Flexible Input Clock Buffer with Divide-by-1, -2, -4
- SNR = 72 dBFS, SFDR = 86 dBc at
fIN = 70 MHz - Ultra-Low Power Consumption:
- 203 mW/Ch at 160 MSPS
- Channel Isolation: 105 dB
- Internal Dither
- JESD204B Serial Interface:
- Supports Subclass 0, 1, 2
- Supports One Lane per ADC up to 160 MSPS
- Support for Multi-Chip Synchronization
- Pin-to-Pin Compatible with 12-Bit Version
- Package: VQFN-48 (7 mm × 7 mm)
The ADC34J4x is a high-linearity, ultra-low power, quad-channel, 14-bit, 50-MSPS to 160-MSPS, analog-to-digital converter (ADC). The devices are designed specifically to support demanding, high input frequency signals with large dynamic range requirements. A clock input divider allows more flexibility for system clock architecture design while the SYSREF input enables complete system synchronization. The ADC34J4x family supports serial current-mode logic (CML) and JESD204B interfaces in order to reduce the number of interface lines, thus allowing high system integration density. The JESD204B interface is a serial interface, where the data of each ADC are serialized and output over only one differential pair. An internal phase-locked loop (PLL) multiplies the incoming ADC sampling clock by 20 to derive the bit clock that is used to serialize the 14-bit data from each channel. The ADC34J4x devices support subclass 1 with interface speeds up to 3.2 Gbps.
Technical documentation
Type | Title | Date | ||
---|---|---|---|---|
* | Data sheet | ADC34J4x Quad-Channel, 14-Bit, 50-MSPS to 160-MSPS, Analog-to-Digital Converter with a JESD204B Interface datasheet (Rev. B) | PDF | HTML | 10 Nov 2014 |
Application brief | Time of Flight and LIDAR - Optical Front End Design (Rev. A) | PDF | HTML | 29 Apr 2022 | |
EVM User's guide | ADC3xxxEVM and ADC3xJxxEVM User's Guide (Rev. D) | 24 Aug 2018 | ||
White paper | Minimum Power Specifications for High-Performance ADC Power-Supply Designs | 31 Mar 2016 | ||
Design guide | Optical Front-End System Design Guide | 26 Oct 2015 |
Design & development
For additional terms or required resources, click any title below to view the detail page where available.
ADC34J45EVM — ADC34J45 Quad-Channel, 14-Bit, 160-MSPS Analog-to-Digital Converter Evaluation Module
The ADC34J45 EVM demonstrates the performance of a low power quad 160Msps 14 bit ADC. It includes the ADC34J45 device, LMK04828 JESD204B clocking solution and TI voltage regulators to provide the necessary voltages. The input for the ADC is connected to a transformer input which can be connected to (...)
TI-JESD204-IP — JESD204 Rapid Design IP for FPGAs connected to TI high-speed data converters
PSPICE-FOR-TI — PSpice® for TI design and simulation tool
TIDA-00725 — Wide Bandwidth Optical Front-end Reference Design
Package | Pins | Download |
---|---|---|
VQFN (RGZ) | 48 | View options |
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