ADS52J65 8-channel 16-bit 125MSPS analog-to-digital converter (ADC) with JESD204B interface | TI.com

ADS52J65 (ACTIVE)

8-channel 16-bit 125MSPS analog-to-digital converter (ADC) with JESD204B interface

 

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Description

The 8-channel, 16-bit ADS52J65 analog-to-digital converter (ADC) uses CMOS process and innovative circuit techniques. It is designed to operate at low power and give very high signal-to-noise ratio (SNR) performance with a 2-Vpp full-scale input. The device gives 80-dBFS idle SNR and 78-dBFS full-scale SNR at 5 MHz. The large input bandwidth of 250 MHz makes the device suitable for a wide range of applications, such as high frequency medical ultrasound, magnetic resonance imaging, and multi-channel data acquisition. The ADC integrates an internal reference trimmed to match across devices.

ADS52J65 has advanced digital features, including a digital I/Q demodulator with fractional decimation filter. The ADC data from each channel is encoded using an 8B to 10B format and is sent as a SerDes data stream using current-mode logic (CML) output buffers, as per the JESD204B standard. The ADC data from all eight channels can be output over a single CML buffer (1-lane SerDes) with the data rate limited to a maximum of 12.8 Gbps. Using SerDes outputs reduces the number of interface lines. This, together with the low-power design, enables eight channels to be packaged in a 9-mm × 9-mm VQFN allowing high system integration densities. ADS52J65 also supports modes where all ADC data is sent over four CML buffers (4-Lane SerDes), reducing the SerDes data rate per lane for low-cost FPGAs.

The ADS52J65 is available in a non-magnetic VQFN package that does not create any magnetic artifact. The device is specified over –40°C to +85°C.

Features

  • 16-Bit Resolution, Idle SNR: 80 dBFS
  • 70 mW/Ch at 125 MSPS, 4-CH per Lane
  • 45 mW/Ch at 62.5 MSPS, 8-CH per Lane
  • Full-Scale Input: 2 VPP
  • Full-Scale SNR: 78 dBFS at fin = 10 MHz
  • Full-Scale SFDR: –85 dBc at fin = 10 MHz
  • Analog Input –3 dB Bandwidth = 250 MHz
  • Maximum Input Signal Frequency for 2 VPP Input = 130 MHz
  • Fast and Consistent Overload Recovery
  • Advanced Digital Features
    • Automatic DC Offset Correction
    • Digital Average
  • Digital I/Q Demodulator
    • Fractional Decimation Filter M = 1 to 63 With Increments of 0.25
    • Data Output Rate Reduction After Decimation
    • 64 mW/Ch at 80 MSPS and Decimation = 2
    • On-Chip RAM With 32 Preset Profiles
  • JESD204B Subclass 0, 1, and 2
    • 2, 4, or 8 Channels per JESD Lane
    • 10-Gbps JESD Interface
    • Supports lane rate up to 12.8 Gbps for short trace length (< 5 Inch)
  • 64-Pin Non-Magnetic 9 × 9-mm Package

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Parametrics

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Part number Order Sample rate (Max) (MSPS) Features Resolution (Bits) Number of input channels SNR (dB) ENOB (Bits) SFDR (dB) Power consumption (Typ) (mW) Input range (Vp-p) Interface Operating temperature range (C) Analog input BW (MHz) Input buffer Package Group Package size: mm2:W x L (PKG) Rating Architecture
ADS52J65 Order now 125     High Performance     16     8     78     13     85     560     2     JESD204B     -40 to 85     250     No     VQFN | 64     64VQFN: 81 mm2: 9 x 9 (VQFN | 64)     Catalog     Pipeline    
ADS5294 Order now 80     Low Power     12
14    
8     75.5     12.2     84     464     2     Serial LVDS     -40 to 85     550     No     HTQFP | 80     80HTQFP: 196 mm2: 14 x 14 (HTQFP | 80)     Catalog     Pipeline    
ADS5295 Order now 100     High Performance     12     8     70.6     11.4     86     640     2     Serial LVDS     -40 to 85     500     No     HTQFP | 80     80HTQFP: 196 mm2: 14 x 14 (HTQFP | 80)     Catalog     Pipeline    
ADS52J90 Order now 65     Low Power     14     16     73.5       80     656     2     JESD204B
Serial LVDS    
-40 to 85     70     No     NFBGA | 198     198NFBGA: 135 mm2: 15 x 9 (NFBGA | 198)     Catalog     SAR