The ADS54J54 is a low power, wide bandwidth 14-bit 500 MSPS quad channel analog-to-digital converter (ADC). It supports the JESD204B serial interface with data rates up to 5 Gbps supporting 1 or 2 lanes per ADC. The buffered analog input provides uniform input impedance across a wide frequency range while minimizing sample-and-hold glitch energy. A sampling clock divider allows more flexibility for system clock architecture design. The ADS54J54 provides excellent spurious-free dynamic range (SFDR) over a large input frequency range with very low power consumption. Optional 2x Decimation Filter provides high-pass or low-pass filter modes.
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|Part number||Order||Sample rate (Max) (MSPS)||Features||Resolution (Bits)||Number of input channels||SNR (dB)||ENOB (Bits)||SFDR (dB)||Power consumption (Typ) (mW)||Input range (Vp-p)||Interface||Operating temperature range (C)||Analog input BW (MHz)||Input buffer||Package Group||Package size: mm2:W x L (PKG)||Rating||Architecture|
||500||High Performance||14||4||68.3||11||95||3500||1.25||JESD204B||-40 to 85||900||Yes||VQFN | 64||64VQFN: 81 mm2: 9 x 9 (VQFN | 64)||Catalog||Pipeline|