SBAS706C April 2015  – January 2017 ADS54J60

PRODUCTION DATA. 

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 AC Characteristics
    7. 7.7 Digital Characteristics
    8. 7.8 Timing Characteristics
    9. 7.9 Typical Characteristics
    10. 7.10Typical Characteristics: Contour
  8. Detailed Description
    1. 8.1Overview
    2. 8.2Functional Block Diagram
    3. 8.3Feature Description
      1. 8.3.1Analog Inputs
      2. 8.3.2DDC Block
        1. 8.3.2.1Decimate-by-2 Filter
        2. 8.3.2.2Decimate-by-4 Filter Using a Digital Mixer
        3. 8.3.2.3Decimate-by-4 Filter with IQ Outputs
      3. 8.3.3SYSREF Signal
        1. 8.3.3.1SYSREF Not Present (Subclass 0, 2)
      4. 8.3.4Overrange Indication
        1. 8.3.4.1Fast OVR
      5. 8.3.5Power-Down Mode
    4. 8.4Device Functional Modes
      1. 8.4.1Device Configuration
        1. 8.4.1.1Serial Interface
        2. 8.4.1.2Serial Register Write: Analog Bank
        3. 8.4.1.3Serial Register Readout: Analog Bank
        4. 8.4.1.4JESD Bank SPI Page Selection
        5. 8.4.1.5Serial Register Write: JESD Bank
          1. 8.4.1.5.1Individual Channel Programming
        6. 8.4.1.6Serial Register Readout: JESD Bank
      2. 8.4.2JESD204B Interface
        1. 8.4.2.1JESD204B Initial Lane Alignment (ILA)
        2. 8.4.2.2JESD204B Test Patterns
        3. 8.4.2.3JESD204B Frame
        4. 8.4.2.4JESD204B Frame
        5. 8.4.2.5JESD204B Frame Assembly with Decimation
          1. 8.4.2.5.1JESD Transmitter Interface
          2. 8.4.2.5.2Eye Diagram
    5. 8.5Register Maps
      1. 8.5.1Example Register Writes
      2. 8.5.2Register Descriptions
        1. 8.5.2.1General Registers
          1. 8.5.2.1.1Register 0h (address = 0h)
          2. 8.5.2.1.2Register 3h (address = 3h)
          3. 8.5.2.1.3Register 4h (address = 4h)
          4. 8.5.2.1.4Register 5h (address = 5h)
          5. 8.5.2.1.5Register 11h (address = 11h)
        2. 8.5.2.2Master Page (080h) Registers
          1. 8.5.2.2.1 Register 20h (address = 20h), Master Page (080h)
          2. 8.5.2.2.2 Register 21h (address = 21h), Master Page (080h)
          3. 8.5.2.2.3 Register 23h (address = 23h), Master Page (080h)
          4. 8.5.2.2.4 Register 24h (address = 24h), Master Page (080h)
          5. 8.5.2.2.5 Register 26h (address = 26h), Master Page (080h)
          6. 8.5.2.2.6 Register 4Fh (address = 4Fh), Master Page (080h)
          7. 8.5.2.2.7 Register 53h (address = 53h), Master Page (080h)
          8. 8.5.2.2.8 Register 54h (address = 54h), Master Page (080h)
          9. 8.5.2.2.9 Register 55h (address = 55h), Master Page (080h)
          10. 8.5.2.2.10Register 59h (address = 59h), Master Page (080h)
        3. 8.5.2.3ADC Page (0Fh) Register
          1. 8.5.2.3.1Register 5F (address = 5F), ADC Page (0Fh)
        4. 8.5.2.4Main Digital Page (6800h) Registers
          1. 8.5.2.4.1 Register 0h (address = 0h), Main Digital Page (6800h)
          2. 8.5.2.4.2 Register 41h (address = 41h), Main Digital Page (6800h)
          3. 8.5.2.4.3 Register 42h (address = 42h), Main Digital Page (6800h)
          4. 8.5.2.4.4 Register 43h (address = 43h), Main Digital Page (6800h)
          5. 8.5.2.4.5 Register 44h (address = 44h), Main Digital Page (6800h)
          6. 8.5.2.4.6 Register 4Bh (address = 4Bh), Main Digital Page (6800h)
          7. 8.5.2.4.7 Register 4Dh (address = 4Dh), Main Digital Page (6800h)
          8. 8.5.2.4.8 Register 4Eh (address = 4Eh), Main Digital Page (6800h)
          9. 8.5.2.4.9 Register 52h (address = 52h), Main Digital Page (6800h)
          10. 8.5.2.4.10Register 72h (address = 72h), Main Digital Page (6800h)
          11. 8.5.2.4.11Register ABh (address = ABh), Main Digital Page (6800h)
          12. 8.5.2.4.12Register ADh (address = ADh), Main Digital Page (6800h)
          13. 8.5.2.4.13Register F7h (address = F7h), Main Digital Page (6800h)
        5. 8.5.2.5JESD Digital Page (6900h) Registers
          1. 8.5.2.5.1 Register 0h (address = 0h), JESD Digital Page (6900h)
          2. 8.5.2.5.2 Register 1h (address = 1h), JESD Digital Page (6900h)
          3. 8.5.2.5.3 Register 2h (address = 2h), JESD Digital Page (6900h)
          4. 8.5.2.5.4 Register 3h (address = 3h), JESD Digital Page (6900h)
          5. 8.5.2.5.5 Register 5h (address = 5h), JESD Digital Page (6900h)
          6. 8.5.2.5.6 Register 6h (address = 6h), JESD Digital Page (6900h)
          7. 8.5.2.5.7 Register 7h (address = 7h), JESD Digital Page (6900h)
          8. 8.5.2.5.8 Register 16h (address = 16h), JESD Digital Page (6900h)
          9. 8.5.2.5.9 Register 31h (address = 31h), JESD Digital Page (6900h)
          10. 8.5.2.5.10Register 32h (address = 32h), JESD Digital Page (6900h)
        6. 8.5.2.6JESD Analog Page (6A00h) Register
          1. 8.5.2.6.1Register 12h-5h (address = 12h-5h), JESD Analog Page (6A00h)
          2. 8.5.2.6.2Register 16h (address = 16h), JESD Analog Page (6A00h)
          3. 8.5.2.6.3Register 17h (address = 17h), JESD Analog Page (6A00h)
          4. 8.5.2.6.4Register 1Ah (address = 1Ah), JESD Analog Page (6A00h)
          5. 8.5.2.6.5Register 1Bh (address = 1Bh), JESD Analog Page (6A00h)
  9. Application and Implementation
    1. 9.1Application Information
      1. 9.1.1Start-Up Sequence
      2. 9.1.2Hardware Reset
      3. 9.1.3SNR and Clock Jitter
    2. 9.2Typical Application
      1. 9.2.1Design Requirements
        1. 9.2.1.1Transformer-Coupled Circuits
      2. 9.2.2Detailed Design Procedure
      3. 9.2.3Application Curves
  10. 10Power Supply Recommendations
    1. 10.1Power Sequencing and Initialization
  11. 11Layout
    1. 11.1Layout Guidelines
    2. 11.2Layout Example
  12. 12Device and Documentation Support
    1. 12.1Documentation Support
      1. 12.1.1Related Documentation
    2. 12.2Receiving Notification of Documentation Updates
    3. 12.3Community Resources
    4. 12.4Trademarks
    5. 12.5Electrostatic Discharge Caution
    6. 12.6Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Features

  • 16-Bit Resolution, Dual-Channel, 1-GSPS ADC
  • Noise Floor: –159 dBFS/Hz
  • Spectral Performance (fIN = 170 MHz at –1 dBFS):
    • SNR: 70 dBFS
    • NSD: –157 dBFS/Hz
    • SFDR: 86 dBc (Including Interleaving Tones)
    • SFDR: 89 dBc (Except HD2, HD3, and Interleaving Tones)
  • Spectral Performance (fIN = 350 MHz at –1 dBFS):
    • SNR: 67.5 dBFS
    • NSD: –154.5 dBFS/Hz
    • SFDR: 75 dBc
    • SFDR: 85 dBc (Except HD2, HD3, and Interleaving Tones)
  • Channel Isolation: 100 dBc at fIN = 170 MHz
  • Input Full-Scale: 1.9 VPP
  • Input Bandwidth (3 dB): 1.2 GHz
  • On-Chip Dither
  • Integrated Wideband DDC Block
  • JESD204B Interface with Subclass 1 Support:
    • 2 Lanes per ADC at 10.0 Gbps
    • 4 Lanes per ADC at 5.0 Gbps
    • Support for Multi-Chip Synchronization
  • Power Dissipation: 1.35 W/Ch at 1 GSPS
  • Package: 72-Pin VQFNP (10 mm × 10 mm)

Applications

  • Radar and Antenna Arrays
  • Broadband Wireless
  • Cable CMTS, DOCSIS 3.1 Receivers
  • Communications Test Equipment
  • Microwave Receivers
  • Software Defined Radio (SDR)
  • Digitizers
  • Medical Imaging and Diagnostics

Description

The ADS54J60 is a low-power, wide-bandwidth, 16-bit, 1.0-GSPS, dual-channel, analog-to-digital converter (ADC). Designed for high signal-to-noise ratio (SNR), the device delivers a noise floor of –159 dBFS/Hz for applications aiming for highest dynamic range over a wide instantaneous bandwidth. The device supports the JESD204B serial interface with data rates up to 10 Gbps, supporting two or four lanes per ADC. The buffered analog input provides uniform input impedance across a wide frequency range while minimizing sample-and-hold glitch energy. Each ADC channel optionally can be connected to a wideband digital down-converter (DDC) block. The ADS54J60 provides excellent spurious-free dynamic range (SFDR) over a large input frequency range with very low power consumption.

The JESD204B interface reduces the number of interface lines, allowing high system integration density. An internal phase-locked loop (PLL) multiplies the ADC sampling clock to derive the bit clock that is used to serialize the 16-bit data from each channel.

Device Information

PART NUMBERPACKAGEBODY SIZE (NOM)
ADS54J60VQFNP (72)10.00 mm × 10.00 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.

FFT for 170 MHz Input Signal
(SNR = 69.8 dBFS; SFDR = 88 dBc;
IL Spur = 86 dBc; Non HD2, HD3 Spur = 89 dBc)

ADS54J60 D003_SBAS706.gif

Revision History

Changes from B Revision (August 2015) to C Revision

  • Changed the SFDR value in the last sub-bullet of the Spectral Performance Features bulletGo
  • Changed Device Information tableGo
  • Added Device Comparison TableGo
  • Added CDM row to ESD Ratings tableGo
  • Changed the minimum value for the input clock frequency in the Recommended Operating Conditions table Go
  • Added minimum value to the ADC sampling rate parameter in the Electrical Characteristics tableGo
  • Added 720 MHz test condition rows to SNR, NSD, SINAD, SFDR, HD2, HD3, Non HD2, HD3, THD, and SFDR_IL parameters of AC Characteristics tableGo
  • Changed typical specification of SFDR parameter in AC Characteristics tableGo
  • Changed Sample Timing, Aperture jitter parameter typical specification in Timing Characteristics sectionGo
  • Added the FOVR latency parameter to the Timing Characteristics tableGo
  • Added Figure 10Go
  • Added Typical Characteristics: Contour sectionGo
  • Changed Overview section Go
  • Changed Functional Block Diagram section: changed Control and SPI block and added dashed outline to FOVR tracesGo
  • Added Figure 60 and text reference to Analog Inputs sectionGo
  • Changed SYSREF Signal section: changed Table 4 and added last paragraphGo
  • Added SYSREF Not Present (Subclass 0, 2) sectionGo
  • Changed the number of clock cycles in the Fast OVR sectionGo
  • Changed Table 10 and Table 11Go
  • Changed Table 12 and Table 13Go
  • Deleted Lane Enable with Decimation subsection Go
  • Added the Program Summary of DDC Modes and JESD Link Configuration tableGo
  • Added Figure 83 to Register Maps sectionGo
  • Changed Table 15Go
  • Deleted register 39h, 3Ah, and 56h Go
  • Changed Example Register Writes sectionGo
  • Updated register descriptions Go
  • Added Table 51Go
  • Deleted row for bit 1 in Table 60 as bit 1 is included in last table row Go
  • Changed Table 65Go
  • Changed internal aperture jitter value in SNR and Clock Jitter sectionGo
  • Changed Figure 132Go
  • Changed Power Supply Recommendations section Go
  • Added the Power Sequencing and Initialization sectionGo
  • Added Documentation Support and Receiving Notification of Documentation Updates sectionsGo

Changes from A Revision (May 2015) to B Revision

  • Released to production Go