ADS58J89 Quad 500MSPS Receiver and Feedback IC | TI.com

ADS58J89
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Quad 500MSPS Receiver and Feedback IC

 

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Description

The ADS58J89 is a high-linearity, quad-channel, 14-bit, 250/500-MSPS IF (intermediate frequency) receiver. The four channels contain 500MSPS 14-bit ADCs followed by signal processing for wireless infrastructure systems. The channels can be configured in various modes depending on bandwidth, resolution and sample time requirements. The signal processing block contains selectable modes for decimation filters, SNR Boost filters, resolution versus time and time-division duplex (TDD) burst mode. Designed for high antenna count systems, the 4 channels provides high bandwidth and linearity to multi-channel receivers in a small footprint. The device can be dual function as traffic receiver and power amplifier linearization feedback path in TDD systems.

Key Specifications:

  • Power Dissipation: 875 mW/ch
  • Input Bandwidth (3dB): 900 MHz
  • Aperture Jitter: 98 fs rms
  • Channel Isolation: 85 dB
  • Performance at in = 170 MHz at 1.25 Vpp,
    –1 dBFS
    • SNR: 65.8 dBFS
    • SFDR: 85 dBc HD2,3 95 dBFS non HD2,3

Features

  • 4-Ch, 14-Bit 500MSPS With Digital Signal Processing
  • Power Amplifier Linearization (Feedback) Modes
    • 14-Bits Every Other Sample at 250MSPS
    • Programmable Resolution vs Duty Cycle
      • Duty Cycle 3:2 (60% 11-Bit, 40% 9-Bit)
      • Duty Cycle 2:3 (40% 12-Bit, 60% 9-Bit)
      • Duty Cycle 1:3 (25% 14-Bit, 75% 9-Bit)
  • Traffic Receiver Modes
    • 14-Bit 250MSPS: Decimate by 2 Filter, High/Low Pass
    • 9-Bit SNR-Boost Filter (150-MHz Max Bandwidth)
    • 9-to-14-Bit TDD Burst (200-MHz Max Bandwidth)
  • Flexible Input Clock Buffer With Divide by 1/2/4
  • JESD204B Digital Interface up to 5.0Gbps
    • 1 or 2 Lanes per Channel, With Subclass 1
  • 64-Pin VQFN Package (9 × 9 mm)

Parametrics

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Part number Order Number of input channels Resolution (Bits) Sample rate (Max) (MSPS) Features Analog input BW (MHz) SFDR (Typ) (dB) SNR (Typ) (dB) Power consumption (Typ) (mW) Logic voltage DV/DD (Max) (V) Logic voltage DV/DD (Min) (V) Analog voltage AVDD (Max) (V) Analog voltage AVDD (Min) (V) Operating temperature range (C)
ADS58J89 Order now 4     14     500     Decimating Filter
Differential Inputs
High Dynamic Range
Nap Mode
Out of Range Indicator
Power Down    
900     85     65.8     3270     1.9     1.7     2     1.8     -40 to 85    
ADS58H40 Samples not available 4     14     250     Decimating Filter
Differential Inputs
High Dynamic Range
Nap Mode
Out of Range Indicator
Power Down    
500     85     71     1460     2     1.7     3.45     1.8     -40 to 85    
ADS58H43 Samples not available 4     14     250     Decimating Filter
Differential Inputs
High Dynamic Range
Nap Mode
Out of Range Indicator
Power Down    
500     85     70.5     1460     2     1.7     3.45     1.8     -40 to 85