8.3.1 Analog Input

The device supports a unipolar, single-ended analog input signal. Figure 36 shows a small-signal equivalent circuit of the sample-and-hold circuit. The sampling switch is represented by a resistance (R_S1 and R_S2, typically 50 Ω) in series with an ideal switch (SW₁ and SW₂). The sampling capacitors, C_S1 and C_S2, are typically 16 pF.

Figure 36. Equivalent Input Circuit for the Sampling Stage

During the acquisition process, both positive and negative inputs are individually sampled on C_S1 and C_S2, respectively. During the conversion process, the device converts for the voltage difference between the two sampled values: V_AINP – V_AINM.

Each analog input pin has electrostatic discharge (ESD) protection diodes to AVDD and GND. Keep the analog inputs within the specified range to avoid turning the diodes on.

The full-scale analog input range (FSR) is 0 V to AVDD and the absolute input range on the AINM and AINP pins is –0.1 V to AVDD + 0.1 V.

8.3.2 Reference

The device uses the analog supply voltage (AVDD) as the reference voltage for the analog-to-digital conversion. During the conversion process, the internal capacitors are switched to the AVDD pin as per the successive approximation algorithm. As shown in Figure 37, a 3.3-µF (C_AVDD), low equivalent series resistance (ESR) ceramic capacitor is recommended to be placed between the AVDD and GND pins. The decoupling capacitor provides the instantaneous charge required by the internal circuit during the conversion process and maintains a stable dc voltage on the AVDD pin.

See the Power Supply Recommendations and Layout Example sections for component recommendations and layout guidelines.

Figure 37. Reference for the Device

8.3.3 ADC Transfer Function

The device supports a unipolar, single-ended analog input signal. The output is in straight binary format. Figure 38 and Table 1 show the ideal transfer characteristics for the device.

The least significant bit for the device is given by:

Figure 38. Ideal Transfer Characteristics

8.4.1 ACQ State

In ACQ state, switches SW₁ and SW₂ connected to the analog input pins close and the device acquires the analog input signal on C_S1 and C_S2. The device enters ACQ state at power-up, at the end of every conversion, and after completing the offset calibration. A CS falling edge takes the device from ACQ state to CNV state.

The device consumes extremely low power from the AVDD and DVDD power supplies when in ACQ state.

8.4.2 CNV State

In the CNV state, the device uses the external clock to convert the sampled analog input signal to an equivalent digital code as per the transfer function illustrated in Figure 38. The conversion process requires a minimum of 18 SCLK falling edges to be provided within the frame. After the end of conversion process, the device automatically moves from CNV state to ACQ state. For acquisition of the next sample, a minimum time of t_ACQ must be provided.

Figure 40 shows a detailed timing diagram for the serial interface. In the first serial transfer frame after power-up, the device provides the first data as all zeros. In any frame, the clocks provided on the SCLK pin are also used to transfer the output data for the previous conversion. A leading 0 is output on the SDO pin on the CS falling edge. The most significant bit (MSB) of the output data is launched on the SDO pin on the rising edge after the first SCLK falling edge. Subsequent output bits are launched on the subsequent rising edges provided on SCLK. When all 14 output bits are shifted out, the device outputs 0's on the subsequent SCLK rising edges. The device enters ACQ state after 18 clocks and a minimum time of t_ACQ must be provided for acquiring the next sample. If the device is provided with less than 18 SCLK falling edges in the present serial transfer frame, the device provides an invalid conversion result in the next serial transfer frame.

Figure 40. Serial Interface Timing Diagram

8.4.3 OFFCAL State

In OFFCAL state, the device calibrates and corrects for its internal offset errors. In OFFCAL state, the sampling capacitors are disconnected from the analog input pins (AINP and AINM). The offset calibration is effective for all subsequent conversions until the device is powered off. An offset calibration cycle is recommended at power-up and whenever there is a significant change in the operating conditions for the device (such as in the AVDD voltage and operating temperature).

The host controller must provide a serial transfer frame as described in Figure 41 or in Figure 42 to enter OFFCAL state.

8.4.3.1 Offset Calibration on Power-Up

On power-up, the host must provide 24 SCLKs in the first serial transfer to enter the OFFCAL state. The device provides 0's on SDO during offset calibration. For acquisition of the next sample, a minimum time of t_ACQ must be provided. If the host controller enters the OFFCAL state, but pulls the CS pin high before providing 24 SCLKs, then the offset calibration process is aborted and the device enters the ACQ state. Figure 41 and Table 2 provide the timing for offset calibration on power-up.

Figure 41. Timing for Offset Calibration on Power-Up

Table 2. Timing Specifications for Offset Calibration on Power-Up⁽¹⁾

		MIN	TYP	MAX	UNIT
tcycle	Cycle time for offset calibration on power-up	24 × tCLK + tACQ			ns
tACQ	Acquisition time	95			ns
fSCLK	Frequency of SCLK			60	MHz

(1) In addition to the timing specifications of Figure 41 and Table 2, the timing specifications described in Figure 2 and the Timing Requirements table are also applicable for offset calibration on power-up.

8.4.3.2 Offset Calibration During Normal Operation

During normal operation, the host must provide 64 SCLKs in the serial transfer frame to enter the OFFCAL state. The device provides the conversion result for the previous sample during the first 18 SCLKs and 0's on SDO for the rest of the SCLKs in the serial transfer frame. For acquisition of the next sample, a minimum time of t_ACQ must be provided. If the host controller enters the OFFCAL state, but pulls the CS high before providing 64 SCLKs, then the offset calibration process is aborted and the device enters ACQ state. Figure 42 and Table 3 provide the timing for offset calibration during normal operation.

Figure 42. Timing for Offset Calibration During Normal Operation

Table 3. Timing Specifications for Offset Calibration During Normal Operation⁽¹⁾

		MIN	TYP	MAX	UNIT
tcycle	Cycle time for offset calibration on power-up	64 × tCLK + tACQ			ns
tACQ	Acquisition time	95			ns
fSCLK	Frequency of SCLK			60	MHz

(1) In addition to the timing specifications of Figure 42 and Table 3, the timing specifications described in Figure 2 and the Timing Requirements table are also applicable for offset calibration during normal operation.