ADS808 (ACTIVE)

12-Bit, 70-MSPS Analog-to-Digital Converter (ADC)

12-Bit, 70-MSPS Analog-to-Digital Converter (ADC) - ADS808
 

Recommended alternative parts

  • ADS4122  -  Up to 65MSPS and 87% power reduction at 70MSPS

Description

The ADS808 is a high-dynamic range, 12-bit, 70MHz, pipelined Analog-to-Digital Converter (ADC). It includes a high-bandwidth linear track-and-hold that has a low jitter of only 0.25ps rms, leading to excellent SNR performance. The clock input can accept a low-level differential sine wave or square wave signal down to 0.5Vp-p, further improving the SNR performance. It also accepts a single-ended clock signal and has flexible threshold levels.

The ADS808 has a 2Vp-p differential input range (1Vp-p • 2 inputs) for optimum signal-to-noise ratio. The differential operation gives the lowest even-order harmonic components. A lower input voltage of 1.5Vp-p or 1Vp-p can also be selected using the internal references, further optimizing SFDR. Alternatively, a single-ended input range can be used by tying the IN\ input to the common-mode voltage, if desired.

The ADS808 also provides an over-range flag that indicates when the input signal has exceeded the converter’s full-scale range. This flag can also be used to reduce the gain of the front-end signal conditioning circuitry. It also employs digital error-correction techniques to provide excellent differential linearity for demanding imaging applications. The ADS808 is available in a small TQFP-48 PowerPAD™ thermally enhanced package.

Features

  • DYNAMIC RANGE:
        SNR: 64dB at 10MHz fIN
        SFDR: 68dB at 10MHz fIN
  • PREMIUM TRACK-AND-HOLD:
       Low Jitter: 0.25ps rms
       Differential or Single-Ended Inputs
       Selectable Full-Scale Input Range
  • FLEXIBLE CLOCKING:
       Differential or Single-Ended
       Accepts Sine or Square Wave Clocking
       Down to 0.5Vp-p
       Variable Threshold Level
  • APPLICATIONS
    • BASESTATION WIDEBAND RADIOS:
         CDMA, GSM, TDMA, 3G, AMPS, and NMT
    • TEST INSTRUMENTATION
    • CCD IMAGING

PowerPAD is a registered trademark of Texas Instruments.

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Parametrics Compare all products in High Speed ADCs (>10MSPS)

 
Resolution (Bits)
Sample Rate (Max) (MSPS)
# Input Channels
SNR (dB)
ENOB (Bits)
SFDR (dB)
Power Consumption (Typ) (mW)
Input Range (Vp-p)
Interface
Operating Temperature Range (C)
Analog Input BW (MHz)
Input Buffer
Package Group
Package Size: mm2:W x L (PKG)
Rating
SINAD (dB)
Architecture
DNL (Typ) (+/-LSB)
INL (Typ) (+/-LSB)
Reference Mode
ADS808
12   
70   
1   
64   
10.3   
68   
720   
1
2   
Parallel CMOS   
-40 to 85   
1000   
No   
HTQFP   
48HTQFP: 81 mm2: 9 x 9(HTQFP)   
Catalog   
64   
Pipeline   
0.7   
4   
Ext
Int