SBAS707B June 2016  – January 2018 ADS8910B , ADS8912B , ADS8914B

PRODUCTION DATA. 

  1. 1     Features
  2. 2     Applications
  3. 3     Description
  4. DeviceImages
    1. Easeof System Design With ADS89xxB Integrated Features
  5. 4     Revision History
  6. 5     Pin Configuration and Functions
    1. PinFunctions
  7. 6     Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2ESD Ratings
    3. 6.3Recommended Operating Conditions
    4. 6.4Thermal Information
    5. 6.5Electrical Characteristics
    6. 6.6Timing Requirements
    7. 6.7Switching Characteristics
    8. 6.8Typical Characteristics
  8. 7     Detailed Description
    1. 7.1Overview
    2. 7.2Functional Block Diagram
    3. 7.3Feature Description
      1. 7.3.1LDO Module
      2. 7.3.2Reference Buffer Module
      3. 7.3.3Converter Module
        1. 7.3.3.1Sample-and-Hold Circuit
        2. 7.3.3.2Internal Oscillator
        3. 7.3.3.3ADC Transfer Function
      4. 7.3.4Interface Module
    4. 7.4Device Functional Modes
      1. 7.4.1RST State
      2. 7.4.2ACQ State
      3. 7.4.3CNV State
    5. 7.5Programming
      1. 7.5.1Output Data Word
      2. 7.5.2Data Transfer Frame
      3. 7.5.3Interleaving Conversion Cycles and Data Transfer Frames
      4. 7.5.4Data Transfer Protocols
        1. 7.5.4.1Protocols for Configuring the Device
        2. 7.5.4.2Protocols for Reading From the Device
          1. 7.5.4.2.1Legacy, SPI-Compatible (SYS-xy-S) Protocols
          2. 7.5.4.2.2SPI-Compatible Protocols with Bus Width Options
          3. 7.5.4.2.3Source-Synchronous (SRC) Protocols
            1. 7.5.4.2.3.1Output Clock Source Options with SRC Protocols
            2. 7.5.4.2.3.2Bus Width Options With SRC Protocols
            3. 7.5.4.2.3.3Output Data Rate Options With SRC Protocols
      5. 7.5.5Device Setup
        1. 7.5.5.1Single Device: All multiSPI Options
        2. 7.5.5.2Single Device: Minimum Pins for a Standard SPI Interface
        3. 7.5.5.3Multiple Devices: Daisy-Chain Topology
        4. 7.5.5.4Multiple Devices: Star Topology
    6. 7.6Register Maps
      1. 7.6.1Device Configuration and Register Maps
        1. 7.6.1.1PD_CNTL Register (address = 04h) [reset = 00h]
          1. Table11. PD_CNTL Register Field Descriptions
        2. 7.6.1.2SDI_CNTL Register (address = 008h) [reset = 00h]
          1. Table12. SDI_CNTL Register Field Descriptions
        3. 7.6.1.3SDO_CNTL Register (address = 0Ch) [reset = 00h]
          1. Table13. SDO_CNTL Register Field Descriptions
        4. 7.6.1.4DATA_CNTL Register (address = 010h) [reset = 00h]
          1. Table14. DATA_CNTL Register Field Descriptions
        5. 7.6.1.5PATN_LSB Register (address = 014h) [reset = 00h]
          1. Table15. PATN_LSB Register Field Descriptions
        6. 7.6.1.6PATN_MID Register (address = 015h) [reset = 00h]
          1. Table16. PATN_MID Register Field Descriptions
        7. 7.6.1.7PATN_MSB Register (address = 016h) [reset = 00h]
          1. Table17. PATN_MSB Register Field Descriptions
        8. 7.6.1.8OFST_CAL Register (address = 020h) [reset = 00h]
          1. Table18. OFST_CAL Register Field Descriptions
        9. 7.6.1.9REF_MRG Register (address = 030h) [reset = 00h]
          1. Table19. REF_MRG Register Field Descriptions
  9. 8     Application and Implementation
    1. 8.1Application Information
      1. 8.1.1ADC Reference Driver
      2. 8.1.2ADC Input Driver
        1. 8.1.2.1Charge-Kickback Filter
        2. 8.1.2.2Input Amplifier Selection
    2. 8.2Typical Application
      1. 8.2.1Data Acquisition (DAQ) Circuit for Lowest Distortion and Noise Performance With Differential Input
        1. 8.2.1.1Design Requirements
        2. 8.2.1.2Detailed Design Procedure
        3. 8.2.1.3Application Curves
      2. 8.2.2DAQ Circuit With FDA Input Driver and Single-Ended or Differential Input
      3. 8.2.3Design Requirements
      4. 8.2.4Detailed Design Procedure
      5. 8.2.5Application Curves
  10. 9     Power-Supply Recommendations
  11. 10    Layout
    1. 10.1Layout Guidelines
      1. 10.1.1Signal Path
      2. 10.1.2Grounding and PCB Stack-Up
      3. 10.1.3Decoupling of Power Supplies
      4. 10.1.4Reference Decoupling
      5. 10.1.5Differential Input Decoupling
    2. 10.2Layout Example
  12. 11    Device and Documentation Support
    1. 11.1Documentation Support
      1. 11.1.1Related Documentation
    2. 11.2Related Links
    3. 11.3Receiving Notification of Documentation Updates
    4. 11.4Community Resources
    5. 11.5Trademarks
    6. 11.6Electrostatic Discharge Caution
    7. 11.7Glossary
  13. 12    Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Orderable Information

Features

  • Resolution: 18-Bits
  • High Sample Rate With No Latency Output:
    • ADS8910B: 1-MSPS
    • ADS8912B: 500-kSPS
    • ADS8914B: 250-kSPS
  • Integrated LDO Enables Single-Supply Operation
  • Low-Power Reference Buffer With No Droop
  • Excellent AC and DC Performance:
    • SNR: 102.5-dB, THD: –125-dB
    • INL: ±0.5-LSB
    • DNL: ±0.2-LSB, 18-Bit No-Missing-Codes
  • Wide Input Range:
    • Unipolar Differential Input Range: ±VREF
    • VREF Input Range: 2.5-V to 5-V
  • Single-Supply, Low-Power Operation
    (Includes Internal Reference Buffer and LDO)
    • ADS8910B : 21-mW at 1-MSPS
    • ADS8912B : 16-mW at 500-kSPS
    • ADS8914B : 14-mW at 250-kSPS
  • Enhanced-SPI Digital Interface
    • Interface SCLK: 20-MHz at 1-MSPS
    • Configurable Data Parity Output
  • Extended Temperature Range: –40°C to +125°C
  • Small Footprint: 4-mm × 4-mm VQFN