SLASET0A October   2018  – January 2019 AFE7444

PRODUCTION DATA.  

  1. 1Features
  2. 2Applications
  3. 3Description
    1.     Functional Block Diagram
  4. 4Revision History
  5. 5Device and Documentation Support
    1. 5.1 Receiving Notification of Documentation Updates
    2. 5.2 Community Resources
    3. 5.3 Trademarks
    4. 5.4 Electrostatic Discharge Caution
    5. 5.5 Glossary
  6. 6Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

1 Features

  • Four, 14-bit, 9-GSPS DACs
    • Up to 800-MHz signal bandwidth
    • 1 DSA per channel tunes output power
  • Four, 14-Bit, 3-GSPS ADCs
    • Up to 800-MHz signal bandwidth
    • NSD: –151 dBFS/Hz
    • AC performance at fIN = 2.6 GHz, –3 dBFS
      • SNR: 55 dBFS
      • SFDR: 73 dBc HD2 and HD3
      • SFDR: 91 dBc worst spur
    • 2 DSA per channel extends dynamic range
    • RF and digital power detectors
  • RF frequency range: 10 MHz to 6 GHz
  • Fast frequency hopping < 1 µs
  • Receive digital signal path:
    • dual DDC per ADC
    • 3-phase coherent 32-bit NCOs per DDC
    • Decimation ratio: 3x to 32x
  • Transmit digital signal path:
    • Dual DUC per DAC with 32-bit NCOs
    • Interpolation ratio: 8x to 36x
    • Sin(x)/x correction and configurable delay
    • Power amplifier protection (PAP)
  • JESD204B interface:
    • 8 transceivers at up to 15 Gbps
    • Subclass 1 multichip synchronization
  • Clocks:
    • Internal PLL and VCO with bypass option
    • Clock output up to 3 GHz with clock divider
  • DAC power dissipation: 1.7 W/ch at 9 GSPS
  • ADC power dissipation: 1.8 W/ch at 3 GSPS
  • Package: 17-mm x 17-mm FC BGA, 0.8-mm pitch