The analog input stage of the AMC1303 is a fully differential amplifier feeding the switched-capacitor input of a second-order, delta-sigma (ΔΣ) modulator stage that digitizes the input signal into a 1-bit output stream. The isolated data output DOUT of the converter provides a stream of digital ones and zeros that is synchronous to the internally-generated clock at the CLKOUT pin (active on AMC1303Mx derivates only) with a frequency as specified in the Switching Characteristics table. The time average of this serial bit-stream output is proportional to the analog input voltage.
The Functional Block Diagram section shows a detailed block diagram of the AMC1303. The analog input range is tailored to directly accommodate a voltage drop across a shunt resistor used for current sensing. The SiO2-based capacitive isolation barrier supports a high level of magnetic field immunity as described in the application report ISO72x Digital Isolator Magnetic-Field Immunity (SLLA181A), available for download at www.ti.com. The extended clock frequency of 20 MHz on the AMC1303xxx20 supports faster control loops and higher performance levels compared to the other solutions available on the market.
The AMC1303 incorporates a front-end circuitry that contains a differential amplifier and sampling stage, followed by a ΔΣ modulator. The gain of the differential amplifier is set by internal precision resistors to a factor of 4 for devices with a specified input voltage range of ±250 mV (for the AMC1303x25x), or to a factor of 20 in devices with a ±50-mV input voltage range (for the AMC1303x05x), resulting in a differential input resistance of 4.9 kΩ (for the AMC1303x05x) or 22 kΩ (for the AMC1303x25x).
For reduced offset and offset drift, the differential amplifier is chopper-stabilized with the switching frequency set at fCLK / 32. Figure 42 shows that the switching frequency generates a spur.
|AMC1303xxx20, sinc3 filter, OSR = 2, fIN = 1 kHz|
Consider the input resistance of the AMC1303 in designs with high-impedance signal sources that can cause degradation of gain and offset specifications. The importance of this effect, however, depends on the desired system performance. Additionally, the input bias current caused by the internal common-mode voltage at the output of the differential amplifier causes an offset that is dependent on the actual amplitude of the input signal. See the Isolated Voltage Sensing section for more details on reducing these effects.
There are two restrictions on the analog input signals (AINP and AINN). First, if the input voltage exceeds the range AGND – 6 V to AVDD + 0.5 V, the input current must be limited to 10 mA because the device input electrostatic discharge (ESD) diodes turn on. In addition, the linearity and noise performance of the device are ensured only when the differential analog input voltage remains within the specified linear full-scale range (FSR), that is ±250 mV (for the AMC1303x25x) or ±50 mV (for the AMC1303x05x), and within the specified input common-mode voltage range.
The modulator implemented in the AMC1303 (such as the one conceptualized in Figure 43) is a second-order, switched-capacitor, feed-forward ΔΣ modulator. The analog input voltage VIN and the output V5 of the 1-bit digital-to-analog converter (DAC) are subtracted, providing an analog voltage V1 at the input of the first integrator stage. The output of the first integrator feeds the input of the second integrator stage, resulting in output voltage V3 that is subtracted from the input signal VIN and the output of the first integrator V2. Depending on the polarity of the resulting voltage V4, the output of the comparator is changed. In this case, the 1-bit DAC responds on the next clock pulse by changing its analog output voltage V5, causing the integrators to progress in the opposite direction and forcing the value of the integrator output to track the average value of the input.
The modulator shifts the quantization noise to high frequencies; see Figure 42. Therefore, use a low-pass digital filter at the output of the device to increase the overall performance. This filter is also used to convert the 1-bit data stream at a high sampling rate into a higher-bit data word at a lower rate (decimation). TI's microcontroller families TMS320F2807x and TMS320F2837x offer a suitable programmable, hardwired filter structure called a sigma-delta filter module (SDFM) optimized for usage with the AMC1303 family. Also, SD24_B converters on the MSP430F677x microcontrollers offer a path to directly access the integrated sinc-filters, thus offering a system-level solution for multichannel, isolated current sensing. An additional option is to use a suitable application-specific device, such as the AMC1210 (a four-channel digital sinc-filter). Alternatively, a field-programmable gate array (FPGA) can be used to implement the filter.
The AMC1303 uses an on-off keying (OOK) modulation scheme to transmit the modulator output bitstream across the capacitive SiO2-based isolation barrier. The transmitter modulates the bitstream at TX IN in Figure 44 with an internally-generated, 480-MHz carrier across the isolation barrier to represent a digital zero and sends a no signal to represent the digital one. The receiver demodulates the signal after advanced signal conditioning and produces the output. The symmetrical design of each isolation channel improves the CMTI performance and reduces the radiated emissions caused by the high-frequency carrier. Figure 44 shows a block diagram of an isolation channel integrated in the AMC1303.
Figure 45 shows the concept of the on-off keying scheme.
A differential input signal of 0 V ideally produces a stream of ones and zeros that are high 50% of the time. A differential input of 250 mV (for the AMC1303x25x) or 50 mV (for the AMC1303x05x) produces a stream of ones and zeros that are high 89.06% of the time. With 16 bits of resolution on the decimation filter, that percentage ideally corresponds to code 58368. A differential input of –250 mV (–50 mV for the AMC1303x05x) produces a stream of ones and zeros that are high 10.94% of the time and ideally results in code 7168 with a 16-bit resolution decimation filter. These input voltages are also the specified linear ranges of the different AMC1303 versions with performance as specified in this document. If the input voltage value exceeds these ranges, the output of the modulator shows nonlinear behavior where the quantization noise increases. The output of the modulator clips with a stream of only zeros with an input less than or equal to –320 mV (–64 mV for the AMC1303x05x) or with a stream of only ones with an input greater than or equal to 320 mV (64 mV for the AMC1303x05x). In this case, however, the AMC1303 generates a single 1 (if the input is at negative full-scale) or 0 every 128 clock cycles to indicate proper device function (see the Fail-Safe Output section for more details). Figure 46 shows the input voltage versus the output modulator signal.
Equation 1 calculates the density of ones in the output bit-stream for any input voltage value (with the exception of a full-scale input signal, as described in the Output Behavior in Case of a Full-Scale Input section):
The AMC1303 internally generates the clock signal required for the modulator. This clock is provided externally at the CLKOUT pin on AMC1303Mx devices only. For more details, see the Switching Characteristics section.
The AMC1303Ex offers the IEEE 802.3-compliant Manchester coding feature that generates at least one transition per bit to support clock signal recovery from the bitstream. A Manchester coded bitstream is free of dc components. The Manchester coding combines the clock and data information using exclusive or (XOR) logical operation. Figure 47 shows the resulting bitstream.
In the case of a missing high-side supply voltage AVDD, the output of the ΔΣ modulator is not defined and can cause a system malfunction. In systems with high safety requirements, this behavior is not acceptable. Therefore, as shown in Figure 2, the AMC1303 implements a fail-safe output function that pulls the DOUT and CLKOUT outputs (AMC1303Mx only) to a steady-state logic 1 in case of a missing AVDD.
Similarly, as also shown in Figure 48, if the common-mode voltage of the input reaches or exceeds the specified common-mode overvoltage detection level VCMov as defined in the Electrical Characteristics table, the AMC1303 generates a steady-state bitstream of logic 1's at the DOUT output.
In both cases, the steady-state logic 1 occurs on the DOUT output with a delay of two clock cycles after the event of either exceeded common-mode input voltage or missing AVDD. Another 256 clock cycles are required for the CLKOUT pin of the AMC1303Mx to be held at logic 1.
If a full-scale input signal is applied to the AMC1303 (that is, |VIN| ≥ |VClipping|), Figure 49 shows that the device generates a single one or zero every 128 bits at DOUT, depending on the actual polarity of the signal being sensed. In this way, differentiating between a missing AVDD and a full-scale input signal is possible on the system level.