SBAS734A March 2017  – July 2017 AMC1306E05 , AMC1306E25 , AMC1306M05 , AMC1306M25

PRODUCTION DATA. 

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Power Ratings
    6. 7.6 Insulation Specifications
    7. 7.7 Safety-Related Certifications
    8. 7.8 Safety Limiting Values
    9. 7.9 Electrical Characteristics: AMC1306x05
    10. 7.10Electrical Characteristics: AMC1306x25
    11. 7.11Switching Characteristics
    12. 7.12Insulation Characteristics Curves
    13. 7.13Typical Characteristics
  8. Detailed Description
    1. 8.1Overview
    2. 8.2Functional Block Diagram
    3. 8.3Feature Description
      1. 8.3.1Analog Input
      2. 8.3.2Modulator
      3. 8.3.3Isolation Channel Signal Transmission
      4. 8.3.4Digital Output
      5. 8.3.5Manchester Coding Feature
    4. 8.4Device Functional Modes
      1. 8.4.1Fail-Safe Output
      2. 8.4.2Output Behavior in Case of a Full-Scale Input
  9. Application and Implementation
    1. 9.1Application Information
      1. 9.1.1Digital Filter Usage
    2. 9.2Typical Applications
      1. 9.2.1Frequency Inverter Application
        1. 9.2.1.1Design Requirements
        2. 9.2.1.2Detailed Design Procedure
        3. 9.2.1.3Application Curve
      2. 9.2.2Isolated Voltage Sensing
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2Detailed Design Procedure
        3. 9.2.2.3Application Curve
      3. 9.2.3Do's and Don'ts
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1Layout Guidelines
    2. 11.2Layout Example
  12. 12Device and Documentation Support
    1. 12.1Device Support
      1. 12.1.1Device Nomenclature
        1. 12.1.1.1Isolation Glossary
    2. 12.2Documentation Support
      1. 12.2.1Related Documentation
    3. 12.3Related Links
    4. 12.4Receiving Notification of Documentation Updates
    5. 12.5Community Resources
    6. 12.6Trademarks
    7. 12.7Electrostatic Discharge Caution
    8. 12.8Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Specifications

Absolute Maximum Ratings(1)

MINMAXUNIT
Supply voltageAVDD to AGND or DVDD to DGND–0.36.5V
Analog input voltage at AINP, AINN AGND – 6 AVDD + 0.5V
Digital input or output voltage at CLKIN or DOUTDGND – 0.5DVDD + 0.5V
Input current to any pin except supply pins–1010mA
Junction temperature, TJ 150°C
Storage temperature, Tstg –65150°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

ESD Ratings

VALUEUNIT
V(ESD)Electrostatic dischargeHuman-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)±2000V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)±1000
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

Recommended Operating Conditions

over operating ambient temperature range (unless otherwise noted)
MINNOMMAXUNIT
AVDDAnalog (high-side) supply voltage (AVDD to AGND)3.05.05.5 V
DVDDDigital (controller-side) supply voltage (DVDD to DGND)2.73.35.5V
TA Operating ambient temperature–40 125 °C

Thermal Information

THERMAL METRIC (1) AMC1306xUNIT
DWV (SOIC)
8 PINS
RθJA Junction-to-ambient thermal resistance 112.2°C/W
RθJC(top) Junction-to-case (top) thermal resistance 47.6°C/W
RθJB Junction-to-board thermal resistance 60.0°C/W
ψJT Junction-to-top characterization parameter 23.1°C/W
ψJB Junction-to-board characterization parameter 60.0°C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance n/a°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

Power Ratings

PARAMETERTEST CONDITIONSMINTYPMAXUNIT
PDMaximum power dissipation
(both sides)
AMC1306Ex, AVDD = DVDD = 5.5 V91.85mW
AMC1306Mx, AVDD = DVDD = 5.5 V86.90
PD1Maximum power dissipation
(high-side supply)
AVDD = 5.5 V53.90mW
PD2Maximum power dissipation
(low-side supply)
AMC1306Ex, DVDD = 5.5 V37.95mW
AMC1306Mx, DVDD = 5.5 V33.00

Insulation Specifications

over operating ambient temperature range (unless otherwise noted)
PARAMETERTEST CONDITIONSVALUEUNIT
GENERAL
CLRExternal clearance(1)Shortest pin-to-pin distance through air≥ 9mm
CPGExternal creepage(1)Shortest pin-to-pin distance across the package surface≥ 9mm
DTIDistance through insulationMinimum internal gap (internal clearance) of the double insulation (2 × 0.0105 mm)≥ 0.021mm
CTIComparative tracking indexDIN EN 60112 (VDE 0303-11); IEC 60112≥ 600V
Material groupAccording to IEC 60664-1I
Overvoltage category per IEC 60664-1Rated mains voltage ≤ 300 VRMSI-IV
Rated mains voltage ≤ 600 VRMSI-IV
Rated mains voltage ≤ 1000 VRMSI-III
DIN V VDE V 0884-11 (VDE V 0884-11): 2017-01(2)
VIORM Maximum repetitive peak isolation voltageAt ac voltage (bipolar)2121VPK
VIOWM Maximum-rated isolation working voltageAt ac voltage (sine wave)1500VRMS
At dc voltage2121VDC
VIOTM Maximum transient isolation voltageVTEST = VIOTM, t = 60 s (qualification test)7000VPK
VTEST = 1.2 × VIOTM, t = 1 s (100% production test)8400
VIOSM Maximum surge isolation voltage(3)Test method per IEC 60065, 1.2/50-μs waveform,
VTEST = 1.6 × VIOSM = 12800 VPK (qualification)
8000VPK
qpd Apparent charge(4)Method a, after input/output safety test subgroup 2/3,
Vini = VIOTM, tini = 60 s,
Vpd(m) = 1.2 × VIORM = 2545 VPK, tm = 10 s
≤ 5pC
Method a, after environmental tests subgroup 1,
Vini = VIOTM, tini = 60 s,
Vpd(m) = 1.6 × VIORM = 3394 VPK, tm = 10 s
≤ 5
Method b1, at routine test (100% production) and preconditioning (type test), Vini = VIOTM, tini = 1 s,
Vpd(m) = 1.875 × VIORM = 3977 VPK, tm = 1 s
≤ 5
CIO Barrier capacitance, input to output(5)VIO = 0.5 VPP at 1 MHz~1pF
RIO Insulation resistance, input to output(5)VIO = 500 V at TA = 25°C> 1012 Ω
VIO = 500 V at 100°C ≤ TA ≤ 125°C> 1011
VIO = 500 V at TS = 150°C> 109
Pollution degree2
Climatic category40/125/21
UL1577
VISO Withstand isolation voltageVTEST = VISO = 5000 VRMS or 7000 VDC, t = 60 s (qualification), VTEST = 1.2 × VISO = 6000 VRMS, t = 1 s (100% production test)5000VRMS
Apply creepage and clearance requirements according to the specific equipment isolation standards of an application. Care must be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed circuit board (PCB) do not reduce this distance. Creepage and clearance on a PCB become equal in certain cases. Techniques such as inserting grooves and ribs on the PCB are used to help increase these specifications.
This coupler is suitable for safe electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured by means of suitable protective circuits.
Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.
Apparent charge is electrical discharge caused by a partial discharge (pd).
All pins on each side of the barrier are tied together, creating a two-pin device.

Safety-Related Certifications

VDEUL
Certified according to DIN V VDE V 0884-11 (VDE V 0884-11): 2017-01,
DIN EN 60950-1 (VDE 0805 Teil 1): 2014-08,
and DIN EN 60065 (VDE 0860): 2005-11
Recognized under 1577 component recognition and
CSA component acceptance NO 5 programs
Reinforced insulation Single protection
File number: DIN 40040142 File number: E181974

Safety Limiting Values

Safety limiting intends to minimize potential damage to the isolation barrier upon failure of input or output (I/O) circuitry. A failure of the I/O may allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to overheat the die and damage the isolation barrier, potentially leading to secondary system failures.
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
IS Safety input, output, or supply currentθJA = 112.2°C/W, AVDD = DVDD = 5.5 V,
TJ = 150°C, TA = 25°C
202.5mA
θJA = 112.2°C/W, AVDD = DVDD = 3.6 V,
TJ = 150°C, TA = 25°C
309.4
PS Safety input, output, or total powerθJA = 112.2°C/W, TJ = 150°C, TA = 25°C1114(1)mW
TS Maximum safety temperature150°C
Input, output, or the sum of input and output power must not exceed this value.

The maximum safety temperature is the maximum junction temperature specified for the device. The power dissipation and junction-to-air thermal impedance of the device installed in the application hardware determines the junction temperature. The assumed junction-to-air thermal resistance in the Thermal Information table is that of a device installed on a high-K test board for leaded surface-mount packages. The power is the recommended maximum input voltage times the current. The junction temperature is then the ambient temperature plus the power times the junction-to-air thermal resistance.

Electrical Characteristics: AMC1306x05

minimum and maximum specifications apply from TA = –40°C to +125°C, AVDD = 3.0 V to 5.5 V, DVDD = 2.7 V to 5.5 V, AINP = –50 mV to 50 mV, AINN = AGND, and sinc3 filter with OSR = 256 (unless otherwise noted); typical specifications are at TA = 25°C, CLKIN = 20 MHz, AVDD = 5 V, and DVDD = 3.3 V
PARAMETERTEST CONDITIONSMINTYP MAXUNIT
ANALOG INPUTS
VClipping Differential input voltage before clipping outputVIN = AINP – AINN±64mV
FSRSpecified linear differential full-scaleVIN = AINP – AINN–5050mV
Absolute common-mode input voltage(1)(AINP + AINN) / 2 to AGND–2AVDDV
VCM Operating common-mode input voltage(AINP + AINN) / 2 to AGND–0.032AVDD – 2.1V
VCMov Common-mode overvoltage detection level(2)(AINP + AINN) / 2 to AGNDAVDD - 2V
CIN Single-ended input capacitanceAINN = AGND4pF
CIND Differential input capacitance2pF
IIB Input bias currentAINP = AINN = AGND, IIB = IIBP + IIBN–97–72–57μA
RIN Single-ended input resistanceAINN = AGND4.75
RIND Differential input resistance4.9
IIO Input offset current±10nA
CMTICommon-mode transient immunity50100kV/μs
CMRRCommon-mode rejection ratioAINP = AINN, fIN = 0 Hz,
VCM min ≤ VIN ≤ VCM max
–99dB
AINP = AINN, fIN from 0.1 Hz to 50 kHz,
VCM min ≤ VIN ≤ VCM max
–98
BWInput bandwidth(3)800kHz
DC ACCURACY
DNLDifferential nonlinearityResolution: 16 bits–0.990.99LSB
INLIntegral nonlinearity(4) Resolution: 16 bits, 4.5 V ≤ AVDD ≤ 5.5 V–4±14LSB
Resolution: 16 bits, 3.0 V ≤ AVDD ≤ 3.6 V–5±1.55
EO Offset error Initial, at 25°C, AINP = AINN = AGND–50±2.550µV
TCEO Offset error thermal drift(5) –1±0.251μV/°C
EG Gain errorInitial, at 25°C–0.2%±0.005%0.2%
TCEG Gain error thermal drift(6) –40±2040ppm/°C
PSRRPower-supply rejection ratioAINP = AINN = AGND,
3.0 V ≤ AVDD ≤ 5.5 V, at dc
–108dB
AINP = AINN = AGND,
3.0 V ≤ AVDD ≤ 5.5 V,
10 kHz, 100-mV ripple
–107
AC ACCURACY
SNRSignal-to-noise ratiofIN = 1 kHz7882.5dB
SINADSignal-to-noise + distortionfIN = 1 kHz77.582.3dB
THDTotal harmonic distortion4.5 V ≤ AVDD ≤ 5.5 V,
5 MHz ≤ fCLKIN ≤ 21 MHz, fIN = 1 kHz
–98–84dB
3.0 V ≤ AVDD ≤ 3.6 V,
5 MHz ≤ fCLKIN ≤ 20 MHz, fIN = 1 kHz
–93–83
SFDRSpurious-free dynamic rangefIN = 1 kHz83100dB
DIGITAL INPUTS/OUTPUTS
CMOS Logic With Schmitt-Trigger
IIN Input currentDGND ≤ VIN ≤ DVDD07µA
CIN Input capacitance4 pF
VIH High-level input voltage0.7 × DVDDDVDD + 0.3 V
VIL Low-level input voltage–0.30.3 × DVDD V
CLOAD Output load capacitance30pF
VOH High-level output voltageIOH = –20 µA DVDD – 0.1V
IOH = –4 mA DVDD – 0.4
VOL Low-level output voltageIOL = 20 µA 0.1V
IOL = 4 mA 0.4
POWER SUPPLY
AVDDHigh-side supply voltage3.05.05.5V
IAVDD High-side supply current3.0 V ≤ AVDD ≤ 3.6 V6.38.5mA
4.5 V ≤ AVDD ≤ 5.5 V7.29.8
DVDDController-side supply voltage2.73.35.5V
IDVDD Controller-side supply currentAMC1306Ex, 2.7 V ≤ DVDD ≤ 3.6 V,
CLOAD = 15 pF
4.15.5mA
AMC1306Mx, 2.7 V ≤ DVDD ≤ 3.6 V,
CLOAD = 15 pF
3.34.8
AMC1306Ex, 4.5 V ≤ DVDD ≤ 5.5 V,
CLOAD = 15 pF
5.06.9
AMC1306Mx, 4.5 V ≤ DVDD ≤ 5.5 V,
CLOAD = 15 pF
3.96.0
Steady-state voltage supported by the device in case of a system failure. See specified common-mode input voltage VCM for normal operation. Observe analog input voltage range as specified in the Absolute Maximum Ratings table.
The common-mode overvoltage detection level has a typical hysteresis of 90 mV.
This is the –3-dB, second-order roll-off frequency of the integrated differential input amplifier to consider for the antialiasing filter design.
Integral nonlinearity is defined as the maximum deviation from a straight line passing through the end-points of the ideal ADC transfer function expressed as a number of LSBs or as a percent of the specified linear full-scale range (FSR).
Offset error drift is calculated using the box method, as described by the following equation:
AMC1306E05 AMC1306E25 AMC1306M05 AMC1306M25 ec_eodrift_bas654.gif
Gain error drift is calculated using the box method, as described by the following equation:
AMC1306E05 AMC1306E25 AMC1306M05 AMC1306M25 ec_egdrift_bas654.gif

Electrical Characteristics: AMC1306x25

minimum and maximum specifications apply from TA = –40°C to +125°C, AVDD = 3.0 V to 5.5 V, DVDD = 2.7 V to 5.5 V, AINP = –250 mV to 250 mV, AINN = AGND, and sinc3 filter with OSR = 256 (unless otherwise noted); typical specifications are at TA = 25°C, CLKIN = 20 MHz, AVDD = 5 V, and DVDD = 3.3 V
PARAMETERTEST CONDITIONSMINTYP MAXUNIT
ANALOG INPUTS
VClippingDifferential input voltage before clipping outputAINP – AINN±320mV
FSRSpecified linear differential full-scaleAINP – AINN–250 250mV
Absolute common-mode input voltage(1)(AINP + AINN) / 2 to AGND–2AVDDV
VCMOperating common-mode input voltage(AINP + AINN) / 2 to AGND–0.16 AVDD – 2.1V
VCMovCommon-mode overvoltage detection level(2)(AINP + AINN) / 2 to AGNDAVDD – 2V
CINSingle-ended input capacitanceAINN = AGND 2 pF
CIND Differential input capacitance 1 pF
IIB Input bias currentAINP = AINN = AGND, IIB = IIBP + IIBN–82 –60–48µA
RIN Single-ended input resistanceAINN = AGND19
RIND Differential input resistance 22
IIO Input offset current ±5 nA
CMTICommon-mode transient immunity50100 kV/µs
CMRRCommon-mode rejection ratioAINP = AINN, fIN = 0 Hz,
VCM min ≤ VIN ≤ VCM max
–95 dB
AINP = AINN, fIN from 0.1 Hz to 50 kHz,
VCM min ≤ VIN ≤ VCM max
–95
BWInput bandwidth(3) 900 kHz
DC ACCURACY
DNLDifferential nonlinearityResolution: 16 bits–0.99 0.99LSB
INLIntegral nonlinearity(4) Resolution: 16 bits–4 ±14LSB
EO Offset errorInitial, at 25°C, AINP = AINN = AGND–100 ±4.5100µV
TCEO Offset error thermal drift(5) –1±0.15 1µV/°C
EG Gain error Initial, at 25°C–0.2%±0.005%0.2%
TCEG Gain error thermal drift(6) –40±2040ppm/°C
PSRRPower-supply rejection ratioAINP = AINN = AGND,
3.0 V ≤ AVDD ≤ 5.5 V, at dc
–103 dB
AINP = AINN = AGND,
3.0 V ≤ AVDD ≤ 5.5 V,
10 kHz, 100-mV ripple
–92
AC ACCURACY
SNRSignal-to-noise ratiofIN = 1 kHz82 86 dB
SINADSignal-to-noise + distortionfIN = 1 kHz81.9 85.7 dB
THDTotal harmonic distortion4.5 V ≤ AVDD ≤ 5.5 V,
5 MHz ≤ fCLKIN ≤ 21 MHz, fIN = 1 kHz
–98–86dB
3.0 V ≤ AVDD ≤ 3.6 V,
5 MHz ≤ fCLKIN ≤ 20 MHz, fIN = 1 kHz
–93–85
SFDRSpurious-free dynamic rangefIN = 1 kHz83 100 dB
DIGITAL INPUTS/OUTPUTS
CMOS Logic with Schmitt-trigger
IIN Input currentDGND ≤ VIN ≤ DVDD07μA
CIN Input capacitance4 pF
VIH High-level input voltage0.7 × DVDDDVDD + 0.3 V
VIL Low-level input voltage–0.30.3 × DVDD V
CLOAD Output load capacitancefCLKIN = 20 MHz30pF
VOH High-level output voltageIOH = –20 µA DVDD – 0.1V
IOH = –4 mA DVDD – 0.4
VOL Low-level output voltageIOL = 20 µA 0.1V
IOL = 4 mA 0.4
POWER SUPPLY
AVDDHigh-side supply voltage3.05.05.5V
IAVDD High-side supply current3.0 V ≤ AVDD ≤ 3.6 V6.38.5mA
4.5 V ≤ AVDD ≤ 5.5 V7.29.8
DVDDController-side supply voltage2.73.35.5V
IDVDD Controller-side supply currentAMC1306Ex, 2.7 V ≤ DVDD ≤ 3.6 V,
CLOAD = 15 pF
4.15.5mA
AMC1306Mx, 2.7 V ≤ DVDD ≤ 3.6 V,
CLOAD = 15 pF
3.34.8
AMC1306Ex, 4.5 V ≤ DVDD ≤ 5.5 V,
CLOAD = 15 pF
5.06.9
AMC1306Mx, 4.5 V ≤ DVDD ≤ 5.5 V,
CLOAD = 15 pF
3.96.0
Steady-state voltage supported by the device in case of a system failure; see the specified common-mode input voltage VCM for normal operation. Adhere to the analog input voltage range as specified in the Absolute Maximum Ratings table.
The common-mode overvoltage detection level has a typical hysteresis of 90 mV.
This parameter is the –3-dB, second-order, roll-off frequency of the integrated differential input amplifier to consider for antialiasing filter designs.
Integral nonlinearity is defined as the maximum deviation from a straight line passing through the end-points of the ideal ADC transfer function expressed as number of LSBs or as a percent of the specified linear full-scale range FSR.
Offset error drift is calculated using the box method, as described by the following equation: AMC1306E05 AMC1306E25 AMC1306M05 AMC1306M25 ec_eodrift_bas654.gif .
Gain error drift is calculated using the box method, as described by the following equation: AMC1306E05 AMC1306E25 AMC1306M05 AMC1306M25 ec_egdrift_bas654.gif .

Switching Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
fCLKINCLKIN clock frequency4.5 V ≤ AVDD ≤ 5.5 V521MHz
3.0 V ≤ AVDD ≤ 5.5 V520
tCLKINCLKIN clock period4.5 V ≤ AVDD ≤ 5.5 V47.6200ns
3.0 V ≤ AVDD ≤ 5.5 V50200
tHIGH CLKIN clock high time20 25120 ns
tLOW CLKIN clock low time2025120ns
tH DOUT hold time after rising edge
of CLKIN
AMC1306Mx(1),
CLOAD = 15 pF
3.5ns
tD Rising edge of CLKIN to DOUT valid delayAMC1306Mx(1), CLOAD = 15 pF15ns
tr DOUT rise time10% to 90%, 2.7 V ≤ DVDD ≤ 3.6 V,
CLOAD = 15 pF
0.83.5ns
10% to 90%, 4.5 V ≤ DVDD ≤ 5.5 V,
CLOAD = 15 pF
1.83.9
tf DOUT fall time 90% to 10%, 2.7 V ≤ DVDD ≤ 3.6 V,
CLOAD = 15 pF
0.83.5ns
90% to 10%, 4.5 V ≤ DVDD ≤ 5.5 V,
CLOAD = 15 pF
1.83.9
tISTARTInterface startup timeDVDD at 2.7 V (min) to DOUT valid with AVDD ≥ 3.0 V3232CLKIN cycles
tASTARTAnalog startup timeAVDD step to 3.0 V with DVDD ≥ 2.7 V, 0.1% settling0.5ms
The output of the Manchester encoded versions of the AMC1306Ex can change with every edge of CLKIN with a typical delay of 6 ns; see the Manchester Coding Feature section for additional details.
AMC1306E05 AMC1306E25 AMC1306M05 AMC1306M25 tim_int_bas734.gif Figure 1. Digital Interface Timing
AMC1306E05 AMC1306E25 AMC1306M05 AMC1306M25 tim_start_bas734.gif Figure 2. Device Startup Timing

Insulation Characteristics Curves

AMC1306E05 AMC1306E25 AMC1306M05 AMC1306M25 D001_SBAS734.gif
Figure 3. Thermal Derating Curve for Safety-Limiting Current per VDE
AMC1306E05 AMC1306E25 AMC1306M05 AMC1306M25 tddb_curve_reinforced_dw.gif
TA up to 150°C, stress-voltage frequency = 60 Hz,
isolation working voltage = 1500 VRMS, operating lifetime = 135 years
Figure 5. Reinforced Isolation Capacitor Lifetime Projection
AMC1306E05 AMC1306E25 AMC1306M05 AMC1306M25 D002_SBAS734.gif
Figure 4. Thermal Derating Curve for Safety-Limiting
Power per VDE

Typical Characteristics

at AVDD = 5 V, DVDD = 3.3 V, AINP = –50 mV to 50 mV (AMC1306x05) or –250 mV to 250 mV (AMC1306x25), AINN = AGND, fCLKIN = 20 MHz, and sinc3 filter with OSR = 256 (unless otherwise noted)
AMC1306E05 AMC1306E25 AMC1306M05 AMC1306M25 D003_SBAS734.gif
Figure 6. Maximum Operating Common-Mode Input Voltage vs High-Side Supply Voltage
AMC1306E05 AMC1306E25 AMC1306M05 AMC1306M25 D005_SBAS734.gif
Figure 8. Input Bias Current vs
Common-Mode Input Voltage
AMC1306E05 AMC1306E25 AMC1306M05 AMC1306M25 D008_SBAS734.gif
Figure 10. Integral Nonlinearity vs Temperature
AMC1306E05 AMC1306E25 AMC1306M05 AMC1306M25 D010_SBAS734.gif
Figure 12. Offset Error vs Temperature
AMC1306E05 AMC1306E25 AMC1306M05 AMC1306M25 D012_SBAS734.gif
Figure 14. Gain Error vs High-Side Supply Voltage
AMC1306E05 AMC1306E25 AMC1306M05 AMC1306M25 D014_SBAS734.gif
Figure 16. Gain Error vs Clock Frequency
AMC1306E05 AMC1306E25 AMC1306M05 AMC1306M25 D016_SBAS734.gif
Figure 18. Signal-to-Noise Ratio and Signal-to-Noise + Distortion vs High-Side Supply Voltage
AMC1306E05 AMC1306E25 AMC1306M05 AMC1306M25 D018_SBAS734.gif
Figure 20. Signal-to-Noise Ratio and Signal-to-Noise + Distortion vs Clock Frequency
AMC1306E05 AMC1306E25 AMC1306M05 AMC1306M25 D020_SBAS734.gif
Figure 22. Signal-to-Noise Ratio and Signal-to-Noise + Distortion vs Input Signal Amplitude
AMC1306E05 AMC1306E25 AMC1306M05 AMC1306M25 D021_SBAS734.gif
fCLKIN = 21 MHz
Figure 24. Total Harmonic Distortion vs
High-Side Supply Voltage (5 V, nom)
AMC1306E05 AMC1306E25 AMC1306M05 AMC1306M25 D022_SBAS734.gif
Figure 26. Total Harmonic Distortion vs Temperature
AMC1306E05 AMC1306E25 AMC1306M05 AMC1306M25 D024_SBAS734.gif
Figure 28. Total Harmonic Distortion vs
Input Signal Frequency
AMC1306E05 AMC1306E25 AMC1306M05 AMC1306M25 D043_SBAS734.gif
AMC1306x05
Figure 30. Total Harmonic Distortion vs
Input Signal Amplitude
AMC1306E05 AMC1306E25 AMC1306M05 AMC1306M25 D027_SBAS734.gif
Figure 32. Spurious-Free Dynamic Range vs Temperature
AMC1306E05 AMC1306E25 AMC1306M05 AMC1306M25 D029_SBAS734.gif
Figure 34. Spurious-Free Dynamic Range vs
Input Signal Frequency
AMC1306E05 AMC1306E25 AMC1306M05 AMC1306M25 D046_SBAS734.gif
AMC1306x05
Figure 36. Spurious-Free Dynamic Range vs
Input Signal Amplitude
AMC1306E05 AMC1306E25 AMC1306M05 AMC1306M25 D045_SBAS734.gif
AMC1306x05, 4096-point FFT, VIN = 100 mVPP
Figure 38. Frequency Spectrum with 10-kHz Input Signal
AMC1306E05 AMC1306E25 AMC1306M05 AMC1306M25 D032_SBAS734.gif
AMC1306x25, 4096-point FFT, VIN = 500 mVPP
Figure 40. Frequency Spectrum with 10-kHz Input Signal
AMC1306E05 AMC1306E25 AMC1306M05 AMC1306M25 D034_SBAS734.gif
Figure 42. High-Side Supply Current vs Temperature
AMC1306E05 AMC1306E25 AMC1306M05 AMC1306M25 D036_SBAS734.gif
Figure 44. Controller-Side Supply Current vs
Controller-Side Supply Voltage
AMC1306E05 AMC1306E25 AMC1306M05 AMC1306M25 D038_SBAS734.gif
Figure 46. Controller-Side Supply Current vs
Clock Frequency
AMC1306E05 AMC1306E25 AMC1306M05 AMC1306M25 D004_SBAS734.gif
Figure 7. Common-Mode Overvoltage Detection Level vs Temperature
AMC1306E05 AMC1306E25 AMC1306M05 AMC1306M25 D006_SBAS734.gif
Figure 9. Common-Mode Rejection Ratio vs
Input Signal Frequency
AMC1306E05 AMC1306E25 AMC1306M05 AMC1306M25 D009_SBAS734.gif
Figure 11. Offset Error vs High-Side Supply Voltage
AMC1306E05 AMC1306E25 AMC1306M05 AMC1306M25 D011_SBAS734.gif
Figure 13. Offset Error vs Clock Frequency
AMC1306E05 AMC1306E25 AMC1306M05 AMC1306M25 D013_SBAS734.gif
Figure 15. Gain Error vs Temperature
AMC1306E05 AMC1306E25 AMC1306M05 AMC1306M25 D015_SBAS734.gif
Figure 17. Power-Supply Rejection Ratio vs
Ripple Frequency
AMC1306E05 AMC1306E25 AMC1306M05 AMC1306M25 D017_SBAS734.gif
Figure 19. Signal-to-Noise Ratio and Signal-to-Noise + Distortion vs Temperature
AMC1306E05 AMC1306E25 AMC1306M05 AMC1306M25 D019_SBAS734.gif
Figure 21. Signal-to-Noise Ratio and Signal-to-Noise + Distortion vs Input Signal Frequency
AMC1306E05 AMC1306E25 AMC1306M05 AMC1306M25 D042_SBAS734.gif
Figure 23. Signal-to-Noise Ratio and Signal-to-Noise + Distortion vs Input Signal Amplitude
AMC1306E05 AMC1306E25 AMC1306M05 AMC1306M25 D039_SBAS734.gif
fCLKIN = 20 MHz
Figure 25. Total Harmonic Distortion vs
High-Side Supply Voltage (3.3 V, nom)
AMC1306E05 AMC1306E25 AMC1306M05 AMC1306M25 D023_SBAS734.gif
Figure 27. Total Harmonic Distortion vs Clock Frequency
AMC1306E05 AMC1306E25 AMC1306M05 AMC1306M25 D025_SBAS734.gif
AMC1306x25
Figure 29. Total Harmonic Distortion vs
Input Signal Amplitude
AMC1306E05 AMC1306E25 AMC1306M05 AMC1306M25 D026_SBAS734.gif
Figure 31. Spurious-Free Dynamic Range vs
High-Side Supply Voltage
AMC1306E05 AMC1306E25 AMC1306M05 AMC1306M25 D028_SBAS734.gif
Figure 33. Spurious-Free Dynamic Range vs
Clock Frequency
AMC1306E05 AMC1306E25 AMC1306M05 AMC1306M25 D030_SBAS734.gif
AMC1306x25
Figure 35. Spurious-Free Dynamic Range vs
Input Signal Amplitude
AMC1306E05 AMC1306E25 AMC1306M05 AMC1306M25 D044_SBAS734.gif
AMC1306x05, 4096-point FFT, VIN = 100 mVPP
Figure 37. Frequency Spectrum with 1-kHz Input Signal
AMC1306E05 AMC1306E25 AMC1306M05 AMC1306M25 D031_SBAS734.gif
AMC1306x25, 4096-point FFT, VIN = 500 mVPP
Figure 39. Frequency Spectrum with 1-kHz Input Signal
AMC1306E05 AMC1306E25 AMC1306M05 AMC1306M25 D033_SBAS734.gif
Figure 41. High-Side Supply Current vs
High-Side Supply Voltage
AMC1306E05 AMC1306E25 AMC1306M05 AMC1306M25 D035_SBAS734.gif
Figure 43. High-Side Supply Current vs Clock Frequency
AMC1306E05 AMC1306E25 AMC1306M05 AMC1306M25 D037_SBAS734.gif
Figure 45. Controller-Side Supply Current vs Temperature