SLUSB97A October   2012  – December 2014

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Description (Continued)
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Device Power Up
        1. 8.3.1.1 Power-On-Reset (POR)
        2. 8.3.1.2 Power Up from Battery without DC Source
          1. 8.3.1.2.1 BATFET Turn Off
          2. 8.3.1.2.2 Shipping Mode
        3. 8.3.1.3 Power Up from DC Source
          1. 8.3.1.3.1 REGN LDO
          2. 8.3.1.3.2 Input Source Qualification
          3. 8.3.1.3.3 Input Current Limit Detection
          4. 8.3.1.3.4 D+/D- Detection Sets Input Current Limit
          5. 8.3.1.3.5 HIZ State wth 100mA USB Host
          6. 8.3.1.3.6 Force Input Current Limit Detection
        4. 8.3.1.4 Converter Power-Up
        5. 8.3.1.5 Boost Mode Operation from Battery
      2. 8.3.2 Power Path Management
        1. 8.3.2.1 Narrow VDC Architecture
        2. 8.3.2.2 Dynamic Power Management
        3. 8.3.2.3 Supplement Mode
      3. 8.3.3 Battery Charging Management
        1. 8.3.3.1 Autonomous Charging Cycle
        2. 8.3.3.2 Battery Charging Profile
        3. 8.3.3.3 Thermistor Cold/Hot Temperature Window
        4. 8.3.3.4 Charging Termination
          1. 8.3.3.4.1 Termination when REG02[0] = 1
          2. 8.3.3.4.2 Termination when REG05[6] = 1
        5. 8.3.3.5 Charging Safety Timer
        6. 8.3.3.6 USB Timer when Charging from USB100mA Source
      4. 8.3.4 Status Outputs (STAT and INT)
        1. 8.3.4.1 Charging Status Indicator (STAT)
        2. 8.3.4.2 Interrupt to Host (INT)
      5. 8.3.5 Protections
        1. 8.3.5.1 Input Current Limit on ILIM
        2. 8.3.5.2 Thermal Regulation and Thermal Shutdown
        3. 8.3.5.3 Voltage and Current Monitoring in Buck Mode
          1. 8.3.5.3.1 Input Over-Voltage (ACOV)
          2. 8.3.5.3.2 System Over-Voltage Protection (SYSOVP)
        4. 8.3.5.4 Current Monitoring in Boost Mode
        5. 8.3.5.5 Battery Protection
          1. 8.3.5.5.1 Battery Over-Current Protection (BATOVP)
          2. 8.3.5.5.2 Charging During Battery Short Protection
          3. 8.3.5.5.3 System Over-Current Protection
      6. 8.3.6 Serial Interface
        1. 8.3.6.1 Data Validity
        2. 8.3.6.2 START and STOP Conditions
        3. 8.3.6.3 Byte Format
        4. 8.3.6.4 Acknowledge (ACK) and Not Acknowledge (NACK)
        5. 8.3.6.5 Slave Address and Data Direction Bit
          1. 8.3.6.5.1 Single Read and Write
          2. 8.3.6.5.2 Multi-Read and Multi-Write
    4. 8.4 Device Functional Modes
      1. 8.4.1 Host Mode and Default Mode
        1. 8.4.1.1 Plug in USB100mA Source with Good Battery
        2. 8.4.1.2 USB Timer when Charging from USB 100-mA Source
    5. 8.5 Register Map
      1. 8.5.1 I2C Registers
        1. 8.5.1.1  Input Source Control Register REG00 (reset = 00110000, or 30)
        2. 8.5.1.2  Power-On Configuration Register REG01 (reset = 00011011, or 1B)
        3. 8.5.1.3  Charge Current Control Register REG02 (reset = 01100000, or 60)
        4. 8.5.1.4  Pre-Charge/Termination Current Control Register REG03 (reset = 00010001, or 11)
        5. 8.5.1.5  Charge Voltage Control Register REG04 (reset = 10110010, or B2)
        6. 8.5.1.6  Charge Termination/Timer Control Register REG05 (reset = 10011010, or 9A)
        7. 8.5.1.7  Thermal Regulation Control Register REG06 (reset = 00000011, or 03)
        8. 8.5.1.8  Misc Operation Control Register REG07 (reset = 01001011, or 4B)
        9. 8.5.1.9  System Status Register REG08
        10. 8.5.1.10 Fault Register REG09
        11. 8.5.1.11 Vender / Part / Revision Status Register REG0A (reset = 00100011, or 23)
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Inductor Selection
        2. 9.2.2.2 Input Capacitor
        3. 9.2.2.3 Output Capacitor
      3. 9.2.3 Application Performance Plots
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Related Links
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8 Detailed Description

8.1 Overview

The bq24195L, bq24195 is an I2C controlled power path management device and a single cell Li-Ion battery charger. It integrates the input reverse-blocking FET (RBFET, Q1), high-side switching FET (HSFET, Q2), low-side switching FET (LSFET, Q3), and BATFET (Q4) between system and battery. The device also integrates the bootstrap diode for the high-side gate drive.

8.2 Functional Block Diagram

fbd_lusb97.gif

8.3 Feature Description

8.3.1 Device Power Up

8.3.1.1 Power-On-Reset (POR)

The internal bias circuits are powered from the higher voltage of VBUS and BAT. When VBUS or VBAT rises above UVLOZ, the sleep comparator, battery depletion comparator and BATFET driver are active. I2C interface is ready for communication and all the registers are reset to default value. The host can access all the registers after POR.

8.3.1.2 Power Up from Battery without DC Source

If only battery is present and the voltage is above depletion threshold (VBAT_DEPL), the BATFET turns on and connects battery to system. The REGN LDO stays off to minimize the quiescent current. The low RDSON in BATFET and the low quiescent current on BAT minimize the conduction loss and maximize the battery run time. The device always monitors the discharge current through BATFET. When the system is overloaded or shorted, the device will immediately turn off BATFET and keep BATFET off until the input source plugs in again.

8.3.1.2.1 BATFET Turn Off

The BATFET can be forced off by the host through I2C REG07[5]. This bit allows the user to independently turn off the BATFET when the battery condition becomes abnormal during charging. When BATFET is off, there is no path to charge or discharge the battery.

When battery is not attached, the BATFET should be turned off by setting REG07[5] to 1 to disable charging and supplement mode.

8.3.1.2.2 Shipping Mode

When end equipment is assembled, the system is connected to battery through BATFET. There will be a small leakage current to discharge the battery even when the system is powered off. In order to extend the battery life during shipping and storage, the device can turn off BATFET so that the system voltage is zero to minimize the leakage.

In order to keep BATFET off during shipping mode, the host has to disable the watchdog timer (REG05[5:4] = 00) and disable BATFET (REG07[5] = 1) at the same time.

Once the BATFET is disabled, the BATFET can be turned on by plugging in adapter.

8.3.1.3 Power Up from DC Source

When the DC source plugs in, the bq24195L, bq24195 checks the input source voltage to turn on REGN LDO and all the bias circuits. It also checks the input current limit before starts the buck converter.

8.3.1.3.1 REGN LDO

The REGN LDO supplies internal bias circuits as well as the HSFET and LSFET gate drive. The LDO also provides bias rail to TS1/TS2 external resistors. The pull-up rail of STAT can be connected to REGN as well.

The REGN is enabled when all the conditions are valid.

  1. VBUS above UVLOZ
  2. VBUS above battery + VSLEEPZ in buck mode or VBUS below battery + VSLEEPZ in boost mode
  3. After typical 220ms delay (100ms minimum) is complete

If one of the above conditions is not valid, the device is in high impedance mode (HIZ) with REGN LDO off. The device draws less than 50 µA from VBUS during HIZ state. The battery powers up the system when the device is in HIZ.

8.3.1.3.2 Input Source Qualification

After REGN LDO powers up, the bq24195L, bq24195 checks the current capability of the input source. The input source has to meet the following requirements to start the buck converter.

  1. VBUS voltage below 18 V (not in ACOV)
  2. VBUS voltage above 3.8 V when pulling 30 mA (poor source detection)

Once the input source passes all the conditions above, the status register REG08[2] goes high. An INT is asserted to the host.

If the device fails the poor source detection, it will repeat the detection every 2 seconds.

8.3.1.3.3 Input Current Limit Detection

The USB ports on personal computers are convenient charging source for portable devices (PDs). If the portable device is attached to a USB host, the USB specification requires the portable device to draw limited current (100 mA/500 mA in USB 2.0, and 150 mA/900 mA in USB 3.0). If the portable device is attached to a charging port, it is allowed to draw up to 1.5 A.

After REG08[2] goes HIGH, the charger device always runs input current limit detection when a DC source plugs in unless the charger is in HIZ during host mode.

The bq24195L, bq24195 follows battery charging specification 1.2 (bc1.2) to detect input source through USB D+/D– lines. After the input current limit detection is done, the host can write to REG00[2:0] to change the input current limit.

8.3.1.3.4 D+/D– Detection Sets Input Current Limit

The bq24195L, bq24195 contains a D+/D– based input source detection to program the input current limit. The D+/D- detection has two steps: data contact detect (DCD) followed by primary detection.

DCD_Data_Contact_Detection_SLUSAW5.gifFigure 7. USB D+/D- Detection

DCD (Data Contact Detection) uses a current source to detect when the D+/D– pins have made contact during an attach event. The protocol for data contact detect is as follows:

  • Detect VBUS present and REG08[2] = 1 (power good)
  • Turn on D+ IDP_SRC and the D– pull-down resistor RDM_DWN for 40 ms
  • If the USB connector is properly attached, the D+ line goes from HIGH to LOW, wait up to 0.5 sec.
  • Turn off IDP_SRC and disconnect RDM_DWN

The primary detection is used to distinguish between USB host (Standard Down Stream Port, or SDP) and different type of charging ports (Charging Down Stream Port, or CDP, and Dedicated Charging Port, or DCP). The protocol for primary detection is as follows:

  • Turn on VDP_SRC on D+ and IDM_SINK on D– for 40 ms
  • If PD is attached to a USB host (SDP), the D– is low. If PD is attached to a charging port (CDP or DCP), the D– is high
  • Turn off VDP_SRC and IDM_SINK

Table 2 shows the input current limit setting after D+/D– detection.

Table 2. bq24195L, bq24195 USB D+/D– Detection

D+/D– DETECTION OTG INPUT CURRENT LIMIT REG08[7:6]
0.5 sec timer expired in DCD (D+/D- floating) 100 mA 00
USB host LOW 100 mA 01
USB host HIGH 500 mA 01
Charging port 1.5 A 10

8.3.1.3.5 HIZ State wth 100mA USB Host

In battery charging spec, the good battery threshold is the minimum charge level of a battery to power up the portable device successfully. When the input source is 100-mA USB host, and the battery is above bat-good threshold (VBATGD), the device follows battery charging spec and enters high impedance state (HIZ). In HIZ state, the device is in the lowest quiescent state with REGN LDO and the bias circuits off. The charger device sets REG00[7] to 1, and the VBUS current during HIZ state will be less than 30 µA. The system is supplied by the battery.

Once the charger device enters HIZ state in host mode, it stays in HIZ until the host writes REG00[7] = 0. When the processor host wakes up, it is recommended to first check if the charger is in HIZ state.

In default mode, the charger IC will reset REG00[7] back to 0 when input source is removed. When another source plugs in, the charger IC will run detection again, and update the input current limit.

8.3.1.3.6 Force Input Current Limit Detection

The host can force the charger device to run input current limit detection by setting REG07[7] = 1. After the detection is complete, REG07[7] will return to 0 by itself.

8.3.1.4 Converter Power-Up

After the input current limit is set, the converter is enabled and the HSFET and LSFET start switching. If battery charging is disabled, BATFET turns off. Otherwise, BATFET stays on to charge the battery.

The bq24195L, bq24195 provides soft-start when ramp up the system rail. When the system rail is below 2.2 V, the input current limit is forced to 100 mA. After the system rises above 2.2 V, the charger device sets the input current limit set by the lower value between register and ILIM pin.

As a battery charger, the bq24195L, bq24195 deploys a 1.5-MHz step-down switching regulator. The fixed frequency oscillator keeps tight control of the switching frequency under all conditions of input voltage, battery voltage, charge current and temperature, simplifying output filter design.

A type III compensation network allows using ceramic capacitors at the output of the converter. An internal saw-tooth ramp is compared to the internal error control signal to vary the duty cycle of the converter. The ramp height is proportional to the PMID voltage to cancel out any loop gain variation due to a change in input voltage.

In order to improve light-load efficiency, the device switches to PFM control at light load when battery is below minimum system voltage setting or charging is disabled. During the PFM operation, the switching duty cycle is set by the ratio of SYS and VBUS.

8.3.1.5 Boost Mode Operation from Battery

The bq24195L, bq24195 supports boost converter operation to deliver power from the battery to other portable devices through USB port. The boost mode output current rating meets the 1 A (bq24195L) or 2.1 A (bq24195) charging requirements for smartphone and tablet. The boost operation can be enabled if the following conditions are valid:

  1. BAT above BATLOWV threshold (VBATLOWV set by REG04[1])
  2. VBUS less than BAT+VSLEEP (in sleep mode)
  3. Boost mode operation is enabled (OTG pin HIGH and REG01[5:4] = 10)
  4. After 220-ms delay from boost mode enable

In battery boost mode, the bq24195L, bq24195 employs a 1.5-MHz step-up switching regulator. During boost mode, the status register REG08[7:6] is set to 11, the PMID output voltage is 5.1 V.

For power bank applications, the boost current is supported from PMID pin as in the application diagram. It is recommended to use the minimum PMID cap value 20 µF (bq24195L) or 60 µF (bq24195) for boost current. Please note that there is no boost current limit setting when the boost current is sourced from PMID pin, hence it is important not to overload the boost current under this condition.

8.3.2 Power Path Management

The bq24195L, bq24195 accommodates a wide range of input sources from USB, wall adapter, to car battery. The device provides automatic power path selection to supply the system (SYS) from input source (VBUS), battery (BAT), or both.

8.3.2.1 Narrow VDC Architecture

The device deploys Narrow VDC architecture (NVDC) with BATFET separating system from battery. The minimum system voltage is set by REG01[3:1]. Even with a fully depleted battery, the system is regulated above the minimum system voltage (default 3.5 V).

When the battery is below minimum system voltage setting, the BATFET operates in linear mode (LDO mode), and the system is 150 mV above the minimum system voltage setting. As the battery voltage rises above the minimum system voltage, BATFET is fully on and the voltage difference between the system and battery is the VDS of BATFET.

When the battery charging is disabled or terminated, the system is always regulated at 150 mV above the minimum system voltage setting. The status register REG08[0] goes high when the system is in minimum system voltage regulation.

V_SYS_vs_V_BAT_SLUSAW5.gifFigure 8. V(SYS) vs V(BAT)

8.3.2.2 Dynamic Power Management

To meet maximum current limit in USB spec and avoid over loading the adapter, the bq24195L, bq24195 features Dynamic Power Management (DPM), which continuously monitors the input current and input voltage.

When input source is over-loaded, either the current exceeds the input current limit (REG00[2:0]) or the voltage falls below the input voltage limit (REG00[6:3]). The device then reduces the charge current until the input current falls below the input current limit and the input voltage rises above the input voltage limit.

When the charge current is reduced to zero, but the input source is still overloaded, the system voltage starts to drop. Once the system voltage falls below the battery voltage, the device automatically enters the supplement mode where the BATFET turns on and battery starts discharging so that the system is supported from both the input source and battery.

During DPM mode (either VINDPM or IINDPM), the status register REG08[3] will go high.

Figure 9 shows the DPM response with 9-V/1.2-A adapter, 3.2-V battery, 2.8-A charge current and 3.4-V minimum system voltage setting.

DPM_Response_SLUSAW5.gifFigure 9. DPM Response

8.3.2.3 Supplement Mode

When the system voltage falls below the battery voltage, the BATFET turns on and the BATFET gate is regulated the gate drive of BATFET so that the minimum BATFET VDS stays at 30 mV when the current is low. This prevents oscillation from entering and exiting the supplement mode. As the discharge current increases, the BATFET gate is regulated with a higher voltage to reduce RDSON until the BATFET is in full conduction. At this point onwards, the BATFET VDS linearly increases with discharge current. Figure 10 shows the V-I curve of the BATFET gate regulation operation. BATFET turns off to exit supplement mode when the battery is below battery depletion threshold.

BATFET_V_I_Curve_SLUSAW5.gifFigure 10. BATFET V-I Curve

8.3.3 Battery Charging Management

The bq24195L, bq24195 charges 1-cell Li-Ion battery with up to 2.5A/4.5A charge current for high capacity tablet battery. The 12-mΩ BATFET improves charging efficiency and minimizes the voltage drop during discharging.

8.3.3.1 Autonomous Charging Cycle

With battery charging enabled at POR (REG01[5:4] = 01), the bq24195L, bq24195 can complete a charging cycle without host involvement. The device default charging parameters are listed in .

Table 3. Charging Parameter Default Setting

DEFAULT MODE bq24195L, bq24195
Charging voltage 4.208 V
Charging current 2.048 A
Pre-charge current 256 mA
Termination current 256 mA
Temperature profile Hot/Cold
Safety timer 8 hours

A new charge cycle starts when the following conditions are valid:

  • Converter starts
  • Battery charging is enabled by I2C register bit (REG01[5:4]) = 01 and CE is low
  • No thermistor fault on TS1 and TS2
  • No safety timer fault
  • BATFET is not forced to turn off (REG07[5])

The charger device automatically terminates the charging cycle when the charging current is below termination threshold and charge voltage is above recharge threshold. When a full battery voltage is discharged below recharge threshold (REG04[0]), the bq24195L, bq24195 automatically starts another charging cycle.

The STAT output indicates the charging status of charging (LOW), charging complete or charge disable (HIGH) or charging fault (Blinking). The status register REG08[5:4] indicates the different charging phases: 00-charging disable, 01-precharge, 10-fast charge (constant current) and constant voltage mode, 11-charging done. Once a charging cycle is complete, an INT is asserted to notify the host.

The host can always control the charging operation and optimize the charging parameters by writing to the registers through I2C.

8.3.3.2 Battery Charging Profile

The device charges the battery in three phases: preconditioning, constant current and constant voltage. At the beginning of a charging cycle, the device checks the battery voltage and applies current.

Table 4. Charging Current Setting

VBAT CHARGING CURRENT REG DEFAULT SETTING REG08[5:4]
< 2 V 100 mA 01
2 V - 3 V REG03[7:4] 256 mA 01
> 3 V REG02[7:2] 2048 mA 10

If the charger device is in DPM regulation or thermal regulation during charging, the actual charging current will be less than the programmed value. In this case, termination is temporarily disabled and the charging safety timer is counted at half the clock rate.

Battery_Charging_Profile_SLUSAW5.gifFigure 11. Battery Charging Profile

8.3.3.3 Thermistor Cold/Hot Temperature Window

The bq24195L, bq24195 continuously monitors battery temperature by measuring the voltage between the TS pins and ground, typically determined by a negative temperature coefficient thermistor and an external voltage divider. The device compares this voltage against its internal thresholds to determine if charging is allowed. To initiate a charge cycle, the battery temperature must be within the VLTF to VHTF thresholds. During the charge cycle the battery temperature must be within the VLTF to VTCO thresholds, else the device suspends charging and waits until the battery temperature is within the VLTF to VHTF range.

TS_Resistor_Network_SLUSB97.gifFigure 12. TS Resistor Network

When the TS fault occurs, the fault register REG09[2:0] indicates the actual condition on each TS pin and an INT is asserted to the host. The STAT pin indicates the fault when charging is suspended.

TS_pin_Thermistor_Sense_Thresholds_SLUSAW5.gifFigure 13. TS Pin Thermistor Sense Thresholds

Assuming a 103AT NTC thermistor is used on the battery pack, the value RT1 and RT2 can be determined by using the following equations:

Equation 1. Eq1_slusaw5.gif

Select 0°C to 45°C range for Li-ion or Li-polymer battery,
RTHCOLD = 27.28 kΩ
RTHHOT = 4.911 kΩ
RT1 = 5.52 kΩ
RT2 = 31.23 kΩ

8.3.3.4 Charging Termination

The bq24195L, bq24195 terminates a charge cycle when the battery voltage is above recharge threshold, and the current is below termination current. After the charging cycle is complete, the BATFET turns off. The converter keeps running to power the system, and BATFET can turn back on to engage supplement mode.

When termination occurs, the status register REG08[5:4] is 11, and an INT is asserted to the host. Termination is temporarily disabled if the charger device is in input current/voltage regulation or thermal regulation. Termination can be disabled by writing 0 to REG05[7].

8.3.3.4.1 Termination when REG02[0] = 1

When REG02[0] is HIGH to reduce the charging current by 80%, the charging current could be less than the termination current. The charger device termination function should be disabled. When the battery is charged to fully capacity, the host disables charging through CE pin or REG01[5:4].

8.3.3.4.2 Termination when REG05[6] = 1

Usually the STAT bit indicates charging complete when the charging current falls below termination threshold. Write REG05[6] = 1 to enable an early “charge done” indication on STAT pin. The STAT pin goes high when the charge current reduces below 800 mA. The charging cycle is still on-going until the current falls below the termination threshold.

8.3.3.5 Charging Safety Timer

The bq24195L, bq24195 has safety timer to prevent extended charging cycle due to abnormal battery conditions.

In default mode, the device keeps charging the battery with 5-hour fast charging safety timer regardless of REG05[2:1] default value. At the end of the 5 hours, the EN_HIZ (REG00[7]) is set to signal the buck converter stops and the system load is supplied by the battery. The EN_HIZ bit can be cleared to restart the buck converter.

In host mode, the device keeps charging the battery until the fast charging safety timer expired. The duration of safety timer can be set by the REG05[2:1] bits (default = 8 hours). At the end of safety timer, the EN_HIZ (REG00[7]) is cleared to signal the buck converter continues to operation to supply system load.

The safety timer is 1 hour when the battery is below BATLOWV threshold. The user can program fast charge safety timer through I2C (REG05[2:1]). When safety timer expires, the fault register REG09[5:4] goes 11 and an INT is asserted to the host. The safety timer feature can be disabled via I2C (REG05[3]).

The following actions restart the safety timer:

  • At the beginning of a new charging cycle
  • Toggle the CE pin HIGH to LOW to HIGH (charge enable)
  • Write REG01[5:4] from 00 to 01 (charge enable)
  • Write REG05[3] from 0 to 1 (safety timer enable)

During input voltage/current regulation or thermal regulation, or when FORCE_20PCT (REG02[0]) bit is set, the safety timer counts at half clock rate since the actual charge current is likely to be below the register setting. For example, if the charger is in input current regulation (IINDPM) throughout the whole charging cycle, and the safety time is set to 5 hours, the safety timer will expire in 10 hours. This feature can be disabled by writing 0 to REG07[6].

It is recommended to disable safety timer first by clearing REG05[3] bit before safety timer configuration is changed. The safety timer should be re-enabled by setting REG05[3] bit.

8.3.3.6 USB Timer when Charging from USB100mA Source

The total charging time in default mode from USB100-mA source is limited by a 45-min max timer. At the end of the timer, the device stops the converter and goes to HIZ.

8.3.4 Status Outputs (STAT and INT)

8.3.4.1 Charging Status Indicator (STAT)

The bq24195L, bq24195 indicates charging state on the open drain STAT pin. The STAT pin can drive LED as the application diagram shows.

Table 5. STAT Pin State

CHARGING STATE STAT
Charging in progress (including recharge) LOW
Charging complete HIGH
Sleep mode, charge disable HIGH
Charge suspend (Input over-voltage, TS fault, timer fault, input or system over-voltage) blinking at 1Hz

8.3.4.2 Interrupt to Host (INT)

In some applications, the host does not always monitor the charger operation. The INT notifies the system on the device operation. The following events will generate 256-us INT pulse.

  • USB/adapter source identified (through DPDM detection)
  • Good input source detected
    • VVBUS - VBAT > VSLEEPZ
    • VVBUS > VACOV
    • current limit above IBADSRC
  • Input removed
  • Charge Complete
  • Any FAULT event in REG09

When a fault occurs, the charger device sends out INT and keeps the fault state in REG09 until the host reads the fault register. Before the host reads REG09 and all the faults are cleared, the charger device would not send any INT upon new faults. In order to read the current fault status, the host has to read REG09 two times consecutively. The 1st reads fault register status from the last read and the 2nd reads the current fault register status.

8.3.5 Protections

8.3.5.1 Input Current Limit on ILIM

For safe operation, the bq24195L, bq24195 has an additional hardware pin on ILIM to limit maximum input current on ILIM pin. The input maximum current is set by a resistor from ILIM pin to ground as:

Equation 2. Eq3_slusaw5.gif

The actual input current limit is the lower value between ILIM setting and register setting (REG00[2:0]). For example, if the register setting is 111 for 3 A, and ILIM has a 353-Ω resistor to ground for 1.5 A, the input current limit is 1.5 A. ILIM pin can be used to set the input current limit rather than the register settings.

The device regulates ILIM pin at 1 V. If ILIM voltage exceeds 1 V, the device enters input current regulation (Refer to Dynamic Power Path Management section).

The voltage on the ILIM pin is proportional to the input current. The ILIM pin can be used to monitor the input current per Equation 3:

Equation 3. Eq4_slusaw5.gif

For example, if the ILIM pin sets 2 A, and the ILIM voltage is 0.6 V, the actual input current is 1.2 A. If the ILIM pin is open, the input current is limited to zero since ILIM voltage floats above 1 V. If the ILIM pin is short, the input current limit is set by the register.

8.3.5.2 Thermal Regulation and Thermal Shutdown

The bq24195L, bq24195 monitors the internal junction temperature TJ to avoid overheat the chip and limits the IC surface temperature. When the internal junction temperature exceeds the preset limit (REG06[1:0]), the device lowers down the charge current. The wide thermal regulation range from 60°C to 120°C allows the user to optimize the system thermal performance.

During thermal regulation, the actual charging current is usually below the programmed battery charging current. Therefore, termination is disabled, the safety timer runs at half the clock rate, and the status register REG08[1] goes high.

Additionally, the device has thermal shutdown to turn off the converter. The fault register REG09[5:4] is 10 and an INT is asserted to the host.

8.3.5.3 Voltage and Current Monitoring in Buck Mode

The bq24195L, bq24195 closely monitor the input and system voltage, as well as HSFET and LSFET current for safe buck mode operation.

8.3.5.3.1 Input Over-Voltage (ACOV)

The maximum input voltage for buck mode operation is 18 V. If VBUS voltage exceeds 18 V, the device stops switching immediately. During input over voltage (ACOV), the fault register REG09[5:4] will be set to 01. An INT is asserted to the host.

8.3.5.3.2 System Over-Voltage Protection (SYSOVP)

The charger device monitors the voltage at SYS. When system over-voltage is detected, the converter is stopped to protect components connected to SYS from high voltage damage.

8.3.5.4 Current Monitoring in Boost Mode

The bq24195L, bq24195 closely monitors LSFET current to ensure safe boost mode operation.

8.3.5.5 Battery Protection

8.3.5.5.1 Battery Over-Current Protection (BATOVP)

The battery over-voltage limit is clamped at 4% above the battery regulation voltage. When battery over voltage occurs, the charger device immediately disables charge. The fault register REG09[5] goes high and an INT is asserted to the host.

8.3.5.5.2 Charging During Battery Short Protection

If the battery voltage falls below 2 V, the charge current is reduced to 100 mA for battery safety.

8.3.5.5.3 System Over-Current Protection

If the system is shorted or exceeds the over-current limit, the BATFET is latched off. DC source insertion on VBUS is required to reset the latch-off condition and turn on BATFET.

8.3.6 Serial Interface

The bq24195L, bq24195 uses I2C compatible interface for flexible charging parameter programming and instantaneous device status reporting. I2C is a bi-directional 2-wire serial interface developed by Philips Semiconductor (now NXP Semiconductors). Only two bus lines are required: a serial data line (SDA) and a serial clock line (SCL). Devices can be considered as masters or slaves when performing data transfers. A master is the device which initiates a data transfer on the bus and generates the clock signals to permit that transfer. At that time, any device addressed is considered a slave.

The device operates as a slave device with address 6BH, receiving control inputs from the master device like micro controller or a digital signal processor. The I2C interface supports both standard mode (up to 100 kbits), and fast mode (up to 400 kbits).

Both SDA and SCL are bi-directional lines, connecting to the positive supply voltage via a current source or pull-up resistor. When the bus is free, both lines are HIGH. The SDA and SCL pins are open drain.

8.3.6.1 Data Validity

The data on the SDA line must be stable during the HIGH period of the clock. The HIGH or LOW state of the data line can only change when the clock signal on the SCL line is LOW. One clock pulse is generated for each data bit transferred.

Bit_Transfer_on_the_I2C_Bus_SLUSAW5.gifFigure 14. Bit Transfer on the I2C Bus

8.3.6.2 START and STOP Conditions

All transactions begin with a START (S) and can be terminated by a STOP (P). A HIGH to LOW transition on the SDA line while SCl is HIGH defines a START condition. A LOW to HIGH transition on the SDA line when the SCL is HIGH defines a STOP condition.

START and STOP conditions are always generated by the master. The bus is considered busy after the START condition, and free after the STOP condition.

START_and_STOP_conditions_SLUSAW5.gifFigure 15. START and STOP conditions

8.3.6.3 Byte Format

Every byte on the SDA line must be 8 bits long. The number of bytes to be transmitted per transfer is unrestricted. Each byte has to be followed by an Acknowledge bit. Data is transferred with the Most Significant Bit (MSB) first. If a slave cannot receive or transmit another complete byte of data until it has performed some other function, it can hold the clock line SCL low to force the master into a wait state (clock stretching). Data transfer then continues when the slave is ready for another byte of data and release the clock line SCL.

Data_Transfer_on_the_I2C_Bus_SLUSAW5.gifFigure 16. Data Transfer on the I2C Bus

8.3.6.4 Acknowledge (ACK) and Not Acknowledge (NACK)

The acknowledge takes place after every byte. The acknowledge bit allows the receiver to signal the transmitter that the byte was successfully received and another byte may be sent. All clock pulses, including the acknowledge 9th clock pulse, are generated by the master.

The transmitter releases the SDA line during the acknowledge clock pulse so the receiver can pull the SDA line LOW and it remains stable LOW during the HIGH period of this clock pulse.

When SDA remains HIGH during the 9th clock pulse, this is the Not Acknowledge signal. The master can then generate either a STOP to abort the transfer or a repeated START to start a new transfer.

8.3.6.5 Slave Address and Data Direction Bit

After the START, a slave address is sent. This address is 7 bits long followed by the eighth bit as a data direction bit (bit R/W). A zero indicates a transmission (WRITE) and a one indicates a request for data (READ).

Complete_Data_Transfer_SLUSASW5.gifFigure 17. Complete Data Transfer

8.3.6.5.1 Single Read and Write

Single_Write_SLUSAW5.gifFigure 18. Single Write
Single_Read_SLUSAW5.gifFigure 19. Single Read

If the register address is not defined, the charger IC send back NACK and go back to the idle state.

8.3.6.5.2 Multi-Read and Multi-Write

The charger device supports multi-read and multi-write on REG00 through REG08.

Multi_Write_SLUSAW5.gifFigure 20. Multi-Write
Multi_Read_SLUSAW5.gifFigure 21. Multi-Read

The fault register REG09 locks the previous fault and only clears it after the register is read. For example, if Charge Safety Timer Expiration fault occurs but recovers later, the fault register REG09 reports the fault when it is read the first time, but returns to normal when it is read the second time. To verify real time fault, the fault register REG09 should be read twice to get the real condition. In addition, the fault register REG09 does not support multi-read or multi-write.

8.4 Device Functional Modes

8.4.1 Host Mode and Default Mode

The bq24195L, bq24195 is a host controlled device, but it can operate in default mode without host management. In default mode, bq24195L, bq24195 can be used as an autonomous charger with no host or with host in sleep.

When the charger is in default mode, REG09[7] is HIGH. When the charger is in host mode, REG09[7] is LOW. After power-on-reset, the device starts in watchdog timer expiration state, or default mode. All the registers are in the default settings.

Any write command to bq24195L, bq24195 transitions the device from default mode to host mode. All the device parameters can be programmed by the host. To keep the device in host mode, the host has to reset the watchdog timer by writing 1 twice to REG01[6] before the watchdog timer expires (REG05[5:4]), or disable watchdog timer by setting REG05[5:4] = 00.

Watchdog_Timer_Flow_Chart_SLUSAW5.gifFigure 22. Watchdog Timer Flow Chart

8.4.1.1 Plug in USB100mA Source with Good Battery

When the input source is detected as 100-mA USB host, and the battery voltage is above batgood threshold (VBATGD), the charger device enters HIZ state to meet the battery charging spec requirement.

If the charger device is in host mode, it will stay in HIZ state even after the USB100-mA source is removed, and the adapter plugs in. During the HIZ state, REG00[7] is set HIGH and the system load is supplied from battery. It is recommended that the processor host always checks if the charger IC is in HIZ state when it wakes up. The host can write REG00[7] to 0 to exit HIZ state.

If the charger is in default mode, when the DC source is removed, the charger device will get out of HIZ state automatically. When the input source plugs in again, the charger IC runs detection on the input source and update the input current limit.

8.4.1.2 USB Timer when Charging from USB 100-mA Source

The total charging time in default mode from USB 100-mA source is limited by a 45-min max timer. At the end of the timer, the device stops the converter and goes to HIZ.

8.5 Register Map

Table 6. Register Map

REGISTER REGISTER NAME RESET
REG00 Input Source Control Register 00110000, or 30
REG01 Power-On Configuration Register 00011011, or 1B
REG02 Charge Current Control Register 01100000, or 60
REG03 Pre-Charge/Termination Current Control Register 00010001, or 11
REG04 Charge Voltage Control Register 10110010, or B2
REG05 Charge Termination/Timer Control Register 10011010, or 9A
REG06 Thermal Regulation Control Register 00000011, or 03
REG07 Misc Operation Control Register 01001011, or 4B
REG08 System Status Register
REG09 Fault Register
REG0A Vender / Part / Revision Status Register

8.5.1 I2C Registers

Address: 6BH. REG00-07 support Read and Write. REG08-0A are read only.

8.5.1.1 Input Source Control Register REG00 (reset = 00110000, or 30)

Figure 23. REG00 Input Source Control Register Format
7 6 5 4 3 2 1 0
EN_HIZ VINDPM[3] VINDPM[2] VINDPM[1] VINDPM[0] IINLIM[2] IINLIM[1] IINLIM[0]
R/W R/W R/W R/W R/W R/W R/W R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 7. REG00 Input Source Control Register Description

BIT FIELD TYPE RESET DESCRIPTION
Bit 7 EN_HIZ R/W 0 0 – Disable, 1 – Enable Default: Disable (0)
Input Voltage Limit
Bit 6 VINDPM[3] R/W 0 640 mV Offset 3.88 V, Range: 3.88 V to 5.08 V
Default: 4.36 V (0110)
Bit 5 VINDPM[2] R/W 1 320 mV
Bit 4 VINDPM[1] R/W 1 160 mV
Bit 3 VINDPM[0] R/W 0 80 mV
Input Current Limit (Actual input current limit is the lower of I2C and ILIM)
Bit 2 IINLIM[2] R/W 0 000 – 100 mA, 001 – 150 mA, 010 – 500 mA,
011 – 900 mA, 100 – 1.2 A,
101 – 1.5 A,
110 – 2 A, 111 – 3 A
Default SDP: 100 mA (000)(OTG pin = 0) or 500 mA (010)
(OTG pin = 1)
Default DCP/CDP: 1.5 A (101)
Bit 1 IINLIM[1] R/W 0
Bit 0 IINLIM[0] R/W 0

8.5.1.2 Power-On Configuration Register REG01 (reset = 00011011, or 1B)

Figure 24. REG01 Power-On Configuration Register Format
7 6 5 4 3 2 1 0
Register Reset I2C Watchdog Timer Reset CHG_CONFIG[1] CHG_CONFIG[0] SYS_MIN[2] SYS_MIN[1] SYS_MIN[0] Reserved
R/W R/W R/W R/W R/W R/W R/W R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 8. REG01 Power-On Configuration Register Description

BIT FIELD TYPE RESET DESCRIPTION NOTE
Bit 7 Register Reset R/W 0 0 – Keep current register setting,
1 – Reset to default
Default: Keep current register setting (0)
Back to 0 after register reset
Bit 6 I2C Watchdog Timer Reset R/W 0 0 – Normal ; 1 – Reset Default: Normal (0)
Back to 0 after timer reset
Charger Configuration
Bit 5 CHG_CONFIG[1] R/W 0 00 – Charge Disable, 01 – Charge Battery,
10/11 – OTG
Default: Charge Battery (01)
Bit 4 CHG_CONFIG[0] R/W 1
Minimum System Voltage Limit
Bit 3 SYS_MIN[2] R/W 1 0.4 V Offset: 3.0 V, Range 3.0 V to 3.7 V
Default: 3.5 V (101)
Bit 2 SYS_MIN[1] R/W 0 0.2 V
Bit 1 SYS_MIN[0] R/W 1 0.1 V
Bit 0 Reserved R/W 1 1 - Reserved Reserved. Must write "1"

8.5.1.3 Charge Current Control Register REG02 (reset = 01100000, or 60)

Figure 25. REG02 Charge Current Control Register Format
7 6 5 4 3 2 1 0
ICHG[5] ICHG[4] ICHG[3] ICHG[2] ICHG[1] ICHG[0] Reserved FORCE_20PCT
R/W R/W R/W R/W R/W R/W R/W R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 9. REG02 Charge Current Control Register Description

BIT FIELD TYPE RESET DESCRIPTION NOTE
Fast Charge Current Limit
Bit 7 ICHG[5] R/W 0 2048 mA Offset: 512 mA
Range: 512 to 4544 mA (bq24195)
Range: 512 to 2496mA (bq24195L)

Default: 2048 mA (011000)
Bit 6 ICHG[4] R/W 1 1024 mA
Bit 5 ICHG[3] R/W 1 512 mA
Bit 4 ICHG[2] R/W 0 256 mA
Bit 3 ICHG[1] R/W 0 128 mA
Bit 2 ICHG[0] R/W 0 64 mA
Bit 1 Reserved R/W 0 0 - Reserved Reserved. Must write "0"
Bit 0 FORCE_20PCT R/W 0 0 - ICHG as REG02[7:2] (Fast Charge Current Limit) and REG03[7:4] (Pre-Charge Current Limit) programmed
1 - ICHG as 20% of REG02[7:2] (Fast Charge Current Limit) and 50% of REG03[7:4] (Pre-Charge Current Limit) programmed
Default: ICHG as REG02[7:2] (Fast Charge Current Limit) and REG03[7:4] (Pre-Charge Current Limit) programmed (0)

8.5.1.4 Pre-Charge/Termination Current Control Register REG03 (reset = 00010001, or 11)

Figure 26. REG03 Pre-Charge/Termination Current Control Register Format
7 6 5 4 3 2 1 0
IPRECHG[3] IPRECHG[2] IPRECHG[1] IPRECHG[0] ITERM[3] ITERM[2] ITERM[1] ITERM[0]
R/W R/W R/W R/W R/W R/W R/W R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 10. REG03 Pre-Charge/Termination Current Control Register Description

BIT FIELD TYPE RESET DESCRIPTION NOTE
Pre-Charge Current Limit
Bit 7 IPRECHG[3] R/W 0 1024 mA Offset: 128 mA,
Range: 128 mA to 2048 mA
Default: 256 mA (0001)
Bit 6 IPRECHG[2] R/W 0 512 mA
Bit 5 IPRECHG[1] R/W 0 256 mA
Bit 4 IPRECHG[0] R/W 1 128 mA
Termination Current Limit
Bit 3 ITERM[3] R/W 0 1024 mA Offset: 128 mA
Range: 128 mA to 2048 mA
Default: 256 mA (0001)
Bit 2 ITERM[2] R/W 0 512 mA
Bit 1 ITERM[1] R/W 0 256 mA
Bit 0 ITERM[0] R/W 1 128 mA

8.5.1.5 Charge Voltage Control Register REG04 (reset = 10110010, or B2)

Figure 27. REG04 Charge Voltage Control Register Format
7 6 5 4 3 2 1 0
VREG[5] VREG[4] VREG[3] VREG[2] VREG[1] VREG[0] BATLOWV VRECHG
R/W R/W R/W R/W R/W R/W R/W R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 11. REG04 Charge Voltage Control Register Description

BIT FIELD TYPE RESET DESCRIPTION NOTE
Charge Voltage Limit
Bit 7 VREG[5] R/W 1 512 mV Offset: 3.504 V
Range: 3.504 V to 4.400 V (111000)
Default: 4.208 V (101100)
Bit 6 VREG[4] R/W 0 256 mV
Bit 5 VREG[3] R/W 1 128 mV
Bit 4 VREG[2] R/W 1 64 mV
Bit 3 VREG[1] R/W 0 32 mV
Bit 2 VREG[0] R/W 0 16 mV
Battery Precharge to Fast Charge Threshold
Bit 1 BATLOWV R/W 1 0 – 2.8 V, 1 – 3.0 V Default: 3.0 V (1)
Battery Recharge Threshold (below battery regulation voltage)
Bit 0 VRECHG R/W 0 0 – 100 mV, 1 – 300 mV Default: 100 mV (0)

8.5.1.6 Charge Termination/Timer Control Register REG05 (reset = 10011010, or 9A)

Figure 28. REG05 Charge Termination/Timer Control Register Format
7 6 5 4 3 2 1 0
EN_TERM TERM_STAT WATCHDOG[1] WATCHDOG[0] EN_TIMER CHG_TIMER[1] CHG_TIMER[0] Reserved
R/W R/W R/W R/W R/W R/W R/W R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 12. REG05 Charge Termination/Timer Control Register Description

BIT FIELD TYPE RESET DESCRIPTION NOTE
Charging Termination Enable
Bit 7 EN_TERM R/W 1 0 – Disable, 1 – Enable Default: Enable termination (1)
Termination Indicator Threshold
Bit 6 TERM_STAT R/W 0 0 – Match ITERM,
1 – STAT pin high before actual termination when charge current below 800 mA
Default Match ITERM (0)
I2C Watchdog Timer Setting
Bit 5 WATCHDOG[1] R/W 0 00 – Disable timer, 01 – 40 s, 10 – 80 s, 11 – 160 s Default: 40 s (01)
Bit 4 WATCHDOG[0] R/W 1
Charging Safety Timer Enable
Bit 3 EN_TIMER R/W 1 0 – Disable, 1 – Enable Default: Enable (1)
Fast Charge Timer Setting
Bit 2 CHG_TIMER[1] R/W 0 00 – 5 hrs, 01 – 8 hrs, 10 – 12 hrs, 11 – 20 hrs Default: 8 hours (01)
(See Charging Safety Timer for details)
Bit 1 CHG_TIMER[0] R/W 1
Bit 0 Reserved R/W 0 0 - Reserved Reserved. Must write "0"

8.5.1.7 Thermal Regulation Control Register REG06 (reset = 00000011, or 03)

Figure 29. REG06 Thermal Regulation Control Register Format
7 6 5 4 3 2 1 0
Reserved Reserved Reserved Reserved Reserved Reserved TREG[1] TREG[0]
R/W R/W R/W R/W R/W R/W R/W R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 13. REG06 Thermal Regulation Control Register Description

BIT FIELD TYPE RESET DESCRIPTION NOTE
Bit 7 Reserved R/W 0 0 - Reserved Reserved. Must write "0"
Bit 6 Reserved R/W 0 0 - Reserved Reserved. Must write "0"
Bit 5 Reserved R/W 0 0 - Reserved Reserved. Must write "0"
Bit 4 Reserved R/W 0 0 - Reserved Reserved. Must write "0"
Bit 3 Reserved R/W 0 0 - Reserved Reserved. Must write "0"
Bit 2 Reserved R/W 0 0 - Reserved Reserved. Must write "0"
Thermal Regulation Threshold
Bit 1 TREG[1] R/W 1 00 – 60°C, 01 – 80°C, 10 – 100°C, 11 – 120°C Default: 120°C (11)
Bit 0 TREG[0] R/W 1

8.5.1.8 Misc Operation Control Register REG07 (reset = 01001011, or 4B)

Figure 30. REG07 Misc Operation Control Register Format
7 6 5 4 3 2 1 0
DPDM_EN TMR2X_EN BATFET_Disable Reserved Reserved Reserved INT_MASK[1] INT_MASK[0]
R/W R/W R/W R/W R/W R/W R/W R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 14. REG07 Misc Operation Control Register Description

BIT FIELD TYPE RESET DESCRIPTION NOTE
Force DPDM detection
Bit 7 DPDM_EN R/W 0 0 – Not in D+/D– detection;
1 – Force D+/D– detection
Default: Not in D+/D– detection (0), Back to 0 after detection complete
Safety Timer Setting during Input DPM and Thermal Regulation
Bit 6 TMR2X_EN R/W 1 0 – Safety timer not slowed by 2X during input DPM or thermal regulation,
1 – Safety timer slowed by 2X during input DPM or thermal regulation
Default: Safety timer slowed by 2X (1)
Force BATFET Off
Bit 5 BATFET_Disable R/W 0 0 – Allow Q4 turn on, 1 – Turn off Q4 Default: Allow Q4 turn on(0)
Bit 4 Reserved R/W 0 0 – Reserved. Must write "0"
Bit 3 Reserved R/W 1 1 – Reserved. Must write "1"
Bit 2 Reserved R/W 0 0 – Reserved. Must write "0"
Bit 1 INT_MASK[1] R/W 1 0 – No INT during CHRG_FAULT, 1 – INT on CHRG_FAULT Default: INT on CHRG_FAULT (1)
Bit 0 INT_MASK[0] R/W 1 0 – No INT during BAT_FAULT, 1 – INT on BAT_FAULT Default: INT on BAT_FAULT (1)

8.5.1.9 System Status Register REG08

Figure 31. REG08 System Status Register Format
7 6 5 4 3 2 1 0
VBUS_STAT[1] VBUS_STAT[0] CHRG_STAT[1] CHRG_STAT[0] DPM_STAT PG_STAT THERM_STAT VSYS_STAT
R R R R R R R R
LEGEND: R = Read only; -n = value after reset

Table 15. REG08 System Status Register Description

BIT FIELD TYPE DESCRIPTION
Bit 7 VBUS_STAT[1] R 00 – Unknown (no input, or DPDM detection incomplete), 01 – USB host, 10 – Adapter port, 11 – OTG
Bit 6 VBUS_STAT[0] R
Bit 5 CHRG_STAT[1] R 00 – Not Charging, 01 – Pre-charge (<VBATLOWV), 10 – Fast Charging, 11 – Charge Termination Done
Bit 4 CHRG_STAT[0] R
Bit 3 DPM_STAT R 0 – Not DPM, 1 – VINDPM or IINDPM
Bit 2 PG_STAT R 0 – Not Power Good, 1 – Power Good
Bit 1 THERM_STAT R 0 – Normal, 1 – In Thermal Regulation
Bit 0 VSYS_STAT R 0 – Not in VSYSMIN regulation (BAT > VSYSMIN), 1 – In VSYSMIN regulation (BAT < VSYSMIN)

8.5.1.10 Fault Register REG09

Figure 32. REG09 Fault Register Format
7 6 5 4 3 2 1 0
WATCHDOG_
FAULT
Reserved CHRG_FAULT[1] CHRG_FAULT[0] BAT_FAULT NTC_FAULT[2] NTC_FAULT[1] NTC_FAULT[0]
R R R R R R R R
LEGEND: R = Read only; -n = value after reset

Table 16. REG09 Fault Register Description

BIT FIELD TYPE DESCRIPTION
Bit 7 WATCHDOG_FAULT R 0 – Normal, 1- Watchdog timer expiration
Bit 6 Reserved R 0 - Reserved
Bit 5 CHRG_FAULT[1] R 00 – Normal, 01 – Input fault (VBUS OVP or VBAT < VBUS < 3.8 V), 10 - Thermal shutdown,
11 – Charge Safety Timer Expiration
Bit 4 CHRG_FAULT[0] R
Bit 3 BAT_FAULT R 0 – Normal, 1 – BATOVP
Bit 2 NTC_FAULT[2] R 000 – Normal, 101 – Cold, 110 – Hot
Bit 1 NTC_FAULT[1] R
Bit 0 NTC_FAULT[0] R

8.5.1.11 Vender / Part / Revision Status Register REG0A (reset = 00100011, or 23)

Figure 33. REG0A Vender / Part / Revision Status Register Format
7 6 5 4 3 2 1 0
Reserved Reserved PN[2] PN[1] PN[0] TS_PROFILE DEV_REG[0] DEV_REG[1]
R R R R R R R R
LEGEND: R = Read only; -n = value after reset

Table 17. REG0A Vender / Part / Revision Status Register Description

BIT FIELD TYPE RESET DESCRIPTION
Bit 7 Reserved R 0 0 - Reserved
Bit 6 Reserved R 0 0 - Reserved
Device Configuration
Bit 5 PN[2] R 1 100
Bit 4 PN[1] R 0
Bit 3 PN[0] R 0
Bit 2 TS_PROFILE R 0 0 - Cold/Hot window
Bit 1 DEV_REG[0] R 1 11
Bit 0 DEV_REG[1] R 1