SLUSBC1B September   2013  – December 2016

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (Continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Device Power Up
        1. 8.3.1.1 Power-On-Reset (POR)
        2. 8.3.1.2 Power Up from Battery without DC Source
          1. 8.3.1.2.1 BATFET Turn Off
          2. 8.3.1.2.2 Shipping Mode
        3. 8.3.1.3 Boost Mode Operation from Battery
          1. 8.3.1.3.1 Integrated Control to Switch Between USB Charge Mode and Boost Mode
        4. 8.3.1.4 Power Up from DC Source
          1. 8.3.1.4.1 REGN LDO
          2. 8.3.1.4.2 Input Source Qualification
          3. 8.3.1.4.3 Input Current Limit Detection
          4. 8.3.1.4.4 D+/D- Detection Sets Input Current Limit
          5. 8.3.1.4.5 Force Input Current Limit Detection
        5. 8.3.1.5 Converter Power-Up
        6. 8.3.1.6 Low Power HIZ State
      2. 8.3.2 Power Path Management
        1. 8.3.2.1 Narrow VDC Architecture
        2. 8.3.2.2 Dynamic Power Management
        3. 8.3.2.3 Supplement Mode
      3. 8.3.3 Battery Charging Management
        1. 8.3.3.1 Autonomous Charging Cycle
        2. 8.3.3.2 Battery Charging Profile
        3. 8.3.3.3 Thermistor Qualification
          1. 8.3.3.3.1 Cold/Hot Temperature Window
        4. 8.3.3.4 Charging Termination
          1. 8.3.3.4.1 Termination When REG02[0] = 1
        5. 8.3.3.5 Charging Safety Timer
          1. 8.3.3.5.1 Safety Timer Configuration Change
      4. 8.3.4 Status Outputs (STAT, and INT)
        1. 8.3.4.1 Charging Status Indicator (STAT)
        2. 8.3.4.2 Interrupt to Host (INT)
      5. 8.3.5 Protections
        1. 8.3.5.1 Input Current Limit on ILIM
        2. 8.3.5.2 Thermal Regulation and Thermal Shutdown
        3. 8.3.5.3 Voltage and Current Monitoring in Buck Mode
          1. 8.3.5.3.1 Input Over-Voltage (ACOV)
          2. 8.3.5.3.2 System Over-Voltage Protection (SYSOVP)
        4. 8.3.5.4 Current Monitoring in Boost Mode
        5. 8.3.5.5 Battery Protection
          1. 8.3.5.5.1 Battery Over-Voltage Protection (BATOVP)
          2. 8.3.5.5.2 Battery Short Protection
          3. 8.3.5.5.3 System Over-Current Protection
    4. 8.4 Device Functional Modes
      1. 8.4.1 Host Mode and Default Mode
    5. 8.5 Programming
      1. 8.5.1 Serial Interface
        1. 8.5.1.1 Data Validity
        2. 8.5.1.2 START and STOP Conditions
        3. 8.5.1.3 Byte Format
        4. 8.5.1.4 Acknowledge (ACK) and Not Acknowledge (NACK)
        5. 8.5.1.5 Slave Address and Data Direction Bit
          1. 8.5.1.5.1 Single Read and Write
          2. 8.5.1.5.2 Multi-Read and Multi-Write
    6. 8.6 Register Map
      1. 8.6.1 I2C Registers
        1. 8.6.1.1  Input Source Control Register REG00 [reset = 01011000, or 0x58]58 to 0x58 in heading
        2. 8.6.1.2  Power-On Configuration Register REG01 [reset = 0011101100011011 to 00111011 and 0x1B to 0x3B in heading, or 0x3B]
        3. 8.6.1.3  Charge Current Control Register REG02 [reset = 00100000, or 0x20]
        4. 8.6.1.4  Pre-Charge/Termination Current Control Register REG03 [reset = 00010001, or 0x11]
        5. 8.6.1.5  Charge Voltage Control Register REG04 [reset = 10110010, or 0xB2]
        6. 8.6.1.6  Charge Termination/Timer Control Register REG05 [reset = 10011100, or 0x9C]
        7. 8.6.1.7  Boost Voltage/Thermal Regulation Control Register REG06 [reset = 10010011, or 0x93]
        8. 8.6.1.8  Misc Operation Control Register REG07 [reset = 01001011, or 0x4B4B to 0x4B in heading ]
        9. 8.6.1.9  System Status Register REG08
        10. 8.6.1.10 New Fault Register REG09
        11. 8.6.1.11 Vender / Part / Revision Status Register REG0A
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Inductor Selection
        2. 9.2.2.2 Input Capacitor
        3. 9.2.2.3 Output Capacitor
      3. 9.2.3 Application Performance Plots
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Pin Configuration and Functions

RGE Package
24-Pin VQFN With Exposed Thermal Pad
(Top View)
bq24295 Pinout1_SLUSBC1.gif

Pin Functions

PIN TYPE DESCRIPTION
NAME NUMBER
VBUS 1,24 P Charger Input Voltage. The internal n-channel reverse block MOSFET (RBFET) is connected between VBUS and PMID with VBUS on source. Place a 1-µF ceramic capacitor from VBUS to PGND and place it as close as possible to IC.
D+ 2 I
Analog		 Positive line of the USB data line pair. D+/D– based USB host/charging port detection. The detection includes data contact detection (DCD) and primary detection in bc1.2.
D– 3 I
Analog		 Negative line of the USB data line pair. D+/D– based USB host/charging port detection. The detection includes data contact detection (DCD) and primary detection in bc1.2.
STAT 4 O Open drain charge status output to indicate various charger operation. Connect to the pull up rail via 10-kΩ resistor. LOW indicates charge in progress. HIGH indicates charge complete or charge disabled. When any fault condition occurs, STAT pin in the charge blinks at 1 Hz.
SCL 5 I I2C Interface clock. Connect SCL to the logic rail through a 10-kΩ resistor.
SDA 6 I/O I2C Interface data. Connect SDA to the logic rail through a 10-kΩ resistor.
INT 7 O Open-drain Interrupt Output. Connect the INT to a logic rail via 10kΩ resistor. The INT pin sends active low, 256-µs pulse to host to report charger device status and fault.
OTG 8 I
Digital		 OTG Enable pin. The boost mode is activated when the OTG pin is High, REG01[5] = 1, and no Input source is detected at VBUS.
CE 9 I Active low Charge Enable pin. Battery charging is enabled when REG01[5:4] = 01 and CE pin = Low. CE pin must be pulled high or low.
ILIM 10 I ILIM pin sets the maximum input current limit by regulating the ILIM voltage at 1 V. A resistor is connected from ILIM pin to ground to set the maximum limit as IINMAX = (1V/RILIM) × KILIM. The actual input current limit is the lower one set by ILIM and by I2C REG00[2:0]. The minimum input current programmed on ILIM pin is 500 mA.
TS 11 I
Analog		 Temperature qualification voltage input. Connect a negative temperature coefficient thermistor. Program temperature window with a resistor divider from REGN to TS to GND. Charge suspends or Boost disable when TS pin is out of range. A 103AT-2 thermistor is recommended.
QON 12 I BATFET enable control in shipping mode. A logic low to high transition on this pin with minimum 2ms high level turns on BATFET to exit shipping mode. It has internal 1MΩ (Typ) pull down. For backward compatibility, when BATFET enable control function is not used, the pin can be a no connect or tied to TS pin (10k NTC thermistor only). (Refer to Shipping Mode for detail description).
BAT 13,14 P Battery connection point to the positive pin of the battery pack. The internal BATFET is connected between BAT and SYS. Connect a 10 µF closely to the BAT pin.
SYS 15,16 I System connection point. The internal BATFET is connected between BAT and SYS. When the battery falls below the minimum system voltage, switch-mode converter keeps SYS above the minimum system voltage.
PGND 17,18 P Power ground connection for high-current power converter node. Internally, PGND is connected to the source of the n-channel LSFET. On PCB layout, connect directly to ground connection of input and output capacitors of the charger. A single point connection is recommended between power PGND and the analog GND near the IC PGND pin.
SW 19,20 O Switching node connecting to output inductor. Internally SW is connected to the source of the n-channel HSFET and the drain of the n-channel LSFET. Connect the 0.047-µF bootstrap capacitor from SW to BTST.
BTST 21 P PWM high side driver positive supply. Internally, the BTST is connected to the anode of the boost-strap diode. Connect the 0.047-µF bootstrap capacitor from SW to BTST.
REGN 22 P PWM low side driver positive supply output. Internally, REGN is connected to the cathode of the boost-strap diode. Connect a 4.7-µF (10-V rating) ceramic capacitor from REGN to analog GND. The capacitor should be placed close to the IC. REGN also serves as bias rail of TS pin.
PMID 23 P Battery Boost Mode Output Voltage. Connected to the drain of the reverse blocking MOSFET and the drain of HSFET. The minimum capactiance required on PMID to PGND is 20 µF
Thermal Pad P Exposed pad beneath the IC for heat dissipation. Always solder thermal pad to the board, and have vias on the thermal pad plane star-connecting to PGND and ground plane for high-current power converter.