SLUS805C April   2008  – August 2015

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Input Overvoltage Protection
      2. 7.3.2 Battery Overvoltage Protection
      3. 7.3.3 Thermal Protection
      4. 7.3.4 Start-Up Short-Circuit Protection
      5. 7.3.5 Enable Function
      6. 7.3.6 Fault Indication
    4. 7.4 Device Functional Modes
      1. 7.4.1 OPERATION Mode
      2. 7.4.2 POWER-DOWN Mode
      3. 7.4.3 POWER-ON RESET Mode
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Selection of R(BAT)
        2. 8.2.2.2 Selection of R(CE)
        3. 8.2.2.3 Selection of Input and Output Bypass Capacitors
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Related Links
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

DSG Package
8-Pin WSON With Exposed Thermal Pad
Top View
bq24380 bq24381 bq24382 po_lus805.gif

Pin Functions

PIN I/O DESCRIPTION
NAME NO.
CE 5 I Active-low chip enable input. Connect CE = HI to turn the input pass FET off. Connect CE = LOW to turn the internal pass FET on and connect the input to the charging circuitry. CE is Internally pulled down, approximately 200 kΩ.
FAULT 4 O Open-drain device status output. FAULT is pulled to VSS internally when the input pass FET has been turned off due to input overvoltage or output short-circuit conditions, an overtemperature condition, or because the battery voltage is outside safe limits. FAULT is high impedance during normal operation.
IN 1 I Input power, connected to external DC supply. Bypass IN to VSS with a ceramic capacitor (1 μF minimum)
NC 3, 7 Do not connect to any external circuits. These pins may have internal connections used for test purposes.
OUT 8 O Output terminal to the charging system. Bypass OUT to VSS with a ceramic capacitor (1 μF minimum)
VBAT 6 I Battery voltage sense input. Connected to pack positive terminal through a 100-kΩ resistor.
VSS 2 – Ground terminal. Connect to the thermal pad and to the ground rail of the circuit.
Thermal PAD There is an internal electrical connection between the exposed thermal pad and the VSS pin of the device. The thermal pad must be connected to the same potential as the VSS pin on the printed-circuit board. Do not use the thermal pad as the primary ground input for the device. VSS pin must be connected to ground at all times.