SLUSCA6B March 2016  – March 2017


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Description (Continued)
  6. Device Comparison Table
  7. Pin Configuration and Functions
  8. Specifications
    1. 8.1Absolute Maximum Ratings
    2. 8.2ESD Ratings
    3. 8.3Recommended Operating Conditions
    4. 8.4Thermal Information
    5. 8.5Electrical Characteristics
    6. 8.6Timing Requirements
    7. 8.7Typical Characteristics
  9. Detailed Description
    1. 9.1Functional Block Diagram
    2. 9.2Feature Description
      1. 9.2.1 Device Power-On-Reset (POR)
      2. 9.2.2 Device Power Up from Battery without Input Source
      3. 9.2.3 Device Power Up from Input Source
        1. Up REGN Regulation (LDO)
        2. Source Qualification
        3. Source Type Detection
          1. Detection Sets Input Current Limit (bq25898D)
          2. Pin Sets Input Current Limit (bq25898)
          3. Input Current Limit Detection
        4. Voltage Limit Threshold Setting (VINDPM Threshold)
        5. Power-Up
      4. 9.2.4 Input Current Optimizer (ICO)
      5. 9.2.5 Boost Mode Operation from Battery
      6. 9.2.6 Power Path Management
        1. VDC Architecture
        2. Power Management
        3. Mode
      7. 9.2.7 Battery Charging Management
        1. Charging Cycle
        2. Charging Profile
        3. Termination
        4. Compensation (IRCOMP)
        5. Qualification
          1. Guideline Compliance in Charge Mode
          2. Temperature Window in Boost Mode
        6. Safety Timer
      8. 9.2.8 Battery Monitor
      9. 9.2.9 Status Outputs (PG, STAT, and INT)
        1. Good Indicator (PG)
        2. Status Indicator (STAT)
        3. to Host (INT)
      10. 9.2.10BATFET (Q4) Control
        1. Disable Mode (Shipping Mode)
        2. Enable (Exit Shipping Mode)
        3. Full System Reset
      11. 9.2.11Current Pulse Control Protocol
      12. 9.2.12Input Current Limit on ILIM
      13. 9.2.13Thermal Regulation and Thermal Shutdown
        1. Protection in Buck Mode
          1. Protection in Boost Mode
      14. 9.2.14Voltage and Current Monitoring in Buck and Boost Mode
        1. and Current Monitoring in Buck Mode
          1. Overvoltage (ACOV)
          2. Overvoltage Protection (SYSOVP)
        2. and Current Monitoring in Boost Mode
          1. Overcurrent Protection
          2. Mode Overvoltage Protection
      15. 9.2.15Battery Protection
        1. Overvoltage Protection (BATOVP)
        2. Over-Discharge Protection
        3. Overcurrent Protection
      16. 9.2.16Serial Interface
        1. Validity
        2. and STOP Conditions
        3. Format
        4. (ACK) and Not Acknowledge (NACK)
        5. Address and Data Direction Bit
        6. Read and Write
        7. and Multi-Write
    3. 9.3Device Functional Modes
      1. 9.3.1Host Mode and Default Mode
    4. 9.4Register Map
      1. 9.4.1 REG00
      2. 9.4.2 REG01
      3. 9.4.3 REG02
      4. 9.4.4 REG03
      5. 9.4.5 REG04
      6. 9.4.6 REG05
      7. 9.4.7 REG06
      8. 9.4.8 REG07
      9. 9.4.9 REG08
      10. 9.4.10REG09
      11. 9.4.11REG0A
      12. 9.4.12REG0B
      13. 9.4.13REG0C
      14. 9.4.14REG0D
      15. 9.4.15REG0E
      16. 9.4.16REG0F
      17. 9.4.17REG10
      18. 9.4.18REG11
      19. 9.4.19REG12
      20. 9.4.20REG13
      21. 9.4.21REG14
  10. 10Application and Implementation
    1. 10.1Application Information
    2. 10.2Typical Application Diagram
      1. 10.2.1Design Requirements
      2. 10.2.2Detailed Design Procedure
        1. Selection
        2. Input Capacitor
        3. Output Capacitor
      3. 10.2.3Application Curves
    3. 10.3System Example
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1Layout Guidelines
    2. 12.2Layout Example
  13. 13Device and Documentation Support
    1. 13.1Device Support
      1. 13.1.1Third-Party Products Disclaimer
    2. 13.2Related Links
    3. 13.3Receiving Notification of Documentation Updates
    4. 13.4Community Resources
    5. 13.5Trademarks
    6. 13.6Electrostatic Discharge Caution
    7. 13.7Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • YFF|42
Orderable Information

Application and Implementation


Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

Application Information

A typical application consists of the device configured as an I2C controlled power path management device and a single cell battery charger for Li-Ion and Li-polymer batteries used in a wide range of smartphones and other portable devices. It integrates an input reverse-block FET (RBFET, Q1), high-side switching FET (HSFET, Q2), low-side switching FET (LSFET, Q3), and BATFET (Q4) between the system and battery. The device also integrates a bootstrap diode for the high-side gate drive.

Typical Application Diagram

bq25898 bq25898D app_circuit2_bq25898D_slusca6.gif
VREF is the pull up voltage of I2C communication interface
Figure 49. bq25898D Application Diagram with PSEL with Interface and USB On-The-Go (OTG)

Design Requirements

For this design example, use the parameters shown in Table 30.

Table 30. Design Parameters

Input voltage range3.9 V to 14 V
Input current limit1.5 A
Fast charge current4032 mA
Output voltage 4.208 V

Detailed Design Procedure

Inductor Selection

The device has 1.5 MHz switching frequency to allow the use of small inductor and capacitor values. The Inductor saturation current should be higher than the charging current (ICHG) plus half the ripple current (IRIPPLE):

Equation 5. bq25898 bq25898D eq3_Ibat_slusbu7.gif

The inductor ripple current depends on input voltage (VBUS), duty cycle (D = VBAT/VVBUS), switching frequency (fs) and inductance (L):

Equation 6. bq25898 bq25898D eq4_Iripple_slusbu7.gif

The maximum inductor ripple current happens with D = 0.5 or close to 0.5. Usually inductor ripple is designed in the range of (20–40%) maximum charging current as a trade-off between inductor size and efficiency for a practical design.

Buck Input Capacitor

Input capacitor should have enough ripple current rating to absorb input switching ripple current. The worst case RMS ripple current is half of the charging current when duty cycle is 0.5. If the converter does not operate at 50% duty cycle, then the worst case capacitor RMS current IPMID occurs where the duty cycle is closest to 50% and can be estimated by Equation 7:

Equation 7. bq25898 bq25898D eq5_Icin_slusbu7.gif

Low ESR ceramic capacitor such as X7R or X5R is preferred for input decoupling capacitor and should be placed to the drain of the high side MOSFET and source of the low side MOSFET as close as possible. Voltage rating of the capacitor must be higher than normal input voltage level. 25 V rating or higher capacitor is preferred for up to 14-V input voltage. 8.2-μF capacitance is suggested for typical of 3 A – 5 A charging current.

System Output Capacitor

Output capacitor also should have enough ripple current rating to absorb output switching ripple current. The output capacitor RMS current ICOUT is given:

Equation 8. bq25898 bq25898D eq6_Icout_slusbu7.gif

The output capacitor voltage ripple can be calculated as follows:

Equation 9. bq25898 bq25898D eq7_Vout_slusbu7.gif

At certain input/output voltage and switching frequency, the voltage ripple can be reduced by increasing the output filter LC. The charger device has internal loop compensator. To get good loop stability, 1-µH and minimum of 20-µF output capacitor is recommended. The preferred ceramic capacitor is 6V or higher rating, X7R or X5R.

Application Curves

bq25898 bq25898D tek00072_Fig50_slusca6.png
VBAT = 3.2 V, VBUS = 5 V
Figure 50. Power Up with Charge Disabled
bq25898 bq25898D tek00079_FIG52_slusca6.png
VBUS = 5 V
Figure 52. Charge Enable
bq25898 bq25898D tek00093_FIG54_slusca6.png
VBUS = 5 V IIN = 3 A Charge Disable
Figure 54. Input Current DPM Response without Battery
bq25898 bq25898D tek00096_FIG56_slusca6.png
VBUS = 12 V VBAT = 3.8 V ICHG = 3 A
Figure 56. PWM Switching Waveform
bq25898 bq25898D tek00103_FIG58_slusca6.png
VBAT = 3.8 V ILOAD = 1 A
Figure 58. Boost Mode Switching Waveform
bq25898 bq25898D tek00082_FIG60_slusca6.png
VBAT = 3.2 V VBUS = 12 V
Figure 60. Power Up with Charge Disabled
bq25898 bq25898D tek00081_FIG62_slusca6.png
VBUS = 12 V
Figure 62. Charge Disable
bq25898 bq25898D tek00084_FIG64_slusca6.png
VBUS = 12 V ISYS = 7 mA Charge Disable
Figure 64. PFM Switching Waveform
bq25898 bq25898D tek00073_FIG51_slusca6.png
VBAT = 3.2 V, VBUS = 5 V
Figure 51. Power Up with Charge Enabled
bq25898 bq25898D tek00076_FIG53_slusca6.png
VBUS = 5 V
Figure 53. Charge Disable
bq25898 bq25898D tek00095_FIG55_slusca6.png
VBUS = 9 V IIN = 1.5 A VBAT = 3.8 V
ICHG = 2 AISYS = 0 A - 4 A
Figure 55. Load Transient During Supplement Mode
bq25898 bq25898D tek00102_FIG57_slusca6.png
VBUS = 9V ISYS = 20 mA, Charge Disable
No Battery
Figure 57. PFM Switching Waveform
bq25898 bq25898D tek00091_FIG59_slusca6.png
VBAT = 3.8 V ILOAD = 0 A - 1 A
Figure 59. Boost Mode Load Transient
bq25898 bq25898D tek00080_FIG61_slusca6.png
VBUS = 12 V
Figure 61. Charge Enable
bq25898 bq25898D tek00086_FIG63_slusca6.png
VBUS = 12 V VBAT = 3.8 V ICHG = 3 A
Figure 63. PWM Switching Waveform

System Example

bq25898 bq25898D app_circuit2_bq25898_slusca6.gif
C1 = 8.2µF (OTG ≤ 1.8A) or 20µF (OTG ≤ 2.4A) is recommended
Figure 65. bq25898 with PSEL Interface and USB On-The-Go (OTG)