SLUSCA6B March 2016  – March 2017

PRODUCTION DATA. 

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Description (Continued)
  6. Device Comparison Table
  7. Pin Configuration and Functions
  8. Specifications
    1. 8.1Absolute Maximum Ratings
    2. 8.2ESD Ratings
    3. 8.3Recommended Operating Conditions
    4. 8.4Thermal Information
    5. 8.5Electrical Characteristics
    6. 8.6Timing Requirements
    7. 8.7Typical Characteristics
  9. Detailed Description
    1. 9.1Functional Block Diagram
    2. 9.2Feature Description
      1. 9.2.1 Device Power-On-Reset (POR)
      2. 9.2.2 Device Power Up from Battery without Input Source
      3. 9.2.3 Device Power Up from Input Source
        1. 9.2.3.1Power Up REGN Regulation (LDO)
        2. 9.2.3.2Poor Source Qualification
        3. 9.2.3.3Input Source Type Detection
          1. 9.2.3.3.1D+/D- Detection Sets Input Current Limit (bq25898D)
          2. 9.2.3.3.2PSEL Pin Sets Input Current Limit (bq25898)
          3. 9.2.3.3.3Force Input Current Limit Detection
        4. 9.2.3.4Input Voltage Limit Threshold Setting (VINDPM Threshold)
        5. 9.2.3.5Converter Power-Up
      4. 9.2.4 Input Current Optimizer (ICO)
      5. 9.2.5 Boost Mode Operation from Battery
      6. 9.2.6 Power Path Management
        1. 9.2.6.1Narrow VDC Architecture
        2. 9.2.6.2Dynamic Power Management
        3. 9.2.6.3Supplement Mode
      7. 9.2.7 Battery Charging Management
        1. 9.2.7.1Autonomous Charging Cycle
        2. 9.2.7.2Battery Charging Profile
        3. 9.2.7.3Charging Termination
        4. 9.2.7.4Resistance Compensation (IRCOMP)
        5. 9.2.7.5Thermistor Qualification
          1. 9.2.7.5.1JEITA Guideline Compliance in Charge Mode
          2. 9.2.7.5.2Cold/Hot Temperature Window in Boost Mode
        6. 9.2.7.6Charging Safety Timer
      8. 9.2.8 Battery Monitor
      9. 9.2.9 Status Outputs (PG, STAT, and INT)
        1. 9.2.9.1Power Good Indicator (PG)
        2. 9.2.9.2Charging Status Indicator (STAT)
        3. 9.2.9.3Interrupt to Host (INT)
      10. 9.2.10BATFET (Q4) Control
        1. 9.2.10.1BATFET Disable Mode (Shipping Mode)
        2. 9.2.10.2BATFET Enable (Exit Shipping Mode)
        3. 9.2.10.3BATFET Full System Reset
      11. 9.2.11Current Pulse Control Protocol
      12. 9.2.12Input Current Limit on ILIM
      13. 9.2.13Thermal Regulation and Thermal Shutdown
        1. 9.2.13.1Thermal Protection in Buck Mode
          1. 9.2.13.1.1Thermal Protection in Boost Mode
      14. 9.2.14Voltage and Current Monitoring in Buck and Boost Mode
        1. 9.2.14.1Voltage and Current Monitoring in Buck Mode
          1. 9.2.14.1.1Input Overvoltage (ACOV)
          2. 9.2.14.1.2System Overvoltage Protection (SYSOVP)
        2. 9.2.14.2Voltage and Current Monitoring in Boost Mode
          1. 9.2.14.2.1VBUS Overcurrent Protection
          2. 9.2.14.2.2Boost Mode Overvoltage Protection
      15. 9.2.15Battery Protection
        1. 9.2.15.1Battery Overvoltage Protection (BATOVP)
        2. 9.2.15.2Battery Over-Discharge Protection
        3. 9.2.15.3System Overcurrent Protection
      16. 9.2.16Serial Interface
        1. 9.2.16.1Data Validity
        2. 9.2.16.2START and STOP Conditions
        3. 9.2.16.3Byte Format
        4. 9.2.16.4Acknowledge (ACK) and Not Acknowledge (NACK)
        5. 9.2.16.5Slave Address and Data Direction Bit
        6. 9.2.16.6Single Read and Write
        7. 9.2.16.7Multi-Read and Multi-Write
    3. 9.3Device Functional Modes
      1. 9.3.1Host Mode and Default Mode
    4. 9.4Register Map
      1. 9.4.1 REG00
      2. 9.4.2 REG01
      3. 9.4.3 REG02
      4. 9.4.4 REG03
      5. 9.4.5 REG04
      6. 9.4.6 REG05
      7. 9.4.7 REG06
      8. 9.4.8 REG07
      9. 9.4.9 REG08
      10. 9.4.10REG09
      11. 9.4.11REG0A
      12. 9.4.12REG0B
      13. 9.4.13REG0C
      14. 9.4.14REG0D
      15. 9.4.15REG0E
      16. 9.4.16REG0F
      17. 9.4.17REG10
      18. 9.4.18REG11
      19. 9.4.19REG12
      20. 9.4.20REG13
      21. 9.4.21REG14
  10. 10Application and Implementation
    1. 10.1Application Information
    2. 10.2Typical Application Diagram
      1. 10.2.1Design Requirements
      2. 10.2.2Detailed Design Procedure
        1. 10.2.2.1Inductor Selection
        2. 10.2.2.2Buck Input Capacitor
        3. 10.2.2.3System Output Capacitor
      3. 10.2.3Application Curves
    3. 10.3System Example
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1Layout Guidelines
    2. 12.2Layout Example
  13. 13Device and Documentation Support
    1. 13.1Device Support
      1. 13.1.1Third-Party Products Disclaimer
    2. 13.2Related Links
    3. 13.3Receiving Notification of Documentation Updates
    4. 13.4Community Resources
    5. 13.5Trademarks
    6. 13.6Electrostatic Discharge Caution
    7. 13.7Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Device and Documentation Support

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Table 31. Related Links

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Electrostatic Discharge Caution

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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

Glossary

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