SLUSCA6B March 2016  – March 2017

PRODUCTION DATA. 

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Description (Continued)
  6. Device Comparison Table
  7. Pin Configuration and Functions
  8. Specifications
    1. 8.1Absolute Maximum Ratings
    2. 8.2ESD Ratings
    3. 8.3Recommended Operating Conditions
    4. 8.4Thermal Information
    5. 8.5Electrical Characteristics
    6. 8.6Timing Requirements
    7. 8.7Typical Characteristics
  9. Detailed Description
    1. 9.1Functional Block Diagram
    2. 9.2Feature Description
      1. 9.2.1 Device Power-On-Reset (POR)
      2. 9.2.2 Device Power Up from Battery without Input Source
      3. 9.2.3 Device Power Up from Input Source
        1. 9.2.3.1Power Up REGN Regulation (LDO)
        2. 9.2.3.2Poor Source Qualification
        3. 9.2.3.3Input Source Type Detection
          1. 9.2.3.3.1D+/D- Detection Sets Input Current Limit (bq25898D)
          2. 9.2.3.3.2PSEL Pin Sets Input Current Limit (bq25898)
          3. 9.2.3.3.3Force Input Current Limit Detection
        4. 9.2.3.4Input Voltage Limit Threshold Setting (VINDPM Threshold)
        5. 9.2.3.5Converter Power-Up
      4. 9.2.4 Input Current Optimizer (ICO)
      5. 9.2.5 Boost Mode Operation from Battery
      6. 9.2.6 Power Path Management
        1. 9.2.6.1Narrow VDC Architecture
        2. 9.2.6.2Dynamic Power Management
        3. 9.2.6.3Supplement Mode
      7. 9.2.7 Battery Charging Management
        1. 9.2.7.1Autonomous Charging Cycle
        2. 9.2.7.2Battery Charging Profile
        3. 9.2.7.3Charging Termination
        4. 9.2.7.4Resistance Compensation (IRCOMP)
        5. 9.2.7.5Thermistor Qualification
          1. 9.2.7.5.1JEITA Guideline Compliance in Charge Mode
          2. 9.2.7.5.2Cold/Hot Temperature Window in Boost Mode
        6. 9.2.7.6Charging Safety Timer
      8. 9.2.8 Battery Monitor
      9. 9.2.9 Status Outputs (PG, STAT, and INT)
        1. 9.2.9.1Power Good Indicator (PG)
        2. 9.2.9.2Charging Status Indicator (STAT)
        3. 9.2.9.3Interrupt to Host (INT)
      10. 9.2.10BATFET (Q4) Control
        1. 9.2.10.1BATFET Disable Mode (Shipping Mode)
        2. 9.2.10.2BATFET Enable (Exit Shipping Mode)
        3. 9.2.10.3BATFET Full System Reset
      11. 9.2.11Current Pulse Control Protocol
      12. 9.2.12Input Current Limit on ILIM
      13. 9.2.13Thermal Regulation and Thermal Shutdown
        1. 9.2.13.1Thermal Protection in Buck Mode
          1. 9.2.13.1.1Thermal Protection in Boost Mode
      14. 9.2.14Voltage and Current Monitoring in Buck and Boost Mode
        1. 9.2.14.1Voltage and Current Monitoring in Buck Mode
          1. 9.2.14.1.1Input Overvoltage (ACOV)
          2. 9.2.14.1.2System Overvoltage Protection (SYSOVP)
        2. 9.2.14.2Voltage and Current Monitoring in Boost Mode
          1. 9.2.14.2.1VBUS Overcurrent Protection
          2. 9.2.14.2.2Boost Mode Overvoltage Protection
      15. 9.2.15Battery Protection
        1. 9.2.15.1Battery Overvoltage Protection (BATOVP)
        2. 9.2.15.2Battery Over-Discharge Protection
        3. 9.2.15.3System Overcurrent Protection
      16. 9.2.16Serial Interface
        1. 9.2.16.1Data Validity
        2. 9.2.16.2START and STOP Conditions
        3. 9.2.16.3Byte Format
        4. 9.2.16.4Acknowledge (ACK) and Not Acknowledge (NACK)
        5. 9.2.16.5Slave Address and Data Direction Bit
        6. 9.2.16.6Single Read and Write
        7. 9.2.16.7Multi-Read and Multi-Write
    3. 9.3Device Functional Modes
      1. 9.3.1Host Mode and Default Mode
    4. 9.4Register Map
      1. 9.4.1 REG00
      2. 9.4.2 REG01
      3. 9.4.3 REG02
      4. 9.4.4 REG03
      5. 9.4.5 REG04
      6. 9.4.6 REG05
      7. 9.4.7 REG06
      8. 9.4.8 REG07
      9. 9.4.9 REG08
      10. 9.4.10REG09
      11. 9.4.11REG0A
      12. 9.4.12REG0B
      13. 9.4.13REG0C
      14. 9.4.14REG0D
      15. 9.4.15REG0E
      16. 9.4.16REG0F
      17. 9.4.17REG10
      18. 9.4.18REG11
      19. 9.4.19REG12
      20. 9.4.20REG13
      21. 9.4.21REG14
  10. 10Application and Implementation
    1. 10.1Application Information
    2. 10.2Typical Application Diagram
      1. 10.2.1Design Requirements
      2. 10.2.2Detailed Design Procedure
        1. 10.2.2.1Inductor Selection
        2. 10.2.2.2Buck Input Capacitor
        3. 10.2.2.3System Output Capacitor
      3. 10.2.3Application Curves
    3. 10.3System Example
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1Layout Guidelines
    2. 12.2Layout Example
  13. 13Device and Documentation Support
    1. 13.1Device Support
      1. 13.1.1Third-Party Products Disclaimer
    2. 13.2Related Links
    3. 13.3Receiving Notification of Documentation Updates
    4. 13.4Community Resources
    5. 13.5Trademarks
    6. 13.6Electrostatic Discharge Caution
    7. 13.7Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Specifications

Absolute Maximum Ratings(1)

over operating free-air temperature range (unless otherwise noted)
MINMAXVALUE
Voltage range (with respect to GND)VBUS (converter not switching)–222V
PMID (converter not switching)–0.322V
STAT–0.320V
PG (bq25898)–0.37V
PSEL (bq25898)–0.37V
VOK (bq25898)–0.37V
DSEL (bq25898D)–0.37V
D+, D– (bq25898D)–0.37V
BTST–0.320V
SW–316V
BAT, SYS (converter not switching)–0.36V
SDA, SCL, INT, OTG, REGN, TS, CE, QON–0.37V
BTST TO SW–0.37V
PGND to GND–0.30.3V
BATSEN–0.37V
ILIM–0.35V
Output sink currentINT, STAT6mA
PG (bq25898)6mA
DSEL (bq25898D)5mA
VOK (bq25898)5mA
Junction temperature–40150°C
Storage temperature range, Tstg–65150°C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to the network ground terminal unless otherwise noted.

ESD Ratings

VALUEUNIT
VESDElectrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)±2000V
Charged device model (CDM), per JEDEC specification JESD22-C101(2)±250V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

Recommended Operating Conditions

MINMAXUNIT
VINInput voltage3.914(1)V
IINInput current (VBUS) 3.25A
ISYSOutput current (SW)4A
VBATBattery voltage4.608V
IBATFast charging current4A
Discharging current with internal MOSFET Up to 6 (continuos)A
9 (peak)
(Up to 1 sec duration)
A
TAOperating free-air temperature range–4085°C
The inherent switching noise voltage spikes should not exceed the absolute maximum rating on either the BTST or SW pins. A tight layout minimizes switching noise.

Thermal Information

THERMAL METRIC(1) bq25898, bq25898DUNIT
YFF (DSBGA)
42-BALL
RθJAJunction-to-ambient thermal resistance 53.5°C/W
RθJCtopJunction-to-case (top) thermal resistance 0.2°C/W
RθJBJunction-to-board thermal resistance 8.2°C/W
ψJTJunction-to-top characterization parameter 0.9°C/W
ψJBJunction-to-board characterization parameter 8.2°C/W
RθJCbotJunction-to-case (bottom) thermal resistance N/A°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

Electrical Characteristics

VVBUS_UVLOZ < VVBUS < VACOV and VVBUS > VBAT + VSLEEP, TJ = –40°C to 125°C and TJ = 25°C for typical values (unless otherwise noted)
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
QUIESCENT CURRENTS
IBAT Battery discharge current (BAT, SW, SYS) in buck modeVBAT = 4.2 V, V(VBUS) < V(UVLO), leakage between BAT and VBUS5µA
High-Z Mode, No VBUS, BATFET Disabled (REG09[5] = 1), Battery Monitor Disabled, TJ < 85°C1223µA
High-Z Mode, No VBUS, BATFET Enabled (REG09[5] = 0), Battery Monitor Disabled, TJ < 85°C3260µA
I(VBUS_HIZ) Input supply current (VBUS) in buck mode when High-Z mode is enabledV(VBUS)= 5 V, High-Z Mode, No Battery, Battery Monitor Disabled1535µA
V(VBUS)= 12 V, High-Z Mode, No Battery, Battery Monitor Disabled2550µA
I(VBUS) Input supply current (VBUS) in buck modeVBUS > V(UVLO), VBUS > VBAT, Converter not switching1.53mA
VBUS > V(UVLO), VBUS > VBAT, Converter switching, VBAT = 3.2V, ISYS = 0A3mA
VBUS > V(UVLO), VBUS > VBAT, Converter switching, VBAT = 3.8 V, ISYS = 0 A3mA
I(BOOST) Battery discharge current in boost modeVBAT = 4.2 V, Boost mode, I(VBUS)= 0 A, Converter switching5mA
VBUS/BAT POWER UP
V(VBUS_OP) VBUS operating range3.914V
V(VBUS_UVLOZ) VBUS for active I2C, no battery3.6V
V(SLEEP) Sleep mode falling threshold 2565120mV
V(SLEEPZ) Sleep mode rising threshold130250370mV
V(ACOV) VBUS over-voltage rising threshold13.914.6V
VBUS over-voltage falling threshold13.313.9V
tACOV_RISINGACOV rising deglitch VVBUS rising 1µs
tACOV_FALLINGACOV falling deglitch VVBUS falling 1ms
VBAT(UVLOZ) Battery for active I2C, no VBUS2.3V
VBAT(DPL) Battery depletion falling threshold2.152.5V
VBAT(DPLZ) Battery depletion rising threshold2.352.7V
V(VBUSMIN) Bad adapter detection threshold3.8V
I(BADSRC) Bad adapter detection current source30mA
POWER-PATH MANAGEMENT
VSYS Typical system regulation voltageI(SYS) = 0 A, VBAT> VSYS(MIN), BATFET Disabled (REG09[5]=1)VBAT+
50 mV
V
Isys = 0 A, VBAT< VSYS(MIN), BATFET Disabled (REG09[5]=1)VSYS(MIN) +
250 mV
V
VSYS(MIN) Minimum DC system voltage output VBAT< VSYS(MIN), SYS_MIN = 3.5 V (REG03[3:1] = 101), ISYS= 0 A3.603.75V
VSYS(MAX) Maximum DC system voltage output VBAT = 4.35 V, SYS_MIN = 3.5 V (REG03[3:1] = 101), ISYS= 0 A4.404.42V
RON(RBFET) Top reverse blocking MOSFET(RBFET) on-resistance between VBUS and PMIDTJ = -40°C - 85°C2840
TJ = -40°C - 125°C2847
RON(HSFET) Top switching MOSFET (HSFET) on-resistance between PMID and SWTJ = -40°C - 85°C2433
TJ = -40°C - 125°C2440
RON(LSFET) Bottom switching MOSFET (LSFET) on-resistance between SW and GNDTJ = -40°C - 85°C1218
TJ = -40°C - 125°C1221
V(FWD)BATFET forward voltage in supplement modeBAT discharge current 10 mA30mV
BATTERY CHARGER
VBAT(REG_RANGE) Typical charge voltage range3.8404.608V
VBAT(REG_STEP) Typical charge voltage step16mV
VBAT(REG) Charge voltage resolution accuracyVBAT = 4.208 V (REG06[7:2] = 010111) or
VBAT = 4.352 V (REG06[7:2] = 100000)
TJ = -40°C - 85°C
-0.5%0.5%
I(CHG_REG_RANGE)Typical fast charge current regulation range04032mA
I(CHG_REG_STEP)Typical fast charge current regulation step64mA
I(CHG_REG_ACC)Fast charge current regulation accuracyVBAT= 3.1 V or 3.8 V, ICHG = 256 mA
TJ = -40°C - 85°C
-20%20%
VBAT= 3.1 V or 3.8 V, ICHG = 1792 mA
TJ = -40°C - 85°C
-5%5%
VBAT(LOWV)Battery LOWV falling thresholdFast charge to precharge, BATLOWV (REG06[1]) = 12.62.82.9V
Battery LOWV rising thresholdPrecharge to fast charge, BATLOWV (REG06[1]) = 1
(Typical 200-mV hysteresis)
2.83.03.15V
Battery LOWV falling thresholdFast charge to precharge, BATLOWV (REG06[1]) = 02.52.62.7V
Battery LOWV rising thresholdPrecharge to fast charge, BATLOWV (REG06[1]) = 0
(Typical 200-mV hysteresis)
2.72.82.9V
I(PRECHG_RANGE)Precharge current range641024mA
I(PRECHG_STEP)Typical precharge current step64mA
I(PRECHG_ACC) Precharge current accuracyVBAT = 2.6 V, IPRECHG = 256 mA–20%20%
I(TERM_RANGE)Termination current range641024mA
I(TERM_STEP)Typical termination current step64mA
I(TERM_ACC) Termination current accuracyITERM = 256 mA, ICHG≤ 1344 mA
TJ = -20°C - 85°C
-20%20%
ITERM = 256 mA, ICHG> 1344 mA
TJ = -20°C - 85°C
-20%20%
V(SHORT)Battery short voltageVBAT falling2.0V
V(SHORT_HYST)Battery short voltage hysteresisVBAT rising200mV
I(SHORT)Battery short currentVBAT < 2.2 V110mA
V(RECHG) Recharge threshold below VBATREG VBAT falling, VRECHG (REG06[0] = 0) = 0100mV
VBAT falling, VRECHG (REG06[0] = 0) = 1200mV
IBAT(LOAD)Battery discharge load currentVBAT = 4.2 V15mA
ISYS(LOAD)System discharge load currentVSYS = 4.2 V30mA
RON(BATFET) SYS-BAT MOSFET (BATFET) on-resistanceTJ = 25°C57
TJ = -40°C - 125°C510
RBATSENBATSEN input resistance800
INPUT VOLTAGE / CURRENT REGULATION
VIN(DPM_RANGE)Typical input voltage regulation range3.915.3V
VIN(DPM_STEP)Typical input voltage regulation step100mV
VIN(DPM_ACC)Input voltage regulation accuracyVINDPM = 4.4 V, 7.8 V, 10.8 V-3%3%
IIN(DPM_RANGE)Typical input current regulation range1003250mA
IIN(DPM_STEP)Typical input current regulation step50mA
IIN(DPM100_ACC)Input current 100mA regulation accuracy
VBAT = 5V, current pulled from SW
IINLIM (REG00[5:0]) = 100 mA8590100mA
IIN(DPM_ACC)Input current regulation accuracy
VBAT = 5V, current pulled from SW
USB150, IINLIM (REG00[5:0]) = 150 mA125135150mA
USB500, IINLIM (REG00[5:0]) = 500 mA440470500mA
USB900, IINLIM (REG00[5:0]) = 900 mA750825900mA
Adapter 1.5 A, IINLIM (REG00[5:0]) = 1500 mA130014001500mA
IIN(START) Input current regulation during system start upVSYS = 2.2 V, IINLIM (REG00[5:0]) ≥ 200 mA200mA
KILIMIINMAX = KILIM/RILIM, Input Current regulation by ILIM pin = 1.5 A290320350A x Ω
VOK (bq25898)/DSEL (bq25898D)
VVOK_OHVoltageVBUS > 6 V I(VOK) = 20 mA and I(REGN) = 30 mA 4.755.25V
VBUS = 5 V I(VOK) = 5 mA and I(REGN) = 30 mA 4.354.8V
VVOK_OLVoltageBattery only VBAT = 3.8 V, I(VOK) = -10 mA 0.4V
VDSEL_OHVoltageI(DSEL) = 20 mA and I(REGN) = 30 mA, VBUS = 5 V1.3V
VDSEL_OLVoltageI(DSEL) = -10 mA and I(REGN) = 30 mA, VBUS = 5 V0.4V
D+/D- DETECTION (bq25898D)
I(10UA_ISRC)D+ connection check current source71014µA
I(100UA_ISINK)D+/D- current sink (100 µA)50100150µA
I(DPDM_LKG)D+/D- Leakage currentD–, switch open–11µA
D+, switch open–11µA
I(1P6MA_ISINK)D+/D- current sink (1.6 mA)1.351.601.75mA
R(D–_DWN)D– pulldown for connection check14.2524.8
VFLOAT_VDPSRCD+/D- Voltage source (HIZ) REG01[7:5] = 000 (default) or REG01[4:2] = 000 (default) HIZV
V0P0_VDSRCD+/D- Voltage source (0 V) REG01[7:5] = 001 or REG01[4:2] = 001 00.15V
V0P6_VDSRCD+/D- Voltage source (0.6 V) REG01[7:5] = 010 or REG01[4:2] = 010 0.50.60.7V
V1P2_DPVSRCD+/D- Voltage source (1.2 V) REG01[7:5] = 011 or REG01[4:2] = 011 1.0751.21.325V
V2P0_DPVSRCD+/D- Voltage source (2.0 V) REG01[7:5] = 100 or REG01[4:2] = 100 1.87522.125V
V2P7_DPVSRCD+/D- Voltage source (2.7 V) REG01[7:5] = 101 or REG01[4:2] = 101 2.5752.72.825V
V3P3_DPVSRCD+/D- Voltage source (3.3 V) REG01[7:5] = 110 or REG01[4:2] = 110 or REG01[4:2] = 111 3.153.33.45V
RDPDM_SHORTD+/D- Short REG01[7:5] = 111 200Ω
V(0P4_VTH)D+/D- low comparator threshold250400mV
V(0P8_VTH)D+ low comparator threshold0.8V
V(2P7_VTH)D+/D- comparator threshold for non-standard adapter detection (Divider 1, 3,or 4)2.552.85V
V(2P0_VTH)D+/D- comparator threshold for non-standard adapter detection (Divider 1, 3)1.852.15V
V(1P2_VTH)D+/D- comparator threshold for non-standard adapter detection (Divider 2)1.051.35V
BAT OVER-VOLTAGE/CURRENT PROTECTION
VBAT(OVP)Battery over-voltage thresholdVBAT rising, as percentage of VBAT(REG)104%
VBAT(OVP_HYST)Battery over-voltage hysteresisVBAT falling, as percentage of VBAT(REG)2%
IBAT(FET_OCP)System over-current threshold9A
THERMAL REGULATION AND THERMAL SHUTDOWN
TREGJunction temperature regulation accuracyREG08[1:0] = 11120°C
TSHUT Thermal shutdown rising temperatureTemperature rising160°C
TSHUT(HYS) Thermal shutdown hysteresisTemperature falling30°C
JEITA THERMISTOR COMPARATOR (BUCK MODE)
V(T1) T1 (0°C) threshold, charge suspended T1 below this temperature.As percentage to V(REGN)72.75%73.25%73.75%
V(T1_HYS) Charge back to ICHG/2 (REG04[6:0]) and VREG (REG06[7:2]) above this temperature.As Percentage to V(REGN)1.4%
V(T2) T2 (10°C) threshold, charge back to ICHG/2 (REG04[6:0]) and VREG (REG06[7:2]) below this temperature. As Percentage to V(REGN)67.75%68.25%68.75%
V(T2_HYS) Charge back to ICHG (REG04[6:0]) and VREG (REG06[7:2]) above this temperature. As Percentage to V(REGN)1.4%
V(T3) T3 (45°C) threshold,charge back to ICHG (REG04[6:0]) and VREG-200mV (REG06[7:2]) above this temperature. As percentage to V(REGN)44.25v44.75%45.25%
V(T3_HYS) Charge back to ICHG (REG04[6:0]) and VREG (REG06[7:2]) below this temperature. As Percentage to V(REGN)1%
V(T5) T5 (60°C) threshold, charge suspended above this temperature. As Percentage to V(REGN)33.875%34.375%34.875%
V(T5_HYS) Charge back to ICHG (REG04[6:0]) and VREG-200mV (REG06[7:2]) below this temperature. As Percentage to V(REGN)1.25%
COLD/HOT THERMISTOR COMPARATOR (BOOST MODE)
V(BCOLD1)Cold temperature threshold 1, TS pin voltage rising thresholdAs percentage to VREGN REG01[5] = 1
(Approx. -20°C w/ 103AT)
79.5%80%80.5%
V(BCOLD1_HYS)Cold temperature threshold 1, TS pin voltage falling thresholdAs percentage to VREGN REG01[5] = 1 1%
V(BHOT2)Hot temperature threshold 2, TS pin voltage falling thresholdAs percentage to VREGN REG01[7:6] = 10
(Approx. 65°C w/ 103AT)
30.75%31.25%31.75%
V(BHOT2_HYS)Hot temperature threshold 2, TS pin voltage rising thresholdAs percentage to VREGN REG01[7:6] = 10 3%
PWM
FSW PWM switching frequency, and digital clockOscillator frequency 1.321.68MHz
DMAX Maximum PWM duty cycle97%
BOOST MODE OPERATION
V(OTG_REG_RANGE) Typical boost mode regulation voltage range4.555.55V
V(OTG_REG_STEP) Typical boost Mode Regulation voltage step64mV
V(OTG_REG_ACC) Boost mode regulation voltage accuracyI(VBUS) = 0 A, BOOSTV = 4.998 V (REG0A[7:4] = 0111) -3%3%
V(OTG_BAT) Battery voltage exiting boost modeBAT falling, REG03[0] = 02.72.9V
BAT falling, REG03[0] = 12.42.6V
I(OTG) Typical boost mode output current range0.52.45A
I(OTG_OCP_ACC) Boost mode RBFET over-current protection accuracy BOOST_LIM = 1.5 A (REG0A[2:0] = 100)1.52.0A
V(OTG_OVP)Boost mode over-voltage thresholdRising threshold5.86V
REGN LDO
V(REGN)REGN LDO output voltageV(VBUS) = 9 V, I(REGN) = 40 mA5.666.4V
V(VBUS) = 5 V, I(REGN) = 20 mA4.74.8V
I(REGN)REGN LDO current limitV(VBUS) = 9 V, V(REGN) = 3.8 V50mA
ANALOG-TO-DIGITAL CONVERTER (ADC)
RESResolutionRising threshold7bits
VBAT(RANGE)Typical battery voltage rangeV(VBUS) > VBAT + V(SLEEP) or OTG mode is enabled2.3044.848V
V(VBUS) < VBAT + V(SLEEP) and OTG mode is disabledVSYS_MIN4.848V
V(BAT_RES)Typical battery voltage resolution20mV
V(SYS_RANGE)Typical system voltage rangeV(VBUS) > VBAT + V(SLEEP) or OTG mode is enabled2.3044.848V
V(VBUS) < VBAT + V(SLEEP) and OTG mode is disabledVSYS_MIN4.848V
V(SYS_RES)Typical system voltage resolution20mV
V(VBUS_RANGE)Typical VVBUS voltage rangeV(VBUS) > VBAT + V(SLEEP) or OTG mode is enabled2.615.3V
V(VBUS_RES)Typical VVBUS voltage resolution100mV
IBAT(RANGE)Typical battery charge current rangeV(VBUS) > VBAT + V(SLEEP) and VBAT > VBAT(SHORT)04.032A
IBAT(RES)Typical battery charge current resolution50mA
V(TS_RANGE)Typical TS voltage range21%80%
V(TS_RES)Typical TS voltage resolution0.47%
LOGIC I/O PIN (OTG, CE, PSEL, QON)
VIH Input high threshold level1.3V
VIL Input low threshold level0.4V
IIN(BIAS) High level leakage currentPull-up rail 1.8 V1µA
V(QON) Internal /QON pull-upBattery only modeBATV
V(VBUS) = 9 V5.8V
V(VBUS) = 5 V4.3V
R(QON) Internal /QON pull-up resistance200
LOGIC I/O PIN (INT, STAT, PG)
VOL Output low threshold levelSink Current = 5 mA, Sink current0.4V
IOUT_BIAS High level leakage currentPull-up rail 1.8 V1µA
I2C INTERFACE (SCL, SDA)
VIH Input high threshold level, SCL and SDAPull-up rail 1.8 V1.3V
VIL Input low threshold levelPull-up rail 1.8 V0.4V
VOL Output low threshold levelSink Current = 5 mA, Sink current0.4V
IBIAS High level leakage currentPull-up rail 1.8 V1µA

Timing Requirements

MINNOMMAXUNIT
VBUS/BAT POWER UP
tBADSRCBad adapter detection duration30msec
BAT OVER-VOLTAGE PROTECTION
tBATOVPBattery over-voltage deglitch time to disable charge1µs
BATTERY CHARGER
tRECHGRecharge deglitch time20msec
Current Pulse Control
tPUMPX_STOPCurrent pulse control stop pulse430570msec
tPUMPX_ON1Current pulse control long on pulse240360msec
tPUMPX_ON2Current pulse control short on pulse70130msec
tPUMPX_OFFCurrent pulse control off pulse70130msec
tPUMPX_DLYCurrent pulse control stop start delay80225msec
BATTERY MONITOR
tCONVConversion timeCONV_RATE(REG02[6]) = 081000msec
QON and SHIPMODE TIMING
tSHIPMODEQON low time to turn on BATFET and exit ship modeTJ = -10°C - 60°C0.81.3sec
tQON_RSTQON low time to enable full system resetTJ = -10°C - 60°C15.523sec
tBATFET_RSTBATFET off time during full system resetTJ = -10°C - 60°C250400msec
tSM_DLYEnter ship mode delayTJ = -10°C - 60°C1015sec
I2C INTERFACE
fSCLSCL clock frequency400KHz
DIGITAL CLOCK and WATCHDOG TIMER
fLPDIGDigital low power clock REGN LDO disabled183045KHz
fDIGDigital clockREGN LDO enabled132015001680KHz
tWDTWatchdog reset timeWATCHDOG (REG07[5:4])=11, REGN LDO disabled100160sec
WATCHDOG (REG07[5:4])=11, REGN LDO enabled136160sec

Typical Characteristics

bq25898 bq25898D D001_slusca6.gif
VBAT = 3.8 V DCR = 10 mΩ
Figure 1. Charge Efficiency vs Charge Current
bq25898 bq25898D D003_slusca6.gif
Figure 3. Boost Mode Efficiency vs VBUS Load Current
bq25898 bq25898D D005_slusca6.gif
VBAT = 2.6 VVBUS = 5 V SYSMIN = 3.5 V
Figure 5. SYS Voltage Regulation vs System Load Current
bq25898 bq25898D D007_slusca6.gif
VBUS = 5 V
Figure 7. BAT Voltage vs Temperature
bq25898 bq25898D D009_slusca6.gif
Figure 9. Charge Efficiency
bq25898 bq25898D D002_slusca6.gif
Figure 2. System Light Load Efficiency vs System Light Load Current
bq25898 bq25898D D004_slusca6.gif
VBUS = 5 V
Figure 4. Charge Current Accuracy vs Charge Current I2C Setting
bq25898 bq25898D D006_slusca6.gif
VBAT = 4.2 V
Figure 6. SYS Voltage Regulation vs System Load Current
bq25898 bq25898D D008_slusca6.gif
Figure 8. Input Current Limit vs Temperature
bq25898 bq25898D D010_slusca6.gif
Figure 10. Charge Voltage Accuracy